JP2006270065A - Circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit device capable of suppressing its deformation while suppressing an insulating layer from peeling off a substrate. <P>SOLUTION: The circuit device comprises a resin layer 2 formed on a substrate 1, fillers 20a, 20b, and 20c filling the resin layer 2, a conductive layer 3 formed on the resin layer 2, and an LSI chip 9 formed on the conductive layer 3. The average particle size of the fillers 20a, 20b, and 20c filling the resin layer 2 is controlled so that young' module at the part positioned on the substrate 1 side of the resin layer 2 is smaller than that positioned on the side opposite to the substrate 1 of the resin layer 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a circuit device, and more particularly to a circuit device including a circuit element.

  2. Description of the Related Art In recent years, circuit devices included in electronic devices and the like have increased in heat generation density per unit volume in order to reduce size, increase density, and increase functionality. Therefore, in recent years, a metal substrate having high heat dissipation is used as a substrate of a circuit device, and an IC (Integrated Circuit) or an LSI (Large Scale Integrated Circuit) is used on the metal substrate. Are mounted (for example, refer to Patent Document 1). Conventionally, a structure in which a hybrid IC (Hybrid Integrated Circuit) is formed on a metal substrate is also known. Here, the hybrid IC means a circuit device in which circuit elements such as an IC chip, a capacitor, and a resistor are integrated on one substrate.

FIG. 22 is a cross-sectional view schematically showing the structure of a conventional circuit device disclosed in Patent Document 1. In FIG. Referring to FIG. 22, in the conventional circuit device, a resin layer 102 that functions as an insulating layer and is added with silica (SiO ₂ ) as a filler is formed on a metal substrate 101 made of aluminum. . An IC chip 104 is attached to a predetermined region on the resin layer 102 via an adhesive layer 103 made of resin. A metal wiring 105 made of copper is formed through an adhesive layer 103 in a region on the resin layer 102 that is spaced from the end of the IC chip 104 by a predetermined distance. The metal wiring 105 and the metal substrate 101 are insulated by the resin layer 102. The metal wiring 105 and the IC chip 104 are electrically connected by a wire 106.

  In the conventional circuit device shown in FIG. 22, a large amount of heat is generated from the IC chip 104 by using the metal substrate 101 made of aluminum and mounting the IC chip 104 on the metal substrate 101 via the resin layer 102. Even if this occurs, the heat can be dissipated by the metal substrate 101.

JP-A-8-288605

  However, in the conventional circuit device shown in FIG. 22, since the thermal expansion coefficient of the resin layer 102 is smaller than the thermal expansion coefficient of the metal substrate 101, when the metal substrate 101 expands due to the heat generated in the IC chip 104. There is a disadvantage that the metal substrate 101 under the resin layer 102 is deformed so as to be warped. As a result, there is a problem that the circuit device is deformed.

  Accordingly, in order to solve the above-described problems, it is conceivable to suppress deformation of the metal substrate 101 under the resin layer 102 by increasing the rigidity (Young's modulus) of the entire resin layer 102. However, when the rigidity (Young's modulus) of the entire resin layer 102 is increased, shear generated between the metal substrate 101 and the resin layer 102 when the metal substrate 101 expands due to heat generated in the IC chip 104. Since the stress increases, there is a problem that the resin layer 102 is easily peeled from the metal substrate 101.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to suppress the deformation of the circuit device while suppressing the insulating layer from peeling from the substrate. It is to provide a possible circuit device.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a circuit device according to one aspect of the present invention includes a substrate, an insulating layer formed on the substrate, a filler filled in the insulating layer, and a conductive material formed on the insulating layer. And a circuit element formed on the conductive layer. The average particle size of the filler filled in the insulating layer is such that the Young's modulus of the portion located on the substrate side of the insulating layer is smaller than the Young's modulus of the portion located on the opposite side of the substrate of the insulating layer. It is controlled.

  In the circuit device according to this aspect, as described above, the insulating layer is insulated so that the Young's modulus of the portion located on the substrate side of the insulating layer is smaller than the Young's modulus of the portion located on the side opposite to the substrate of the insulating layer. By controlling the average particle size of the filler filled in the layer, the rigidity of the portion of the insulating layer on the substrate side can be made smaller than the rigidity of the portion of the insulating layer on the side opposite to the substrate. Thus, even when the insulating layer formed on the substrate is pulled by the thermally expanded substrate when the substrate is expanded by the heat generated in the circuit element, the Young's modulus (rigidity) of the insulating layer on the substrate side is small. Since the portion is deformed so as to extend together with the substrate, the shear stress generated between the substrate and the insulating layer can be reduced. As a result, peeling of the insulating layer from the substrate can be suppressed. Even if the substrate expands due to the heat generated by the circuit element, the Young's modulus (rigidity) of the portion located on the opposite side of the insulating layer from the substrate is large, so that the substrate under the insulating layer is deformed to be warped. Can be suppressed. Thereby, it can suppress that a circuit device deform | transforms.

  In the circuit device according to the aforementioned aspect, the insulating layer is composed of one layer, and the Young's modulus of the portion located on the substrate side of the insulating layer composed of one layer is opposite to the substrate of the insulating layer composed of one layer. It may be smaller than the Young's modulus of the portion located on the side. If comprised in this way, the shear stress which generate | occur | produces between a board | substrate and an insulating layer can be easily made small by the part with small Young's modulus (rigidity) located in the board | substrate side of the insulating layer which consists of one layer. In addition, it is possible to suppress the substrate under the insulating layer from being warped and deformed by a portion having a large Young's modulus (rigidity) located on the opposite side to the substrate of the insulating layer formed of one layer.

  In the circuit device according to the aforementioned aspect, the insulating layer includes a first insulating layer having a first Young's modulus formed on the substrate and a second insulating layer formed on the surface of the first insulating layer opposite to the substrate. A second insulating layer having a Young's modulus, and the first Young's modulus of the first insulating layer is smaller than the second Young's modulus of the second insulating layer. If comprised in this way, the shear stress which generate | occur | produces between a board | substrate and an insulating layer (1st insulating layer) can be easily made small by the 1st insulating layer which has small 1st Young's modulus (rigidity). In addition, the second insulating layer having a large second Young's modulus (rigidity) can prevent the substrate under the insulating layer (first insulating layer) from being warped and deformed. The insulating layer includes a first insulating layer having a small first Young's modulus formed on the substrate and a second second Young's modulus having a large second Young's modulus formed on the surface of the first insulating layer opposite to the substrate. By including the two insulating layers, the Young's modulus (rigidity) of the insulating layer on the substrate side (first insulating layer) can be easily set to the portion of the insulating layer opposite to the substrate (second It can be made smaller than the Young's modulus (rigidity) of the insulating layer.

  In this case, preferably, the first insulating layer is filled with a filler corresponding to each of a plurality of different average particle diameters, and the second insulating layer has a plurality of different average particle diameters. The filler corresponding to each of these is filled. If comprised in this way, for example, a predetermined filler and the filler corresponding to the average particle diameter smaller than the average particle diameter of the predetermined filler can be used so that the predetermined filler cannot enter. Since the gap can be filled with the filler corresponding to the small average particle diameter, the filling rate of the filler in the first insulating layer (second insulating layer) can be increased. In this case, if the filler filled in the first insulating layer (second insulating layer) is made of a material capable of increasing the thermal conductivity of the first insulating layer (second insulating layer), the first The heat dissipation of the insulating layer (second insulating layer) can be improved. In order to increase the filling rate of the filler in the first insulating layer (second insulating layer), the mixing ratio of the filler corresponding to the large average particle diameter and the filler corresponding to the small average particle diameter is set. , 8: 2 is preferable.

  In the configuration in which the first insulating layer (second insulating layer) is filled with a filler corresponding to each of a plurality of different average particle diameters, preferably the largest of the fillers filled in the insulating layer The filler corresponding to the average particle diameter is not filled in the first insulating layer, but is filled in the second insulating layer. If comprised in this way, the Young's modulus (rigidity) of a 1st insulating layer can be easily made smaller than the Young's modulus (rigidity) of a 2nd insulating layer.

  In the configuration in which the first insulating layer (second insulating layer) is filled with a filler corresponding to each of a plurality of different average particle diameters, preferably the smallest of the fillers filled in the insulating layer The filler corresponding to the average particle diameter is filled in both the first insulating layer and the second insulating layer. If comprised in this way, the filling rate of the filler with which both a 1st insulating layer and a 2nd insulating layer are filled can be made high easily.

  In the configuration in which the insulating layer is composed of one layer, the insulating layer may be filled with a filler corresponding to each of a plurality of different average particle diameters. If comprised in this way, for example, a predetermined filler and the filler corresponding to the average particle diameter smaller than the average particle diameter of the predetermined filler can be used so that the predetermined filler cannot enter. Since the gap can be filled with the filler corresponding to the small average particle diameter, the filling rate of the filler in the insulating layer can be increased. In this case, if the filler filled in the insulating layer is made of a material capable of increasing the thermal conductivity of the insulating layer, the heat dissipation of the insulating layer can be improved.

  Further, in the configuration in which the insulating layer consisting of the one layer is filled with fillers corresponding to each of a plurality of different average particle diameters, the average of the fillers filled in the portion located on the substrate side of the insulating layer The particle size may be smaller than the average particle size of the filler filled in the portion located on the opposite side of the insulating layer from the substrate. If comprised in this way, the Young's modulus (rigidity) of the part by the side of the board | substrate of an insulating layer can be easily made smaller than the Young's modulus (rigidity) of the part on the opposite side to the board | substrate of an insulating layer.

  In this case, the filler filled in the insulating layer may be distributed so that the average particle diameter of the filler decreases from the conductive layer side toward the substrate side. According to this configuration, the Young's modulus (rigidity) of the intermediate portion of the insulating layer is set so that the Young's modulus (rigidity) of the portion located on the substrate side of the insulating layer is equal to the Young's modulus of the portion located on the opposite side of the insulating layer substrate. The size can be between the rate (stiffness). As a result, the intermediate portion of the insulating layer can reduce the shear stress generated between the portion of the insulating layer located on the substrate side and the portion of the insulating layer located on the opposite side of the substrate. It is possible to suppress cracks from occurring.

  Further, in the configuration in which the insulating layer is composed of one layer, an opening having a depth reaching the surface of the substrate is formed in a region corresponding to the lower portion of the circuit element of the insulating layer. The layer may be formed in contact with the surface of the substrate through the opening of the insulating layer. According to this structure, when a large amount of heat is generated from the circuit element, the heat can be radiated to the substrate side through the conductive layer in contact with the surface of the substrate. Thereby, the heat dissipation of a circuit device can be improved.

  Further, in the configuration in which the first insulating layer (second insulating layer) is filled with a filler corresponding to each of a plurality of different types of average particle diameters, the filler filled in the second insulating layer is the first A first filler corresponding to the average particle size, a second filler corresponding to a second average particle size smaller than the first average particle size, and a size between the first average particle size and the second average particle size And at least a third filler corresponding to the third average particle diameter. If comprised in this way, when the difference of the 1st average particle diameter of a 1st filler and the 2nd average particle diameter of a 2nd filler is large, it is between 1st average particle diameter and 2nd average particle diameter. By further adding a third filler corresponding to the third average particle size having the size of γ, it is possible to suppress a decrease in the filling rate of the filler in the second insulating layer.

  Further, in the configuration in which the insulating layer includes the first insulating layer and the second insulating layer, the conductive layer includes a first conductive layer formed between the first insulating layer and the second insulating layer, and a second insulating layer. A first opening having a depth reaching the surface of the substrate is formed in a region corresponding to the lower part of the circuit element of the first insulating layer, and a second conductive layer formed on the layer. A second opening having a depth reaching the surface of the first conductive layer is formed in a region of the second insulating layer corresponding to the lower portion of the circuit element. A first heat radiating portion formed to contact the surface of the substrate through the one opening, and the second conductive layer is in contact with the surface of the first conductive layer through the second opening of the second insulating layer; The 2nd thermal radiation part formed so that it may be included may be included. With this configuration, when a large amount of heat is generated from the circuit element in the case where the insulating layer has a two-layer structure, the heat contacts the surface of the substrate from the second heat radiation portion of the second conductive layer. Since it can transmit to the 1st thermal radiation part of 1 conductive layer, the thermal radiation to the board | substrate side can be performed easily. Thereby, when the insulating layer has a two-layer structure, the heat dissipation of the circuit device can be improved.

  In the configuration in which the conductive layer includes a first conductive layer and a second conductive layer, the first conductive layer includes a first wiring portion in addition to the first heat dissipation portion, and the second conductive layer includes a second conductive layer. In addition to the heat dissipation part, a second wiring part may be included. If comprised in this way, the 1st wiring part of a 1st conductive layer and the 2nd wiring part of a 2nd conductive layer can be insulated by a 2nd insulating layer. As a result, even if the first wiring portion of the first conductive layer and the second wiring portion of the second conductive layer intersect with each other in plan view, the first wiring portion of the first conductive layer and the second conductive layer It is possible to suppress an electrical short circuit with the second wiring portion. As a result, the degree of freedom of wiring routing can be improved and the wiring density can be improved.

  Moreover, in the structure in which the said insulating layer contains a 1st insulating layer and a 2nd insulating layer, the 1st insulating layer and the 2nd insulating layer may have the same material as a main component. If comprised in this way, the 1st Young's modulus of a 1st insulating layer can be easily made into 2nd by controlling the average particle diameter of each filler with which a 1st insulating layer and a 2nd insulating layer are filled. It can be made smaller than the second Young's modulus of the insulating layer.

  In the circuit device according to the above aspect, the insulating layer may include an insulating layer containing a resin as a main component. With this configuration, in a circuit device in which an insulating layer mainly composed of a resin is formed on a substrate, the insulating layer can be easily prevented from peeling from the substrate, and the circuit device can be deformed. (Suppressing the substrate) can be suppressed.

  In this case, the filler may be made of a material that can increase the thermal conductivity of the insulating layer. If comprised in this way, since the heat conductivity of the insulating layer which has resin as a main component becomes high, the heat dissipation of the insulating layer which has resin as a main component can be improved.

  In the circuit device according to the above aspect, the substrate may include a substrate mainly made of metal. If comprised in this way, the heat | fever which generate | occur | produced in the circuit element can be efficiently radiated with the board | substrate which has a metal as a main component.

  In the circuit device according to the aforementioned aspect, the substrate may have an uneven surface. If comprised in this way, since the contact area of a board | substrate and an insulating layer can be increased, the adhesiveness between a board | substrate and an insulating layer can be improved. Thereby, it can suppress more that an insulating layer peels from a board | substrate.

  In the circuit device according to the aforementioned aspect, the substrate is formed on the first layer having the first thermal expansion coefficient and the first thermal expansion coefficient different from the first thermal expansion coefficient of the first layer. A second layer having a second thermal expansion coefficient, and a third layer formed on the second layer and having a third thermal expansion coefficient different from the second thermal expansion coefficient of the second layer. Also good. If comprised in this way, by adjusting the thickness of a 1st layer, a 2nd layer, and a 3rd layer, the thermal expansion coefficient of the board | substrate containing a 1st layer, a 2nd layer, and a 3rd layer Can be controlled. In this case, if the thickness of the first layer to the third layer is adjusted so that the thermal expansion coefficient of the substrate approaches both the thermal expansion coefficient of the circuit element and the thermal expansion coefficient of the insulating layer, the substrate, the circuit element, and The insulating layer can be prevented from peeling from the substrate due to the difference in thermal expansion coefficient with the insulating layer.

  In the circuit device according to the aforementioned aspect, the surface of the substrate may be oxidized or nitrided. If comprised in this way, even if the insulation of the insulating layer located between a board | substrate and a conductive layer deteriorates, since the oxidized or nitrided surface part of a board | substrate functions as an insulating layer, a board | substrate, a conductive layer, and It can suppress that the withstand voltage between these falls.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a perspective view showing the structure of a hybrid integrated circuit device (hybrid IC) according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line 100-100 in FIG. FIG. 3 is a schematic diagram showing the distribution of the filler filled in the resin layer of the hybrid integrated circuit device according to the first embodiment shown in FIG. First, the structure of the hybrid integrated circuit device according to the first embodiment will be described with reference to FIGS.

  In the hybrid integrated circuit device according to the first embodiment, as shown in FIG. 2, a substrate 1 having a multilayer structure (three-layer structure) having a thickness of about 100 μm to about 3 mm (for example, about 1.5 mm) is used. The substrate 1 was formed on a lower metal layer 1a made of copper, an intermediate metal layer 1b made of an Fe—Ni alloy (so-called Invar alloy) formed on the lower metal layer 1a, and an intermediate metal layer 1b. The upper metal layer 1c made of copper is composed of a clad material laminated. The lower metal layer 1a and the upper metal layer 1c made of copper have a thermal expansion coefficient of about 12 ppm / ° C. The intermediate metal layer 1b made of an Invar alloy is made of an alloy containing about 36% of Ni in Fe and has a small thermal expansion coefficient of about 0.2 ppm / ° C. to about 5 ppm / ° C. That is, the thermal expansion coefficient (about 0.2 ppm / ° C. to about 5 ppm / ° C.) of the intermediate metal layer 1b is smaller than the thermal expansion coefficients (about 12 ppm / ° C.) of the lower metal layer 1a and the upper metal layer 1c. The thickness ratio of the lower metal layer 1a, the intermediate metal layer 1b, and the upper metal layer 1c is 1: 1: 1, and the thermal expansion coefficient of the substrate 1 is about 6 ppm / ° C. to about 8 ppm / ° C. It has been adjusted.

  Moreover, in 1st Embodiment, the copper oxide which has thickness of about 0.1 micrometer-about 0.3 micrometer in the surface part of the uppermost metal layer 1c of the uppermost surface among three layers (1a-1c) which comprise the board | substrate 1. A film 1d is formed. The copper oxide film 1d is formed by oxidizing the surface portion of the upper metal layer 1c. Moreover, in 1st Embodiment, the surface of the board | substrate 1 (copper oxide film 1d) is formed in the uneven | corrugated shape whose arithmetic mean roughness Ra is about 10 micrometers-about 20 micrometers.

  On the uneven surface of the substrate 1 (copper oxide film 1d), a first resin layer 2 mainly composed of an epoxy resin having a thickness of about 60 μm to about 160 μm is formed. This resin layer 2 functions as an insulating layer. The thermal expansion coefficient of the resin layer 2 is about 17 ppm / ° C. to about 18 ppm / ° C. The resin layer 2 is an example of the “insulating layer” in the present invention.

Here, in the first embodiment, as shown in FIG. 3, in order to increase the thermal conductivity of the resin layer 2 mainly composed of an epoxy resin, filling corresponding to each of three different average particle diameters. The materials 20a, 20b and 20c are filled in the resin layer 2. Examples of the constituent material of the filler that can increase the thermal conductivity of the resin layer 2 include alumina (Al ₂ O ₃ ), silica (SiO ₂ ), aluminum nitride (AlN), silicon nitride (SiN), and boron nitride. (BN). The thermal conductivity of an epoxy resin filled with about 85% of a filler such as alumina or silica is about 3 W / (m · K), and the thermal conductivity of an epoxy resin without added filler (about about It is higher than 0.6 W / (m · K)).

  The average particle diameters of the fillers 20a, 20b and 20c filled in the resin layer 2 are set to about 1 μm, about 10 μm and about 20 μm, respectively. For example, the filler 20b having an average particle diameter of about 10 μm refers to a filler having an average particle diameter of about 10 μm and an error within a range of about ± 10%. Further, inside the resin layer 2, a layer containing only the filler 20a (average particle size: about 1 μm), a layer containing only the filler 20b (average particle size: about 10 μm), and a filler 20c (average particle size: about 20 μm) are disposed in this order from the substrate 1 (see FIG. 2) side. Moreover, the weight filling rate of the fillers 20a to 20c filled in the resin layer 2 is about 60% to about 90% in total.

And in 1st Embodiment, the rigidity (Young's modulus) of the part located in the board | substrate 1 (refer FIG. 2) side of the insulating layer 2 is comprised by the resin layer 2 as mentioned above, and the board | substrate of the insulating layer 2 It is lower than the rigidity (Young's modulus) of the part located on the opposite side to 1. Specifically, inside the resin layer 2, a layer containing a filler 20a (average particle size: about 1 μm), a layer containing a filler 20b (average particle size: about 10 μm), and a filler 20c (average particle size: The Young's modulus of the layer containing about 20 μm is about 0.5 × 10 ¹⁰ Pa, about 0.7 × 10 ¹⁰ Pa and about 10 × 10 ¹⁰ Pa, respectively.

  In the first embodiment, as shown in FIG. 2, five via holes having a diameter of about 70 μm and penetrating the resin layer 2 are provided in a predetermined region of the resin layer 2 located below the LSI chip 9 described later. 2a is formed. Further, two via holes 2b having a diameter of about 70 μm and penetrating the resin layer 2 are formed in a predetermined region of the resin layer 2 located below the chip resistor 10 described later. In a predetermined region on the resin layer 2, a first conductive layer 3 made of copper having a thickness of about 15 μm and including thermal via portions 3a and 3b and a wiring portion 3c is formed. The thermal via portion 3 a of the conductive layer 3 is disposed in a region below the LSI chip 9 and has a portion embedded in the via hole 2 a so as to contact the surface of the substrate 1. Further, the thermal via portion 3 b is embedded in a via hole 2 b located in a region below the chip resistor 10. The thermal via portions 3 a and 3 b of the conductive layer 3 have a function of radiating heat to the substrate 1. The thermal conductivity of the resin layer 2 with the conductive layer 3 buried in the via holes 2a and 2b is about 6 W / (m · K) to about 8 W / (m · K). Further, the wiring portion 3c of the conductive layer 3 is disposed in a region spaced a predetermined distance from the end portion of the thermal via portion 3a.

  In the first embodiment, the second resin layer 4 having the same thickness and composition as the first resin layer 2 is formed so as to cover the conductive layer 3. A second conductive layer 5 made of copper having the same thickness as the first conductive layer 3 is formed in the predetermined region. The second resin layer 4 and the conductive layer 5 have a structure for transferring heat to the thermal via portion 3 a of the first conductive layer 3. The resin layer 4 is an example of the “insulating layer” in the present invention.

  Specifically, five via holes 4 a having a diameter of about 70 μm and penetrating the resin layer 4 are formed in a region located below the LSI chip 9 of the resin layer 4. The five via holes 4a are respectively formed at positions corresponding to the five via holes 2a. In the resin layer 4, two via holes 4 b having a diameter of about 70 μm and penetrating the resin layer 4 are formed in a region corresponding to the wiring portion 3 c of the conductive layer 3. Conductive layer 5 includes thermal via portion 5a, wire bonding portion 5b, and wiring portions 5c and 5d. The thermal via portion 5a of the conductive layer 5 is disposed in a region below the LSI chip 9, and is a portion embedded in the via hole 4a so as to contact the surface of the thermal via portion 3a of the conductive layer 3. Have The thermal via portion 5a of the conductive layer 5 has a function of transferring heat generated in the LSI chip 9 to the thermal via portion 3a of the conductive layer 3 to dissipate heat. The wire bonding portion 5b of the conductive layer 5 is disposed in a region corresponding to the via hole 4b, and has a portion embedded in the via hole 4b so as to contact the surface of the wiring portion 3c of the conductive layer 3. . The wiring portion 5 c of the conductive layer 5 is disposed in a region below the chip resistor 10. The wiring portion 5d of the conductive layer 5 is disposed in a region below the lead 11 described later. Although not shown, the wiring portion 5d of the second conductive layer 5 is disposed so as to intersect the wiring portion 3c of the first conductive layer 3 when viewed in plan.

Also, a solder resist layer 6a having an opening in a region corresponding to the wire bonding portion 5b and the wiring portions 5c and 5d of the conductive layer 5 is formed so as to cover the conductive layer 5. The solder resist layer 6 a functions as a protective film for the conductive layer 5. The solder resist layer 6a is made of a thermosetting resin such as a melamine derivative, a liquid crystal polymer, an epoxy resin, a PPE (polyphenylene ether) resin, a polyimide resin, a fluororesin, a phenol resin, and a polyamide bismaleimide. In addition, since a liquid crystal polymer, an epoxy resin, and a melamine derivative are excellent in a high frequency characteristic, they are preferable as a material of the soldering resist layer 6a. Further, the solder resist layer 6a, it may be added a filler such as SiO _2. The LSI chip 9 is mounted on the solder resist layer 6a on the thermal via portion 5a of the conductive layer 5 via a resin layer 6 made of an epoxy resin having a thickness of about 20 μm. The LSI chip 9 uses a single crystal silicon substrate (not shown) and has a thermal expansion coefficient of about 4 ppm / ° C. The LSI chip 9 is electrically connected to the wire bonding portion 5 b of the conductive layer 5 by a wire 7. The chip resistor 10 is mounted on the wiring portion 5c of the conductive layer 5 via a fusion layer 8a made of a brazing material such as solder, and is electrically connected to the wiring portion 5c by the fusion layer 8a. Has been. The LSI chip 9 and the chip resistor 10 are examples of the “circuit element” in the present invention. The lead 11 is mounted on the wiring portion 5d of the conductive layer 5 via a fusion layer 8b made of a solder material such as solder, and is electrically connected to the wiring portion 5d by the fusion layer 8b. ing.

  Further, as shown in FIGS. 1 and 2, in order to protect the LSI chip 9 and the chip resistor 10 mounted inside the apparatus, a resin layer made of an epoxy resin so as to cover the LSI chip 9 and the chip resistor 10 12 is formed. Further, as shown in FIG. 1, a plurality of leads 11 are provided on one side of the hybrid integrated circuit device.

  In the first embodiment, as described above, the average particle diameters of the fillers 20a, 20b, and 20c filled in the resin layer 2 mainly composed of epoxy resin are set to about 1 μm, about 10 μm, and about 20 μm, respectively. In addition, inside the resin layer 2, a layer containing the filler 20a (average particle size: about 1 μm), a layer containing the filler 20b (average particle size: about 10 μm), and a filler 20c (average particle size: about 20 μm). ) In this order from the substrate 1 side, the Young's modulus (rigidity) of the portion of the resin layer 2 on the substrate 1 side is changed to the Young's modulus of the portion of the resin layer 2 opposite to the substrate 1. It can be made smaller than (rigidity). As a result, when the substrate 1 expands due to heat generated by the LSI chip 9 and the chip resistor 10, even if the resin layer 2 formed on the substrate 1 is pulled by the thermally expanded substrate 1, Since the portion having a small Young's modulus (rigidity) on the substrate 1 side is deformed so as to extend together with the substrate 1, the shear stress generated between the substrate 1 and the resin layer 2 can be reduced. As a result, peeling of the resin layer 2 from the substrate 1 can be suppressed. Even if the substrate 1 expands due to heat generated by the LSI chip 9 and the chip resistor 10, the Young's modulus (rigidity) of the portion of the resin layer 2 located on the opposite side of the substrate 1 is large. It can suppress that the board | substrate 1 deform | transforms so that it may curve. Thereby, it can suppress that a hybrid integrated circuit device deform | transforms.

  In the first embodiment, as described above, a layer containing the filler 20a (average particle diameter: about 1 μm) and the filler 20b (average particle diameter: about 10 μm) are contained in the first resin layer 2. And the layer containing the filler 20c (average particle diameter: about 20 μm) are arranged in this order from the substrate 1 side, whereby the Young's modulus (rigidity) of the intermediate portion of the resin layer 2 is reduced. The size can be set between the Young's modulus (rigidity) of the portion located on the substrate 1 side and the Young's modulus (rigidity) of the portion located on the opposite side of the resin layer 2 from the substrate 1. Thereby, the shearing stress generated between the portion of the resin layer 2 located on the substrate 1 side and the portion of the resin layer 2 located on the opposite side of the substrate 1 can be reduced by the intermediate portion of the resin layer 2. Therefore, it is possible to suppress the occurrence of cracks in the first resin layer 2. Since the second resin layer 4 has the same structure as that of the first resin layer 2, the second resin layer 4 can also suppress the occurrence of cracks. can get.

  Further, in the first embodiment, as described above, the fillers 20a to 20c are made of a material capable of increasing the thermal conductivity of the first resin layer 2, so that the epoxy resin is a main component. Therefore, the heat conductivity of the resin layer 2 containing an epoxy resin as a main component can be improved. Since the second resin layer 4 has the same structure as the first resin layer 2, the second resin layer 4 can also improve heat dissipation.

  Further, in the first embodiment, as described above, the conductive layer 3 is configured to include the thermal via portion 3a that contacts the surface of the substrate 1 through the via hole 2a of the resin layer 2, and the conductive layer 5 is When a large amount of heat is generated from the LSI chip 9 by including the thermal via portion 5a in contact with the surface of the conductive layer 3 through the via hole 34a of the resin layer 4, the heat is transferred to the conductive layer 5 This thermal via portion 5a can be transmitted to the thermal via portion 3a of the conductive layer 3 in contact with the surface of the substrate 1. Further, when the conductive layer 3 is configured to include the thermal via portion 3b that contacts the surface of the substrate 1 through the via hole 2b of the resin layer 2, when a large amount of heat is generated from the chip resistor 10, Heat can be transferred to the thermal via portion 3 b of the conductive layer 3 that is in contact with the surface of the substrate 1. As a result, when a large amount of heat is generated from the LSI chip 9 and the chip resistor 10, heat can be easily radiated to the substrate 1 side.

  In the first embodiment, as described above, the first resin layer 2 and the conductive layer 3 are sequentially formed, and the second resin layer 4 and the conductive layer are formed on the first conductive layer 3. By sequentially forming 5, the wiring portion 3 c of the conductive layer 3 and the wiring portion 5 d of the conductive layer 5 can be insulated by the resin layer 4. Thereby, even if the wiring part 3c of the conductive layer 3 and the wiring part 5d of the conductive layer 5 intersect each other in plan view, the wiring part 3c of the conductive layer 3 and the wiring part 5d of the conductive layer 5 are electrically connected. Can be prevented from being short-circuited. As a result, the degree of freedom in routing the wiring portions 3c and 5d can be improved, and the wiring density can be improved.

  In the first embodiment, as described above, the heat generated in the LIS chip 9 and the chip resistor 10 can be efficiently radiated by using the substrate 1 mainly made of metal.

  Moreover, in 1st Embodiment, while using the board | substrate 1 which has an uneven surface as mentioned above, the resin layer 2 which has an epoxy resin as a main component on the uneven surface of the board | substrate 1 is formed. Thus, the contact area between the substrate 1 and the resin layer 2 can be increased, so that the adhesion between the substrate 1 and the resin layer 2 can be improved. Thereby, it can suppress more that the resin layer 2 peels from the board | substrate 1. FIG.

  In the first embodiment, as described above, the lower metal layer 1a and the upper metal layer 1c made of copper having a thermal expansion coefficient of about 0.2 ppm / ° C. to about 5 ppm / ° C., and about 0.2 ppm / ° C. The substrate 1 including the intermediate metal layer 1b made of an Invar alloy having a thermal expansion coefficient of about 5 ppm / ° C. is used, and the thickness ratio of the lower metal layer 1a, the intermediate metal layer 1b, and the upper metal layer 1c is 1: 1. By setting the ratio to 1, the thermal expansion coefficient of the substrate 1 can be set to about 6 ppm / ° C. to about 8 ppm / ° C., so that the thermal expansion coefficient of the substrate 1 (about 6 ppm / ° C. to about 8 ppm / ° C.) It is possible to approach both the thermal expansion coefficient of the chip 9 (about 4 ppm / ° C.) and the thermal expansion coefficient of the resin layer 2 (about 17 ppm / ° C. to about 18 ppm / ° C.). Thereby, it is possible to prevent the resin layer 2 from being peeled from the substrate 1 due to the difference in thermal expansion coefficient between the substrate 1 and the LSI chip 9 and the resin layer 2.

  In the first embodiment, as described above, the surface of the substrate 1 (upper metal layer 1c) is oxidized to form the copper oxide film 1d on the surface portion of the substrate 1 (upper metal layer 1c). Even if the insulating property of the resin layer 2 located between the substrate 1 and the wiring portion 3c of the conductive layer 3 deteriorates, the copper oxide film 1d on the surface portion of the substrate 1 functions as an insulating layer. It can suppress that the withstand voltage between the wiring parts 3c of the conductive layer 3 falls.

  4 to 16 are cross-sectional views for explaining a manufacturing process of the hybrid integrated circuit device according to the first embodiment of the present invention. A manufacturing process for the hybrid integrated circuit device according to the first embodiment is now described with reference to FIGS.

  First, as shown in FIG. 4, a lower metal layer 1a and an upper metal layer 1c made of copper having a thermal expansion coefficient of about 12 ppm / ° C. and a thermal expansion coefficient of about 0.2 ppm / ° C. to about 5 ppm / ° C. At the same time, the substrate 1 including the intermediate metal layer 1b made of Invar alloy is formed. Specifically, the substrate 1 made of a clad material having a three-layer structure is formed by pressure bonding in a state where the intermediate metal layer 1b is disposed between the lower metal layer 1a and the upper metal layer 1c. At this time, the thicknesses of the lower metal layer 1a, the intermediate metal layer 1b, and the upper metal layer 1c are set so that the thickness of the substrate 1 is about 100 μm to about 3 mm (for example, about 1.5 mm). In the first embodiment, the ratio of the thicknesses of the lower metal layer 1a, the intermediate metal layer 1b, and the upper metal layer 1c is set to 1: 1: 1. As a result, the thermal expansion coefficient of the substrate 1 is about 6 ppm / ° C. to about 8 ppm / ° C.

  Thereafter, the surface of the uppermost metal layer 1c constituting the substrate 1 is formed into a concavo-convex shape having an arithmetic average roughness Ra of about 10 μm to about 20 μm by using a sand blast technique, a wet blast technique or a wet etching technique. To roughen. The sandblasting technique is a technique for spraying an abrasive on a workpiece (work) by accelerating the abrasive with compressed air from a compressor. The wet blasting technique is a technique for spraying an abrasive on a workpiece (work) by accelerating a liquid mixed with the abrasive with compressed air from a compressor.

  Next, as shown in FIG. 5, the uneven surface of the upper metal layer 1c on the uppermost surface of the substrate 1 is oxidized by heat-treating the substrate 1 under a temperature condition of a few hundred degrees. Thereby, the uneven surface portion of the upper metal layer 1c on the uppermost surface of the substrate 1 becomes a copper oxide film 1d having a thickness of about 0.1 μm to about 0.3 μm.

  Next, as shown in FIG. 6, on the uneven surface of the substrate 1 (copper oxide film 1d), a filler 20a (average particle size: about 1 μm) corresponding to each of three different average particle sizes. , 20b (average particle size: about 10 μm) and 20c (average particle size: about 20 μm) (see FIG. 3) are applied to form a resin layer 2 having a thickness of about 60 μm to about 160 μm. Form. At this time, as shown in FIG. 3, a layer containing the filler 20 a (average particle size: about 1 μm), a layer containing the filler 20 b (average particle size: about 10 μm), and the filler inside the resin layer 2. A layer containing 20c (average particle size: about 20 μm) is formed in this order from the substrate 1 side. Thereafter, a copper foil 3 d having a thickness of about 3 μm is pressure-bonded onto the resin layer 2.

  Next, as shown in FIG. 7, the copper foil 3d located on the formation region of the via holes 2a and 2b (see FIG. 2) is removed using a photolithography technique and an etching technique. Thereby, the formation regions of the via holes 2a and 2b of the resin layer 2 are exposed.

  Next, as shown in FIG. 8, the region from the exposed surface of the resin layer 2 to the surface of the substrate 1 is removed by irradiating a carbon dioxide laser or UV laser from above the copper foil 3d. As a result, five via holes 2a and two via holes 2b having a diameter of about 70 μm and penetrating the resin layer 2 are formed in the resin layer 2. The via holes 2a and 2b are provided to form thermal via portions 3a and 3b described later, respectively.

  Next, as shown in FIG. 9, copper is plated to a thickness of about 0.5 μm on the upper surface of the copper foil 3d (see FIG. 8) and the inner surfaces of the via holes 2a and 2b by using an electroless plating method. Subsequently, the upper surface of the copper foil 3d and the inside of the via holes 2a and 2b are plated using an electrolytic plating method. In the first embodiment, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the upper surface of the copper foil 3d and the accelerator is adsorbed on the inner surfaces of the via holes 2a and 2b. Let Thereby, since the thickness of the copper plating on the inner surfaces of the via holes 2a and 2b can be increased, copper can be embedded in the via holes 2a and 2b. As a result, as shown in FIG. 9, a conductive layer 3 having a thickness of about 15 μm is formed on the resin layer 2, and the conductive layer 3 is embedded in the via holes 2a and 2b.

  In the copper plating step described above, in the first embodiment, the substrate 1 is used in which the intermediate metal layer 1b made of an Invar alloy containing Fe and Ni is sandwiched between the lower metal layer 1a made of copper and the upper metal layer 1c. Therefore, it is possible to suppress the deterioration of the plating solution due to the elution of the component of the intermediate metal layer 1b made of the Invar alloy into the plating solution.

  Next, as shown in FIG. 10, the conductive layer 3 is patterned by using a photolithography technique and an etching technique. Thereby, the thermal via part 3a located in the area below the LSI chip 9 (see FIG. 2), the thermal via part 3b located in the area below the chip resistor 10 (see FIG. 2), and the thermal via part 3a The wiring part 3c located in the area | region spaced apart from the edge part by predetermined spacing is formed.

  Next, as shown in FIG. 11, by applying an epoxy resin filled with a filler (not shown) corresponding to each of three different average particle sizes so as to cover the conductive layer 3, A resin layer 4 having a thickness of about 60 μm to about 160 μm is formed. The three types of fillers used for forming the resin layer 4 are the filler 20a (average particle size: about 1 μm), the filler 20b (average particle size: about 10 μm) and the filler 20c shown in FIG. It has an average particle size similar to (average particle size: about 20 μm). Further, when forming the resin layer 4, a layer containing a filler corresponding to an average particle diameter of about 1 μm, a layer containing a filler corresponding to an average particle diameter of about 10 μm, and an average particle diameter of about 20 μm The layers including the filler to be formed are formed in this order from the substrate 1 side. Thereafter, a copper foil 5 e having a thickness of about 3 μm is pressure-bonded onto the resin layer 4.

  Next, as shown in FIG. 12, the copper foil 5e located on the formation region of the via holes 4a and 4b (see FIG. 2) is removed by using a photolithography technique and an etching technique. Thereby, the formation regions of the via holes 4a and 4b of the resin layer 4 are exposed.

  Next, as shown in FIG. 13, the region from the exposed surface of the resin layer 4 to the surface of the conductive layer 3 is removed by irradiating a carbon dioxide laser or UV laser from above the copper foil 5e. Thus, five via holes 4 a and two via holes 4 b having a diameter of about 70 μm and penetrating the resin layer 4 are formed in the resin layer 4.

  Next, as shown in FIG. 14, copper is plated to a thickness of about 0.5 μm on the upper surface of the copper foil 5e (see FIG. 13) and the inner surfaces of the via holes 4a and 4b by using an electroless plating method. Subsequently, plating is performed on the upper surface of the copper foil 5e and the inside of the via holes 4a and 4b by using an electrolytic plating method. At this time, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the upper surface of the copper foil 5e, and the accelerator is adsorbed on the inner surfaces of the via holes 4a and 4b. Thereby, since the thickness of the copper plating on the inner surfaces of the via holes 4a and 4b can be increased, copper can be embedded in the via holes 4a and 4b. As a result, a conductive layer 5 having a thickness of about 15 μm is formed on the resin layer 4, and the conductive layer 5 is embedded in the via holes 4a and 4b.

  Next, as shown in FIG. 15, the conductive layer 5 is patterned by using a photolithography technique and an etching technique. As a result, the thermal via portion 5a located in a region below the LSI chip 9 (see FIG. 2), the wire bonding portion 5b located in a region spaced from the end of the thermal via portion 5a by a predetermined distance, and the chip resistance A wiring portion 5c located in a region below 10 (see FIG. 2) and a wiring portion 5d located in a region below the lead 11 (see FIG. 2) are formed.

  Next, as illustrated in FIG. 16, a solder resist layer 6 a having openings in regions corresponding to the wire bonding portion 5 b and the wiring portions 5 c and 5 d of the conductive layer 5 is formed so as to cover the conductive layer 5. Then, the LSI chip 9 is mounted on the solder resist layer 6a on the thermal via portion 5a of the conductive layer 5 via the resin layer 6 made of an epoxy resin having a thickness of about 50 μm. The thickness of the resin layer 6 after mounting the LSI chip 9 is about 20 μm. Thereafter, the LSI chip 9 and the wire bonding part 5 b of the conductive layer 5 are electrically connected by the wire 7. Further, the chip resistor 10 is mounted on the wiring portion 5c of the conductive layer 5 via a fusion layer 8a made of a brazing material such as solder. Further, the lead 11 is mounted on the wiring portion 5d of the conductive layer 5 via a fusion layer 8b made of a brazing material such as solder. Note that the chip resistor 10 and the lead 11 are electrically connected to the wiring portions 5c and 5d through the fusion layers 8a and 8b, respectively.

  Finally, as shown in FIG. 2, in order to protect the LSI chip 9 and the chip resistor 10 on the substrate 1, a resin layer 12 made of an epoxy resin is formed so as to cover the LSI chip 9 and the chip resistor 10. Thus, the hybrid integrated circuit device according to the first embodiment is formed.

(Second Embodiment)
FIG. 17 is a sectional view showing the structure of a hybrid integrated circuit device according to the second embodiment of the present invention. FIG. 18 is a schematic view showing the distribution of the filler filled in the first resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. 17, and FIG. 19 is shown in FIG. It is the graph which showed distribution of the filler with which the 1st resin layer of the hybrid integrated circuit device by 2nd Embodiment is filled. FIG. 20 is a schematic diagram showing the distribution of the filler filled in the second resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. 17, and FIG. 21 is shown in FIG. It is the graph which showed distribution of the filler with which the 2nd resin layer of the hybrid integrated circuit device by 2nd Embodiment is filled. 17 to 21, in the second embodiment, unlike the first embodiment, the Young's modulus of the first resin layer is smaller than the Young's modulus of the second resin layer. The case where the average particle diameter of each of the filler filled in the first resin layer and the filler filled in the second resin layer is controlled will be described.

  In the second embodiment, as shown in FIG. 17, a first resin layer 32 mainly composed of an epoxy resin having a thickness of about 120 μm is formed on the same substrate 1 as in the first embodiment. ing. This resin layer 32 functions as an insulating layer. The resin layer 32 is an example of the [insulating layer] and the “first insulating layer” in the present invention.

Here, in the second embodiment, as shown in FIG. 18, the resin layer 32 has a weight of about 75% of a filler containing at least fillers 32a and 32b corresponding to two different average particle diameters. It is filled at a filling rate. The average particle diameters of the fillers 32a and 32b are about 0.7 μm and about 3 μm, respectively. Further, the fillers 32a (average particle size: about 0.7 μm) and 32b (average particle size: about 3 μm) are filled at a frequency as shown in FIG. Specifically, the blending ratio of the fillers 32a and 32b is 2: 8. Further, as a constituent material of the fillers 32a and 32b, alumina (Al ₂ O ₃ ) capable of improving the thermal conductivity of the resin layer 32 is used.

  In the second embodiment, the Young's modulus (rigidity) of the first resin layer 32 is set to about 38470 MPa by filling the fillers 32a and 32b as described above. The thermal conductivity and thermal expansion coefficient of the first resin layer 32 are about 4.4 W / (m · K) and about 10 ppm / ° C., respectively.

  In the second embodiment, as shown in FIG. 17, five via holes 32 a having a diameter of about 70 μm and penetrating the resin layer 32 are formed in a predetermined region of the resin layer 32 located below the LSI chip 9. Is formed. In addition, in a predetermined region of the resin layer 32 located below the chip resistor 10, two via holes 32 b having a diameter of about 70 μm and penetrating the resin layer 32 are formed.

  In a predetermined region on the resin layer 32, a first conductive layer 3 made of copper having a thickness of about 15 μm and including thermal via portions 3a and 3b and a wiring portion 3c is formed. The thermal via portion 3 a of the conductive layer 3 is disposed in a region below the LSI chip 9 and has a portion embedded in the via hole 32 a so as to contact the surface of the substrate 1. Further, the thermal via portion 3 b is embedded in a via hole 32 b located in a region below the chip resistor 10. The thermal via portions 3 a and 3 b of the conductive layer 3 have a function of radiating heat to the substrate 1.

  In the second embodiment, a second resin layer 34 mainly composed of an epoxy resin having a thickness of about 155 μm is formed so as to cover the conductive layer 3. This resin layer 34 functions as an insulating layer. The resin layer 34 is an example of the “insulating layer” and “second insulating layer” in the present invention.

Here, in the second embodiment, as shown in FIG. 20, the resin layer 34 includes approximately 65% filler including at least fillers 34 a, 34 b, and 34 c corresponding to three different average particle diameters. It is filled with the weight filling rate. The average particle diameters of the fillers 34a, 34b and 34c are about 0.7 μm, about 10 μm and about 45 μm, respectively. Further, the fillers 34a (average particle size: about 0.7 μm), 34b (average particle size: about 10 μm) and 34c (average particle size: about 45 μm) are filled at a frequency as shown in FIG. Specifically, the blending ratio of the fillers 34a, 34b and 34c is 2: 4: 4. In addition, as a constituent material of the fillers 34a, 34b, and 34c, alumina (Al ₂ O ₃ ) capable of improving the thermal conductivity of the resin layer 34 is used.

  In the second embodiment, the Young's modulus (rigidity) of the second resin layer 34 is set to about 42050 MPa by filling the fillers 34a, 34b and 34c as described above. That is, in the second embodiment, the Young's modulus (rigidity) (about 38470 MPa) of the first resin layer 32 is smaller than the Young's modulus (rigidity) (about 42050 MPa) of the second resin layer 34. It is configured. The thermal conductivity and thermal expansion coefficient of the second resin layer 34 are about 3.8 W / (m · K) and about 17 ppm / ° C., respectively.

  In the second embodiment, as shown in FIG. 17, five via holes 34 a having a diameter of about 70 μm and penetrating the resin layer 34 are formed in a predetermined region of the resin layer 34 located below the LSI chip 9. Is formed. The five via holes 34a are arranged at positions corresponding to the five via holes 32a, respectively. In the resin layer 34, two via holes 34 b having a diameter of about 70 μm and penetrating the resin layer 34 are formed in a region corresponding to the wiring portion 3 c of the conductive layer 3.

  The predetermined region on the resin layer 34 has a thickness of about 15 μm and a conductive layer 5 made of a second layer of copper including the thermal via portion 5a, the wire bonding portion 5b, and the wiring portions 5c and 5d. Is formed. The thermal via portion 5a of the conductive layer 5 is disposed in a region below the LSI chip 9 and has a portion embedded in the via hole 34a so as to contact the surface of the thermal via portion 3a of the conductive layer 3. . The thermal via portion 5a of the conductive layer 5 has a function of transferring heat generated in the LSI chip 9 to the thermal via portion 3a of the conductive layer 3 to dissipate heat. The wire bonding portion 5b of the conductive layer 5 is disposed in a region corresponding to the via hole 34b, and has a portion embedded in the via hole 34b so as to contact the surface of the wiring portion 3c of the conductive layer 3. . The wiring portion 5 c of the conductive layer 5 is disposed in a region below the chip resistor 10. The wiring portion 5 d of the conductive layer 5 is disposed in a region below the lead 11.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, as described above, the average particle diameters of the fillers 32a and 32b filled in the first resin layer 32 mainly composed of epoxy resin are set to about 0.7 μm and about 3 μm, respectively. In addition, the average particle diameters of the fillers 34a, 34b and 34c filled in the second resin layer 34 mainly composed of an epoxy resin are set to about 0.7 μm, about 10 μm and about 45 μm, respectively. Thus, the Young's modulus (rigidity) of the first resin layer 32 can be made smaller than the Young's modulus (rigidity) of the second resin layer 34. Thereby, even when the first resin layer 32 formed on the substrate 1 is pulled by the thermally expanded substrate 1 when the substrate 1 is expanded by the heat generated by the LSI chip 9 and the chip resistor 10, Since the first resin layer 32 having a small Young's modulus (rigidity) is deformed so as to extend together with the substrate 1, the shear stress generated between the substrate 1 and the first resin layer 32 can be reduced. . As a result, peeling of the first resin layer 32 from the substrate 1 can be suppressed. Even if the substrate 1 expands due to heat generated by the LSI chip 9 and the chip resistor 10, the second resin layer 34 (first layer) is high because the Young's modulus (rigidity) of the second resin layer 34 is large. The resin layer 32) can be prevented from being deformed so that the underlying substrate 1 is warped. Thereby, it can suppress that a hybrid integrated circuit device deform | transforms.

  In the second embodiment, as described above, the first resin layer 32 is filled only with the fillers 32a and 32b corresponding to the relatively small average particle diameter, while the second resin layer 34 is filled. By filling the filler 34a corresponding to the relatively small average particle diameter and the fillers 34b and 34c corresponding to the relatively large average particle diameter, the Young's modulus of the first resin layer 32 ( (Rigidity) can be made smaller than the Young's modulus (rigidity) of the second resin layer 34.

  In the second embodiment, as described above, the mixing ratio of the fillers 32a (average particle size: about 0.7 μm) and 32b (average particle size: about 3 μm) filled in the first resin layer 32 is used. Is set to 2: 8, the filler 32a corresponding to the average particle diameter of about 0.7 μm can be filled into the small gap where the filler 32b corresponding to the average particle diameter of about 3 μm cannot enter. Therefore, the filling rate of the filler in the resin layer 32 can be increased. Thereby, since the heat conductivity of the resin layer 32 can be made high, the heat dissipation of the resin layer 32 can be improved.

  In the second embodiment, as described above, the second resin layer 34 has an average particle diameter (about 0.7 μm) of the filler 34a and an average particle diameter (about 20 μm) of the filler 34c. By filling with the filler 34b corresponding to the average particle size (about 10 μm) having the size of, it is possible to suppress a decrease in the filling rate of the filler in the second resin layer 34, It can suppress that the heat dissipation of the resin layer 34 falls.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and all modifications within the meaning and scope equivalent to the scope of claims for patent are included.

  For example, in the first and second embodiments, the present invention is applied to the hybrid integrated circuit device in which the LSI chip and the chip resistor are mounted. However, the present invention is not limited to this, and circuit elements other than the LSI chip and the chip resistor are used. The present invention can also be applied to a hybrid integrated circuit device to which is mounted and a semiconductor integrated circuit device other than the hybrid integrated circuit device.

  In the first and second embodiments, the example in which the present invention is applied to the circuit device having a two-layer structure in which the second insulating layer and the conductive layer are sequentially formed on the first conductive layer has been described. However, the present invention is not limited to this and can be applied to a circuit device having a single-layer structure. Further, the present invention can be applied to a circuit device in which a third insulating layer and a conductive layer are sequentially formed on the second conductive layer. The present invention can also be applied to a circuit device having a multilayer structure of four or more layers.

  In the first embodiment, in the resin layer, a layer containing only a filler corresponding to an average particle diameter of about 1 μm, a layer containing only a filler corresponding to an average particle diameter of about 10 μm, and about 20 μm The layers including only the filler corresponding to the average particle diameter are arranged in this order from the substrate side. However, the present invention is not limited to this, and the layer including the filler corresponding to the average particle diameter of approximately 20 μm is approximately 20 μm. A filler corresponding to the following average particle diameter (for example, a filler corresponding to an average particle diameter of about 10 μm or about 1 μm) may be mixed, and includes a filler corresponding to an average particle diameter of about 10 μm. A filler corresponding to an average particle diameter of about 10 μm or less (for example, a filler corresponding to an average particle diameter of about 1 μm) may be mixed in the layer. In this case, since the filler corresponding to the small average particle diameter can be filled in the small gap in which the filler corresponding to the large average particle diameter cannot enter, the filling rate of the filler in the resin layer is increased. be able to. Thereby, since the heat conductivity of a resin layer can be made high, the heat dissipation of a resin layer can be improved.

1 is a perspective view showing a structure of a hybrid integrated circuit device (hybrid IC) according to a first embodiment of the present invention. It is sectional drawing along the 100-100 line of FIG. FIG. 3 is a schematic diagram showing a distribution of fillers filled in a resin layer of the hybrid integrated circuit device according to the first embodiment shown in FIG. 2. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of the hybrid integrated circuit device by 1st Embodiment of this invention. It is sectional drawing which showed the structure of the hybrid integrated circuit device by 2nd Embodiment of this invention. FIG. 18 is a schematic diagram showing a distribution of a filler filled in the first resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. 17. 18 is a graph showing a distribution of fillers filled in the first resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. FIG. 18 is a schematic diagram showing a distribution of fillers filled in a second resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. 17. 18 is a graph showing a distribution of fillers filled in a second resin layer of the hybrid integrated circuit device according to the second embodiment shown in FIG. It is sectional drawing which showed the structure of the conventional circuit device roughly.

Explanation of symbols

1 Substrate 2, 4 Resin layer (insulating layer)
3, 5 Conductive layer 9 LSI chip (circuit element)
10 Chip resistor (circuit element)
20a, 20b, 20c, 32a, 32b, 34a, 34b, 34c Filler 32 Resin layer (insulating layer, first insulating layer)
34 Resin layer (insulating layer, second insulating layer)

Claims (6)

A substrate,
An insulating layer formed on the substrate;
A filler filled in the insulating layer;
A conductive layer formed on the insulating layer;
A circuit element formed on the conductive layer,
Of the filler filled in the insulating layer, the Young's modulus of the portion of the insulating layer located on the substrate side is smaller than the Young's modulus of the portion of the insulating layer located on the opposite side of the substrate. A circuit device in which the average particle size is controlled. The insulating layer consists of one layer,
The Young's modulus of the portion located on the substrate side of the one-layer insulating layer is smaller than the Young's modulus of the portion located on the opposite side of the one-layer insulating layer from the substrate. The circuit device described in 1. The insulating layer has a first insulating layer having a first Young's modulus formed on the substrate, and a second Young's modulus formed on a surface of the first insulating layer opposite to the substrate. 2 insulating layers,
The circuit device according to claim 1, wherein a first Young's modulus of the first insulating layer is smaller than a second Young's modulus of the second insulating layer.   The first insulating layer is filled with the filler corresponding to each of a plurality of different average particle diameters, and the second insulating layer is filled with each of a plurality of different average particle diameters. The circuit device according to claim 3, wherein the corresponding filler is filled.   The filler corresponding to the largest average particle diameter among the fillers filled in the insulating layer is not filled in the first insulating layer, but is filled in the second insulating layer. 4. The circuit device according to 4.   The filler corresponding to the smallest average particle diameter among the fillers filled in the insulating layer is filled in both the first insulating layer and the second insulating layer. The circuit device described.

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