JP2006269469A - Thin-film transistor and manufacturing method thereof - Google Patents

Thin-film transistor and manufacturing method thereof Download PDF

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JP2006269469A
JP2006269469A JP2005081117A JP2005081117A JP2006269469A JP 2006269469 A JP2006269469 A JP 2006269469A JP 2005081117 A JP2005081117 A JP 2005081117A JP 2005081117 A JP2005081117 A JP 2005081117A JP 2006269469 A JP2006269469 A JP 2006269469A
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thin film
electrode
semiconductor thin
film transistor
ohmic contact
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Hiromitsu Ishii
裕満 石井
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Casio Comput Co Ltd
カシオ計算機株式会社
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Abstract

PROBLEM TO BE SOLVED: To improve processing accuracy in manufacturing a thin film transistor having a top gate structure having a semiconductor thin film made of intrinsic zinc oxide.
Using a protective film 11 made of silicon nitride as a mask, a semiconductor thin film forming film made of intrinsic zinc oxide and an ohmic contact layer forming layer made of n-type zinc oxide are successively etched, thereby protecting the protective film 11. By forming the semiconductor thin film 10 underneath, forming the ohmic contact layers 8 and 9 on both sides under the semiconductor thin film 10, and leaving the protective film 11 as it is on the entire upper surface of the semiconductor thin film 10, the processing accuracy can be improved. it can.
[Selection] Figure 2

Description

  The present invention relates to a thin film transistor and a method for manufacturing the same.

  For example, in a thin film transistor used as a switching element of an active matrix liquid crystal display element, a gate electrode is provided on the upper surface of an insulating substrate, a gate insulating film is provided on the upper surface of the insulating substrate including the gate electrode, and a gate on the gate electrode is provided. A semiconductor thin film made of intrinsic amorphous silicon is provided on the upper surface of the insulating film, a channel protective film is provided in the center of the upper surface of the semiconductor thin film, and n-type amorphous silicon is formed on both sides of the upper surface of the channel protective film and on the upper surface of the semiconductor thin film on both sides. The ohmic contact layer is formed, and the source / drain electrode is provided on the upper surface of each ohmic contact layer (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 5-67786 (FIG. 2)

  Recently, instead of amorphous silicon, higher mobility can be obtained, and therefore it is considered to use zinc oxide (ZnO). As a method for manufacturing such a thin film transistor using zinc oxide, for example, a semiconductor thin film forming layer made of intrinsic zinc oxide is formed on a gate insulating film, and a channel made of silicon nitride is formed on the upper surface of the semiconductor thin film forming layer. A protective film is patterned, an ohmic contact layer forming layer made of n-type zinc oxide is formed on the upper surface of the semiconductor thin film forming layer including the channel protective film, and the ohmic contact layer forming layer and the semiconductor thin film forming layer are formed It is conceivable to perform continuous patterning to form an ohmic contact layer and a semiconductor thin film in the device area, and pattern the source / drain electrodes on the upper surface of each ohmic contact layer.

  However, in the above manufacturing method, since zinc oxide is easily dissolved in both acid and alkali, and etching resistance is extremely low, a relatively large side is formed in the semiconductor thin film and ohmic contact layer made of zinc oxide formed in the device area in a later step. It has been found that etching occurs and processing accuracy deteriorates.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor that can improve processing accuracy and a method for manufacturing the same.

  In order to achieve the above object, the present invention provides a semiconductor thin film, a protective film provided on the entire top surface of the semiconductor thin film, an insulating film provided on the protective film, and the insulating film on the semiconductor thin film. And a source electrode and a drain electrode provided in electrical connection with the semiconductor thin film under the semiconductor thin film.

  According to the present invention, when the protective film is provided on the entire upper surface of the semiconductor thin film, that is, when the resist pattern for forming the protective film on the upper surface of the semiconductor thin film forming film is peeled off, the semiconductor thin film formation under the protective film The protective film is protected with a protective film, then the semiconductor thin film forming film is etched using the protective film as a mask to form a semiconductor thin film under the protective film, and the protective film is left as it is on the entire upper surface of the semiconductor thin film. The accuracy can be improved.

(First embodiment)
FIG. 1 shows a transmission plan view of a main part of a liquid crystal display device having a thin film transistor as a first embodiment of the present invention, FIG. 2A shows an enlarged transmission plan view of a part of FIG. (B) is a cross-sectional view taken along II B -II B line in FIG. 2 (a). The liquid crystal display element includes a glass substrate 1. On the upper surface of the glass substrate 1, a plurality of pixel electrodes 2 arranged in a matrix, thin film transistors 3 connected to the pixel electrodes 2, and scanning lines arranged in the row direction and supplying scanning signals to the thin film transistors 3. 4 and a data line 5 arranged in the column direction and supplying a data signal to each thin film transistor 3 is provided. Here, for the purpose of clarifying FIG. 1 and FIG. 2 (A), a diagonal short solid line hatching is written on the edge of the pixel electrode 2 (hereinafter the same).

  That is, a source electrode 6 made of aluminum, chromium, ITO or the like, a drain electrode 7 and a data line 5 connected to the drain electrode 7 are provided at each predetermined location on the upper surface of the glass substrate 1. On the upper surface of the source electrode 6, one ohmic contact layer 8 made of n-type zinc oxide is provided on a predetermined portion on the drain electrode 7 side and the upper surface of the glass substrate 1 in the vicinity thereof. On the upper surface of the drain electrode 7, another ohmic contact layer 9 made of n-type zinc oxide is provided on a predetermined portion on the source electrode 6 side and on the upper surface of the glass substrate 1 in the vicinity thereof. In other words, the ohmic contact layers 8 and 9 protrude from the opposite end faces 8a and 9a of the upper surfaces of the source electrode 6 and the drain electrode 7 from the opposite end faces 6a and 7a of the source electrode 6 and the drain electrode 7, respectively. Has been provided

  A semiconductor thin film 10 made of intrinsic zinc oxide is provided on the entire upper surfaces of both ohmic contact layers 8 and 9 and the upper surface of the glass substrate 1 therebetween. A protective film 11 made of silicon nitride is provided on the entire top surface of the semiconductor thin film 10. Here, the semiconductor thin film 10 and the protective film 11 have the same planar shape as shown in FIG. Further, the two ohmic contact layers 8 and 9 have the same shape as the end surfaces of the semiconductor thin film 10 and the protective film 11 except for the end surfaces 8 a and 9 a facing each other. The distance between the end faces 8a and 9a between the two ohmic contact layers 8 and 9 is the channel length L, and the dimension in the direction perpendicular to the channel length L of the ohmic contact layers 8 and 9 is the channel width W. Yes.

  An insulating film 12 made of silicon nitride is provided on the upper surface of the glass substrate 1 including the protective film 11, the data line 5 and the source electrode 6. A gate electrode 13 made of aluminum, chromium, ITO or the like and a scanning line 4 connected to the gate electrode 13 are provided at predetermined locations on the upper surface of the insulating film 12.

  Here, the source electrode 6, the drain electrode 7, the ohmic contact layers 8 and 9, the semiconductor thin film 10, the protective film 11, the insulating film 12 and the gate electrode 13 constitute a thin film transistor 3 having a top gate structure. In this case, the gate insulating film of the thin film transistor 3 is formed by the protective film 11 and the insulating film 12.

  An overcoat film 14 made of silicon nitride is provided on the upper surface of the insulating film 12 including the gate electrode 13 and the scanning line 4. A contact hole 15 is provided in the overcoat film 14 in a portion corresponding to a predetermined portion of the source electrode 6. A pixel electrode 2 made of a transparent conductive material such as ITO is connected to the source electrode 6 through a contact hole 15 at a predetermined location on the upper surface of the overcoat film 14.

  Next, an example of a method for manufacturing the thin film transistor 3 in the liquid crystal display element will be described. First, as shown in FIGS. 3A and 3B, a metal film made of aluminum, chromium, ITO, or the like formed by sputtering at each predetermined location on the upper surface of the glass substrate 1 is obtained by photolithography. By patterning, the source electrode 6, the drain electrode 7, and the data line 5 connected to the drain electrode 7 are formed.

  Next, a first ohmic contact layer forming layer 21 made of n-type zinc oxide is formed on the upper surface of the glass substrate 1 including the source electrode 6, the drain electrode 7, and the data line 5 by facing target sputtering. . In this case, it can be formed by reactive sputtering using oxygen gas with indium and zinc as targets or gallium and zinc as targets. Alternatively, indium-zinc oxide (InZnO) or gallium-zinc oxide (GaZnO) may be used as a target.

  Next, resist patterns 22a and 22b are formed at predetermined locations on the upper surface of the first ohmic contact layer forming layer 21 by photolithography. In this case, one resist pattern 22 a is formed to be somewhat larger than the source electrode 6 and completely cover the source electrode 6. The other resist pattern 22b is formed to be somewhat larger than the drain electrode 7 including a part of the data line 5 so as to completely cover the drain electrode 7 including a part of the data line 5.

  The resist patterns 22a and 22b are formed as described above with reference to FIGS. 2A and 2B. For example, the resist patterns 22a and 22b are formed between the end face 6a of the source electrode 6 and the end face 8a of one ohmic contact layer 8. This is because the interval is a margin for keeping the positional relationship between the end faces 6a and 8a in a desired relationship, and generally 1 to 4 μm is required although it depends on the processing accuracy.

  Next, when the first ohmic contact layer forming layer 21 is etched using the resist patterns 22a and 22b as masks, as shown in FIGS. 4A and 4B, the second ohmic contact layer forming layer 21 is formed under the resist patterns 22a and 22b. Ohmic contact layer forming layers 21a and 21b are formed. In this case, an alkaline aqueous solution is used as the etching solution for the first ohmic contact layer forming layer 21 made of n-type zinc oxide. For example, an aqueous solution of less than 30 wt% sodium hydroxide (NaOH), preferably an aqueous solution of 2 to 10 wt% is used. The temperature of the etching solution is 5 to 40 ° C., preferably room temperature (22 to 23 ° C.).

  When an aqueous solution of sodium hydroxide (NaOH) 5 wt% (temperature is room temperature (22 to 23 ° C.)) was used as an etching solution, the etching rate was about 80 nm / min. By the way, considering the controllability of processing, if the etching rate is too large, it is difficult to control the end of etching because of variations in film thickness, density, etc. Of course, if it is too small, the productivity is lowered. Therefore, it is generally said that the etching rate is preferably about 100 to 200 nm / min. A 5 wt% aqueous solution of sodium hydroxide (NaOH) with an etching rate of about 80 nm / min can be said to be a satisfactory range.

  However, the concentration of sodium may be increased to increase production efficiency. In addition, when using an etching solution having a high speed such as an aqueous phosphoric acid solution, the concentration must be extremely low, such as about 0.05%. When using such a low concentration, the rate of deterioration during use is low. Is too large to control. Accordingly, in the case of an aqueous sodium hydroxide solution, an aqueous solution of less than 30 wt%, preferably an aqueous solution of about 2 to 10 wt% can be applied, and this is extremely effective in this respect. When the amount of side etching of the first ohmic contact layer forming layer 21 by wet etching affects the distance between the end faces 8a and 9a between the ohmic contact layers 8 and 9, that is, the channel length L, dry etching is performed. It is good.

  Next, the resist patterns 22a and 22b are stripped using a resist stripping solution. Here, it is possible to perform resist stripping satisfactorily even if a resist stripping solution that does not exhibit acidity or alkalinity (no electrolyte), for example, a single organic solvent (for example, dimethyl sulfoxide (DMSO)) is used. Has been confirmed by the inventor. Here, the resist stripping solution etches the second ohmic contact layer forming layers 21a and 21b made of n-type zinc oxide. In this case, the amount of side etching is not so large, which affects the channel length L. Not so much as to affect. Moreover, although the upper surfaces of the second ohmic contact layer forming layers 21a and 21b are etched by the resist stripping solution, the reduction of the ohmic contact layer does not affect the characteristics of the thin film transistor, so there is no problem. As the ohmic contact layer, ITO can be used instead of n-type zinc oxide.

  Next, as shown in FIGS. 5A and 5B, intrinsic zinc oxide is formed on the upper surface of the glass substrate 1 including the second ohmic contact layer forming layers 21a and 21b and the data line 5 by plasma CVD. A film 10a for forming a semiconductor thin film and a film 11a for forming a protective film made of silicon nitride are successively formed. Next, a resist pattern 23 for forming a device area is formed by a photolithography method at a predetermined position on the upper surface of the protective film forming film 11a.

Next, when the protective film forming film 11a is etched using the resist pattern 23 as a mask, the protective film 11 is formed under the resist pattern 23 as shown in FIGS. 6 (A) and 6 (B). In this case, the surface of the semiconductor thin film forming film 10a in the region other than under the resist pattern 23 is exposed. Therefore, as a method for etching the protective film forming film 11a made of silicon nitride, the etching speed of the protective film forming film 11a is fast, but the semiconductor thin film forming film 10a made of intrinsic zinc oxide is prevented from being damaged as much as possible. In addition, reactive plasma etching (dry etching) using sulfur hexafluoride (SF 6 ) is preferable.

  Next, the resist pattern 23 is stripped using a resist stripping solution. In this case, the surface of the semiconductor thin film forming film 10a in the region other than the region under the protective film 11 is exposed to the resist stripping solution. However, since the exposed portion is outside the device area, there is no problem. That is, unlike the ohmic contact layer, side etching of the channel region and etching of the upper surface of the channel region greatly affect the characteristics of the thin film transistor. However, in the present invention, the semiconductor thin film forming film 10 a under the protective film 11 is protected by the protective film 11. In this case, a resist stripping solution that does not exhibit acidity or alkalinity (no electrolyte), for example, a single organic solvent (for example, dimethyl sulfoxide (DMSO)) may be used.

  Next, when the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b are continuously etched using the protective film 11 as a mask, as shown in FIGS. A semiconductor thin film 10 is formed under the protective film 11, and ohmic contact layers 8 and 9 are formed on both sides under the semiconductor thin film 10.

  In this case, since the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b are formed of intrinsic zinc oxide and n-type zinc oxide, when the sodium hydroxide aqueous solution is used as an etching solution, Processing controllability can be improved. Here, the distance between the two ohmic contact layers 8 and 9 is the channel length L, and the dimension in the direction perpendicular to the channel length L of the ohmic contact layers 8 and 9 is the channel width W.

  In the above description, after the resist pattern 23 is removed, the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b are etched using the protective film 11 as a mask. The resist pattern 23 may be peeled off after etching the application film 10a and the second ohmic contact layer forming layers 21a and 21b.

  Next, as shown in FIGS. 8A and 8B, an insulating film 12 made of silicon nitride is formed on the upper surface of the glass substrate 1 including the protective film 11, the source electrode 6 and the data line 5 by plasma CVD. Form a film. Next, a metal film made of chromium, aluminum, ITO, or the like formed by sputtering at a predetermined location on the upper surface of the insulating film 12 is patterned by photolithography, whereby the gate electrode 13 and the gate electrode 13 are formed. Connected scan lines 4 are formed.

  Next, as shown in FIGS. 2A and 2B, an overcoat film 14 made of silicon nitride is formed on the upper surface of the insulating film 12 including the gate electrode 13 and the scanning line 4 by plasma CVD. . Next, a contact hole 15 is formed in the overcoat film 14 and the insulating film 12 at a portion corresponding to a predetermined portion of the source electrode 15 by photolithography. Next, a pixel electrode forming film made of a transparent conductive material such as ITO formed by sputtering is patterned at a predetermined position on the upper surface of the overcoat film 14 by photolithography, thereby bringing the pixel electrode 2 into contact. It is formed by being connected to the source electrode 6 through the hole 15. Thus, the liquid crystal display element shown in FIGS. 2A and 2B is obtained.

  As described above, in the above manufacturing method, when the resist pattern 23 for forming the protective film 11 is peeled off from the upper surface of the semiconductor thin film forming film 10a, the semiconductor thin film forming film 10a under the protective film 11 is removed. Next, the semiconductor thin film 10 is formed under the protective film 11 by successively etching the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b using the protective film 11 as a mask. In addition, since the ohmic contact layers 8 and 9 are formed on both sides under the semiconductor thin film 10 and the protective film 11 is left as it is on the entire upper surface of the semiconductor thin film 10, the processing accuracy can be improved.

  In the thin film transistor 3 obtained by the above manufacturing method, the distance between the two ohmic contact layers 8 and 9 is the channel length L, and the dimension in the direction perpendicular to the channel length L of the ohmic contact layers 8 and 9 is the channel width W. Therefore, the size can be made equal to the size of the channel-etched thin film transistor with the bottom gate structure, and the size can be reduced.

(Second Embodiment)
FIG. 9A shows a transmission plan view of a main part of a liquid crystal display device having a thin film transistor as a second embodiment of the present invention, and FIG. 9B shows a line IX B -IX B in FIG. 9A. FIG. This liquid crystal display element differs from the liquid crystal display element shown in FIGS. 2A and 2B in that the distance between the source electrode 6 and the drain electrode 7 is the channel length L, and each of the source electrode 6 and the drain electrode 7 is Ohmic contact layers 8 and 9 are provided only at predetermined locations on the upper surface, thereby further reducing the size of the thin film transistor 3. That is, ohmic contact layers 8 and 9 have end faces 8a and 9a facing each other on the upper surfaces of the source electrode 6 and the drain electrode 7, respectively, and have the same shape as the end faces 6a and 7a facing the source electrode 6 and the drain electrode 7. Has been provided

  In this case, the gate electrode 13 and the source electrode 6 are provided at positions closer to the drain electrode 7 side to some extent as compared with the case shown in FIGS. Further, the dimensions of the semiconductor thin film 10 and the protective film 11 in the channel length L direction are somewhat shorter than those shown in FIGS. 2 (A) and 2 (B). As a result, the thin film transistor 3 is downsized to some extent even when the channel length L and the channel width W are the same as in the case shown in FIGS. Further, the area of the pixel electrode 2 is increased to some extent as compared with the case shown in FIGS. 2A and 2B, and the aperture ratio is increased accordingly.

  Next, an example of a method for manufacturing the thin film transistor 3 portion in the liquid crystal display element will be described. First, as shown in FIGS. 9A and 9B, a metal film made of aluminum, chromium, ITO or the like formed by sputtering at each predetermined location on the upper surface of the glass substrate 1 by photolithography. By patterning, the source electrode 6, the drain electrode 7, and the data line 5 connected to the drain electrode 7 are formed.

  Next, a first ohmic contact layer forming layer 21 made of n-type zinc oxide is formed on the upper surface of the glass substrate 1 including the source electrode 6, the drain electrode 7 and the data line 5 by plasma CVD. Next, resist patterns 22a and 22b are formed at predetermined positions on the upper surface of the first ohmic contact layer forming layer 21 by photolithography including backside exposure (exposure from the lower surface side of the glass substrate 1). . In this case, since the back exposure is performed, one resist pattern 22 a is formed on the source electrode 6, and the other resist pattern 22 b is formed on the drain electrode 7 and the data line 5.

  Next, when the first ohmic contact layer forming layer 21 is etched using the resist patterns 22a and 22b as masks, a second ohmic contact is formed under the resist pattern 21 as shown in FIGS. Layer forming layers 21a and 21b are formed. In this case, since the first ohmic contact layer forming layer 21 is formed of n-type zinc oxide, when the sodium hydroxide is used as an etching solution, the process controllability can be improved.

  Next, the resist patterns 22a and 22b are stripped using a resist stripping solution. In this case, the surfaces of the second ohmic contact layer forming layers 21a and 21b are exposed. Accordingly, as the resist stripping solution in this case, a resist that does not exhibit acidity or alkalinity (no electrolyte), for example, a single organic solvent (for example, dimethyl sulfoxide (DMSO)) is used.

  Next, as shown in FIGS. 12A and 12B, a semiconductor thin film made of intrinsic zinc oxide is formed on the upper surface of the glass substrate 1 including the second ohmic contact layer forming layers 21a and 21b by plasma CVD. A forming film 10a and a protective film forming film 11a made of silicon nitride are successively formed. Next, a resist pattern 23 for forming a device area is formed by a photolithography method at a predetermined position on the upper surface of the protective film forming film 11a.

Next, when the protective film forming film 11a is etched using the resist pattern 23 as a mask, the protective film 11 is formed under the resist pattern 23 as shown in FIGS. In this case, the surface of the semiconductor thin film forming film 10a in the region other than under the resist pattern 23 is exposed. Accordingly, as an etching method for forming the protective film 11 made of silicon nitride, reactive plasma etching (dry etching) using sulfur hexafluoride (SF 6 ) is preferable.

  Next, the resist pattern 23 is stripped using a resist stripping solution. In this case, the surface of the semiconductor thin film forming film 10a in the region other than the region under the protective film 11 is exposed to the resist stripping solution. However, since the exposed portion is outside the device area, there is no problem. That is, the semiconductor thin film forming film 10 a under the protective film 11 is protected by the protective film 11. In this case, a resist stripping solution that does not exhibit acidity or alkalinity (no electrolyte), for example, a single organic solvent (for example, dimethyl sulfoxide (DMSO)) may be used.

  Next, when the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b are continuously etched using the protective film 11 as a mask, as shown in FIGS. A semiconductor thin film 10 is formed under the protective film 11, and ohmic contact layers 8 and 9 are formed on both sides under the semiconductor thin film 10.

  In this case, since the semiconductor thin film forming film 10a and the second ohmic contact layer forming layers 21a and 21b are formed of intrinsic zinc oxide and n-type zinc oxide, when the sodium hydroxide aqueous solution is used as an etching solution, Processing controllability can be improved. Here, the distance between the two ohmic contact layers 8 and 9 is the channel length L, and the dimension in the direction perpendicular to the channel length L of the ohmic contact layers 8 and 9 is the channel width W. Thereafter, through the same steps as in the first embodiment, the liquid crystal display elements shown in FIGS. 9A and 9B are obtained.

  In the initial step, the source / drain electrode forming film and the first ohmic contact layer forming layer 21 are continuously formed on the upper surface of the glass substrate 1, and the first ohmic contact layer forming layer 21 is formed. For example, resist patterns 22a and 22b as shown in FIGS. 10A and 10B are formed on the upper surface, and the first ohmic contact layer forming layer 21 and the source / drain electrodes are formed using the resist patterns 22a and 22b as a mask. By continuously etching the film, for example, as shown in FIGS. 11A and 11B, second ohmic contact layer forming layers 21a and 21b are formed under the resist patterns 22a and 22b. The source electrode 6 and the drain electrode 7 may be formed under the ohmic contact layer forming layers 21a and 21b.

(Third embodiment)
FIG. 15A shows a transmission plan view of the main part of a liquid crystal display device provided with a thin film transistor as a third embodiment of the present invention, and FIG. 15B shows the XV B -XV B line of FIG. FIG. This liquid crystal display element is different from the liquid crystal display elements shown in FIGS. 9A and 9B in that an upper insulating film 16 made of silicon nitride is provided on the upper surface of the insulating film 12 including the gate electrode 13, and the upper insulating film. This is that a substantially lattice-shaped auxiliary capacitance electrode 17 made of a light-shielding metal such as aluminum or chromium is provided at a predetermined position on the upper surface of 16.

  In this case, an overcoat film 14 made of silicon nitride is provided on the upper surface of the upper insulating film 16 including the auxiliary capacitance electrode 17. A pixel electrode 2 made of a transparent conductive material such as ITO is provided at a predetermined position on the upper surface of the overcoat film 14 through the contact hole 15 provided in the overcoat film 14, the upper insulating film 16, and the insulating film 12. It is provided connected to.

  Then, the entire peripheral portion of the pixel electrode 2 is overlapped with a substantially lattice-shaped auxiliary capacitance electrode 17 disposed around the pixel electrode 2. The substantially lattice-shaped auxiliary capacitance electrode 17 includes a first auxiliary capacitance electrode portion 17a including a portion overlapped with the data line 5, a second auxiliary capacitance electrode portion 17b including a portion overlapped with the scanning line 2, The third auxiliary capacitance electrode portion 17c includes a portion overlapped with the thin film transistor 3.

  In this case, since the first auxiliary capacitance electrode portion 17a having a width larger than the width of the data line 5 is provided between the data line 5 and the pixel electrode 2, the first auxiliary capacitance electrode portion 17a Generation of coupling capacitance between the data line 5 and the pixel electrode 2 can be prevented, and therefore vertical crosstalk can be prevented from occurring, and display characteristics can be improved. In addition, since the second auxiliary capacitance electrode portion 17b having a width wider than the width of the scanning line 4 is provided between the scanning line 4 and the pixel electrode 2, the second auxiliary capacitance electrode portion 17b performs scanning. It is possible to prevent a coupling capacitance from being generated between the line 4 and the pixel electrode 2, and thus it is possible to prevent the occurrence of vertical crosstalk and improve the display characteristics.

(Fourth embodiment)
FIG. 16A shows a transmission plan view of the main part of a liquid crystal display device having a thin film transistor as a fourth embodiment of the present invention, and FIG. 16B shows the XVI B -XVI B line of FIG. FIG. This liquid crystal display element is different from the liquid crystal display element shown in FIGS. 15A and 15B in that an upper layer insulating film 16 is not provided and aluminum, chromium, etc. are formed at predetermined positions on the upper surface of the insulating film 12. The gate electrode 13 made of a light-shielding metal, the scanning line 4 connected to the gate electrode 13, and the auxiliary capacitance electrode 17 are provided.

  In this case, the auxiliary capacitance electrode 17 includes a first auxiliary capacitance electrode portion 17 d including a portion overlapped with a part of the data line 5, and a second auxiliary electrode disposed in parallel with the scanning line 4 in the vicinity of the scanning line 4. The auxiliary capacitance electrode portion 17e and a third auxiliary capacitance electrode portion 17f arranged along a predetermined edge of the pixel electrode 2 are included.

  In the method of manufacturing the thin film transistor portion of the liquid crystal display element, a gate electrode 13 made of a light-shielding metal such as aluminum or chromium is formed at each predetermined location on the upper surface of the insulating film 12, and the scanning line 4 connected to the gate electrode 13 and Since the auxiliary capacitance electrode 17 can be formed at the same time, compared to the case shown in FIGS. 15A and 15B, a step of forming an upper insulating film and a step of forming a film for forming an auxiliary capacitance electrode The step of forming the resist pattern for forming the auxiliary capacitance electrode, the step of etching the auxiliary capacitance electrode forming film using the resist pattern as a mask to form the auxiliary capacitance electrode, and the step of peeling the resist pattern can be omitted. The number of processes can be reduced.

(Fifth embodiment)
FIG. 17A shows a transmission plan view of the main part of a liquid crystal display device provided with a thin film transistor as a fourth embodiment of the present invention, and FIG. 17B shows a line XVII B -XVII B in FIG. FIG. This liquid crystal display element differs from the liquid crystal display element shown in FIGS. 15A and 15B in that it is made of a conductive material that can make ohmic contact with zinc oxide without providing the ohmic contact layers 8 and 9, for example, ITO. The semiconductor thin film 10 made of intrinsic zinc oxide is provided at a predetermined position on the upper surface of the source electrode 6, a predetermined position on the upper surface of the drain electrode 7 also made of ITO, and the upper surface of the glass substrate 1 therebetween. In this case, the data line 5 is also formed of, for example, ITO.

  In this method of manufacturing the thin film transistor portion of the liquid crystal display element, the first ohmic contact layer forming layer is formed, the second ohmic contact layer forming resist pattern is formed, and the resist pattern is used as a mask. The step of etching the first ohmic contact layer forming layer to form the second ohmic contact layer and the step of removing the resist pattern can be omitted, and the number of steps can be reduced.

(Other embodiments)
The formation of the semiconductor thin film forming film 10a and the ohmic contact layer forming layer 21 is not limited to the plasma CVD method, and may be a sputtering method, a vapor deposition method, a casting method, a plating method, or the like. The ohmic contact layers 8 and 9 are not limited to n-type zinc oxide but may be p-type zinc oxide, or may be zinc oxide in which conductivity is changed by causing oxygen deficiency.

  Further, a base insulating film may be provided between the glass substrate 1 and the source electrode 6 and the drain electrode 7. For example, when the base insulating film is formed of an ion barrier material, impurity diffusion from the glass substrate 1 can be suppressed, and reaction between the glass substrate 1 and the zinc oxide film can be suppressed. When a material having a lattice constant or crystal structure close to that of zinc oxide is selected as the material for the base insulating film, the crystallinity of the zinc oxide film can be improved.

FIG. 2 is a transmission plan view of the main part of the liquid crystal display device including the thin film transistor as the first embodiment of the present invention. FIG. 2A is a partially enlarged plan view of a part of FIG. 1, and FIG. 2B is a sectional view taken along the line II B -II B. FIG. 3A is a transparent plan view of an initial process in manufacturing the thin film transistor portion shown in FIG. 2, and FIG. 3B is a cross-sectional view taken along the line III B -III B. FIG. 4A is a transmission plan view of the process following FIG. 3, and FIG. 4B is a cross-sectional view taken along the line IV B -IV B. (A) is transparent plan view of a step subsequent to FIG. 4, (B) is a sectional view along its V B -V B line. (A) is the permeation | transmission top view of the process following FIG. 5, (B) is sectional drawing which follows the VI B- VI B line. FIG. 7A is a transparent plan view of the process following FIG. 6, and FIG. 7B is a sectional view taken along the line VII B- VII B. (A) is a transmission plan view of the process following FIG. 7, (B) is a cross-sectional view along the VIII B -VIII B line. FIG. 5A is a transmission plan view of a main part of a liquid crystal display device including a thin film transistor as a second embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along the line IX B -IX B. FIG. 10A is a transmission plan view of an initial step in manufacturing the thin film transistor portion shown in FIG. 9, and FIG. 10B is a cross-sectional view taken along line X B -X B. (A) is a transmission plan view of the process following FIG. 10, and (B) is a cross-sectional view along the XI B -XI B line. (A) is a transmission plan view of the process following FIG. 11, and (B) is a cross-sectional view along the XII B -XII B line. (A) is a transmission plan view of the process following FIG. 12, and (B) is a cross-sectional view along the XIII B -XIII B line. (A) is a transmission plan view of the process following FIG. 13, and (B) is a cross-sectional view along the XIV B -XIV B line. (A) the third transparent plan view of a main part of a liquid crystal display device having a thin film transistor according to an embodiment, (B) is a sectional view taken along the XV B -XV B line of the present invention. (A) is a transmission top view of the principal part of the liquid crystal display element provided with the thin-film transistor as 4th Embodiment of this invention, (B) is sectional drawing which follows the XVI B- XVI B line. (A) is a transmission plan view of the principal part of the liquid crystal display element provided with the thin film transistor as the fifth embodiment of the present invention, and (B) is a sectional view taken along the line XVII B -XVII B.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Pixel electrode 3 Thin film transistor 4 Scan line 5 Data line 6 Source electrode 7 Drain electrode 8, 9 Ohmic contact layer 10 Semiconductor thin film 11 Protective film 12 Insulating film 13 Gate electrode 14 Overcoat film 15 Contact hole 16 Upper insulating film 17 Auxiliary capacitance electrode

Claims (21)

  1.   A semiconductor thin film; a protective film provided on the entire top surface of the semiconductor thin film; an insulating film provided on the protective film; a gate electrode provided on the insulating film on the semiconductor thin film; and the semiconductor thin film A thin film transistor comprising a source electrode and a drain electrode provided below and electrically connected to the semiconductor thin film.
  2.   2. The thin film transistor according to claim 1, wherein the semiconductor thin film contains zinc oxide.
  3.   2. The invention according to claim 1, wherein ohmic contact layers project from the opposing end surfaces of the source electrode and the drain electrode on the upper surfaces of the source electrode and the drain electrode, respectively, below the semiconductor thin film. A thin film transistor, wherein the thin film transistor is provided.
  4.   2. The end face of the ohmic contact layer facing each other on the upper surface of the source electrode and the drain electrode under the semiconductor thin film is the same as the facing face of the source electrode and the drain electrode. A thin film transistor characterized by being provided in a shape.
  5.   5. The thin film transistor according to claim 3, wherein the ohmic contact layer contains zinc oxide.
  6.   6. The thin film transistor according to claim 5, wherein the ohmic contact layer is made of ITO.
  7.   2. The thin film transistor according to claim 1, wherein the semiconductor thin film contains zinc oxide and is directly provided on each upper surface of the source electrode and the drain electrode.
  8.   8. The thin film transistor according to claim 7, wherein the source electrode and the drain electrode are made of ITO.
  9.   2. The thin film transistor according to claim 1, further comprising an overcoat film covering the gate electrode.
  10.   10. The thin film transistor according to claim 9, wherein a pixel electrode is provided on the upper surface of the overcoat film so as to be connected to the source electrode.
  11.   11. The thin film transistor according to claim 10, wherein an auxiliary capacitance electrode is provided between the insulating film and the overcoat film.
  12.   12. The invention according to claim 11, wherein a data line connected to the drain electrode is provided on the same layer as the drain electrode, and the auxiliary capacitance electrode is overlapped with the data line through the insulating film. A thin film transistor, wherein a width of a portion of the auxiliary capacitance electrode overlapped with the data line is wider than a width of the data line.
  13.   13. The thin film transistor according to claim 12, wherein the auxiliary capacitance electrode is overlapped with all peripheral portions of the pixel electrode.
  14.   14. The thin film transistor according to claim 13, wherein the auxiliary capacitance electrode is provided on an upper surface of an upper insulating film provided so as to cover the gate electrode under the overcoat film.
  15.   The scanning line connected to the gate electrode is provided on the same layer as the gate electrode, and the auxiliary capacitance electrode is overlapped with the scanning line via the upper insulating film. A thin film transistor having a portion, wherein the width of the portion of the auxiliary capacitance electrode overlapped with the scan line is wider than the width of the scan line.
  16.   15. The thin film transistor according to claim 14, wherein the auxiliary capacitance electrode is provided on an upper surface of the insulating film.
  17.   A method of manufacturing a thin film transistor, comprising: forming a semiconductor thin film on a source electrode and a drain electrode; forming the semiconductor thin film in a device shape by photolithography; and forming an insulating film and a gate electrode on the semiconductor thin film formed in the device shape When forming the semiconductor thin film in the device shape, a protective film is provided on the semiconductor thin film, a photoresist is formed on the protective film in the device shape, and then the semiconductor thin film is formed in the device shape. A method for manufacturing a thin film transistor.
  18.   18. The method of manufacturing a thin film transistor according to claim 17, wherein the semiconductor thin film contains zinc oxide.
  19.   The ohmic contact layer is formed on the source electrode and the drain electrode so as to protrude from the end surfaces facing each other of the source electrode and the drain electrode, respectively. And forming the semiconductor thin film.
  20.   The invention according to claim 17, wherein ohmic contact layers are formed on the source electrode and the drain electrode, respectively, so that their opposing end faces have the same shape as the opposing end faces of the source electrode and the drain electrode, Next, a method of manufacturing a thin film transistor, wherein the semiconductor thin film is formed.
  21.   21. The method of manufacturing a thin film transistor according to claim 19, wherein the ohmic contact layer contains zinc oxide.
JP2005081117A 2005-03-22 2005-03-22 Thin-film transistor and manufacturing method thereof Pending JP2006269469A (en)

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Cited By (9)

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JP2008098447A (en) * 2006-10-12 2008-04-24 Casio Comput Co Ltd Thin film transistor, and its manufacturing method
JP2008135520A (en) * 2006-11-28 2008-06-12 Casio Comput Co Ltd Thin-film transistor panel and its manufacturing method
JP2008141113A (en) * 2006-12-05 2008-06-19 Canon Inc Etching method, pattern formation method, method for manufacturing thin film transistor, and etching solution
WO2009028453A1 (en) * 2007-08-31 2009-03-05 Konica Minolta Holdings, Inc. Thin film transistor
JP2009147039A (en) * 2007-12-13 2009-07-02 Casio Comput Co Ltd Thin film transistor panel and method of manufacturing the same
JP2010232645A (en) * 2009-03-05 2010-10-14 Semiconductor Energy Lab Co Ltd Semiconductor device, and method of manufacturing the same
US7863607B2 (en) 2007-06-14 2011-01-04 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7910920B2 (en) 2007-02-16 2011-03-22 Samsung Electronics Co., Ltd. Thin film transistor and method of forming the same
US7994510B2 (en) 2008-05-30 2011-08-09 Samsung Mobile Display Co., Ltd. Thin film transistor, method of manufacturing the same and flat panel display device having the same

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JP2004319673A (en) * 2003-04-15 2004-11-11 Masashi Kawasaki Semiconductor device and its manufacturing method
JP2005033172A (en) * 2003-06-20 2005-02-03 Masashi Kawasaki Semiconductor device, manufacturing method therefor, and electronic device

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JP2004319673A (en) * 2003-04-15 2004-11-11 Masashi Kawasaki Semiconductor device and its manufacturing method
JP2005033172A (en) * 2003-06-20 2005-02-03 Masashi Kawasaki Semiconductor device, manufacturing method therefor, and electronic device

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008098447A (en) * 2006-10-12 2008-04-24 Casio Comput Co Ltd Thin film transistor, and its manufacturing method
JP2008135520A (en) * 2006-11-28 2008-06-12 Casio Comput Co Ltd Thin-film transistor panel and its manufacturing method
JP2008141113A (en) * 2006-12-05 2008-06-19 Canon Inc Etching method, pattern formation method, method for manufacturing thin film transistor, and etching solution
US7960289B2 (en) 2006-12-05 2011-06-14 Canon Kabushiki Kaisha Etching method, pattern forming process, thin-film transistor fabrication process, and etching solution
KR101410926B1 (en) 2007-02-16 2014-06-24 삼성전자주식회사 Thin film transistor and method for forming the same
US8614442B2 (en) 2007-02-16 2013-12-24 Samsung Electronics Co., Ltd. Thin film transistor and method of forming the same
US7910920B2 (en) 2007-02-16 2011-03-22 Samsung Electronics Co., Ltd. Thin film transistor and method of forming the same
US7863607B2 (en) 2007-06-14 2011-01-04 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
WO2009028453A1 (en) * 2007-08-31 2009-03-05 Konica Minolta Holdings, Inc. Thin film transistor
JP2009147039A (en) * 2007-12-13 2009-07-02 Casio Comput Co Ltd Thin film transistor panel and method of manufacturing the same
US7994510B2 (en) 2008-05-30 2011-08-09 Samsung Mobile Display Co., Ltd. Thin film transistor, method of manufacturing the same and flat panel display device having the same
JP2010232645A (en) * 2009-03-05 2010-10-14 Semiconductor Energy Lab Co Ltd Semiconductor device, and method of manufacturing the same
US8759206B2 (en) 2009-03-05 2014-06-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9941393B2 (en) 2009-03-05 2018-04-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US10326008B2 (en) 2009-03-05 2019-06-18 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

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