JP2006269002A - Shift register circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register circuit, a display apparatus, and portable equipment provided with the display apparatus in which further miniaturization and weight-reduction are achieved and the further reduction of power consumption can be performed and a utilization value in industry is high. <P>SOLUTION: In the shift register circuit 10, shift register units (SR) driven according to a plurality of clock signals (CLK1, CLK2) having mutually inverse phases of a plurality of stages (SR1, SR2, SR3, ...) are connected in series, a start pulse signal (STH) is received, and the signal is transferred successively according to the clock signals (CLK1, CLK2), the circuit is provided with a start pulse signal generating part 13 generating a start pulse signal based on a start pulse generating signal (SP1) generated in the clock signal (CLK2). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention includes a shift register circuit having a plurality of shift registers connected in series, receiving a start pulse signal, and sequentially transferring it according to a clock signal, a display device including the shift register circuit, and a display thereof The present invention relates to a portable device including the device.

  Conventionally, flat displays in which a large number of pixels are formed on one substrate such as an LCD (liquid crystal display) and an organic EL (electroluminescence) display have been widely used. This flat display includes an active matrix display panel in which a selection transistor is arranged for each pixel arranged in a matrix to control display in each pixel, and is suitable for high-definition display.

  In this active matrix type display panel, in order to supply a video signal to be displayed to each two-dimensional pixel, a vertical drive circuit that shifts the display line in the vertical direction and a video sequentially for each pixel in the horizontal direction. A horizontal drive circuit is required to supply the signal.

  In the horizontal drive circuit, the shift register circuit of the horizontal drive circuit takes in the high level of the start pulse signal indicating the start of one horizontal period and transfers it according to the horizontal transfer clock signal.

  Then, by synchronizing the horizontal transfer clock signal with the data signal for each pixel of the video signal, the output of the horizontal shift register circuit opens a switch between the video signal line and the data line for each column of the panel, A data signal for each pixel can be supplied to a corresponding data line.

  On the other hand, also in the vertical drive circuit, the vertical transfer start pulse signal is transferred according to the vertical transfer clock signal in the shift register circuit of the vertical drive circuit, and the row of the panel to which the data signal is supplied is selected.

  Then, the data signal of each pixel is supplied to the pixel by the horizontal driving circuit and the vertical driving circuit.

  FIG. 6 is a block diagram of a shift register circuit formed by connecting a plurality of shift register units SR in series.

  As shown in FIG. 6, this shift register circuit is configured by connecting a plurality of shift register units SR1, SR2, SR3, SR4,. The shift register units SR at each stage are supplied with clock signals CLK1 and CLK2 having opposite phases to each other via respective clock input terminals clk1in and clk2in.

  A start pulse signal (STH) is supplied to the input terminal (in) of the first-stage shift register unit SR1. The input terminals (in) of the shift register units SR2, SR3, SR4,... At the second and subsequent stages are output terminals of the shift register units SR1, SR2, SR3, SR4,. Pulses S1, S2, S3... Output from (out) are input.

  The clock signals CLK1, CLK2 are input to the shift register units SR1, SR2, SR3, SR4,..., And the start pulse signal STH is transferred. Further, selection signals are output from the respective shift register units SR1, SR2, SR3, SR4,.

As a prior art related to the shift register circuit, for example, there is the following Patent Document 1.
JP-A-8-212793

  In the conventional shift register circuit described above, a dedicated wiring, input terminal, or circuit is required to input the start pulse signal (STH), and accordingly, the circuit scale increases and the current consumption also increases. There was a problem. In addition, due to the downsizing, weight reduction, diversification of designs, and consideration for environmental impacts of mobile devices, display devices mounted on mobile devices are required to be smaller, lighter, and more space-saving. There is a high demand for energy saving.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to create a start pulse signal (STH) inside a shift register circuit and to generate a start pulse signal (STH). ) To reduce the circuit scale by reducing the external input, to achieve a smaller size and lighter weight, and to further reduce power consumption by reducing the circuit scale, To provide a display device including the shift register circuit, a driving semiconductor chip used in the display device, and a portable device including the display device.

  To achieve the above object, a shift register circuit according to the first aspect of the present invention ("shift register circuit 10" is a corresponding example) is a shift register driven in response to a plurality of clock signals having opposite phases. A plurality of units ("shift register unit SR1" is a corresponding example) are connected in series, a start pulse signal ("start pulse signal (STH)" is a corresponding example) is received, and the clock signal ("clock signal" CLK1, CLK2 "are shift register circuits that sequentially transfer according to a corresponding example), and start pulses are generated based on a start pulse generation signal (" start pulse generation signal SP1 "is a corresponding example) formed in the clock signal. Start pulse signal generator for generating a signal ("start pulse signal generator 13" corresponds to Shift register circuit, characterized in that it is provided an example) that.

  In the shift register circuit according to the first aspect, as described above, the start pulse signal generation unit 13 is provided, and the start pulse signal (STH) is generated by the shift register circuit. Therefore, the start pulse signal is input from the outside. This eliminates the need to reduce the circuit scale, reduce the number of input terminals, reduce the circuit scale, and reduce power consumption. Accordingly, it is possible to provide a shift register circuit, a display device, and a portable device including the display device, which can be further reduced in size and weight and have higher industrial utility value that can reduce power consumption.

  The shift register circuit according to the second aspect of the present invention (“shift register circuit 10” is a corresponding example) is preferably the start pulse signal generating unit (“start pulse signal” in the shift register circuit according to the first aspect). The generation unit 13 "corresponds to one example), and the one clock formed on one clock signal or the other clock signal by inputting the plurality of clock signals (" clock signals CLK1 and CLK2 "are corresponding examples). Based on the start pulse generation signal in phase with the signal (“start pulse generation signal SP1” is a corresponding example), a NAND circuit that forms a start pulse signal (“NAND circuit 11” is a corresponding example) and an inverter circuit (“ The inverter circuit 12 "corresponds to an AND circuit or NOR circuit (" NOR "). Road 16 "is from the corresponding one example of).

  If comprised in this way, a start pulse signal generation part can be further formed in a shift register circuit with semiconductor technology.

  The shift register circuit according to the third aspect of the present invention (“shift register circuit 10” is a corresponding example) is preferably the start pulse signal generation unit (“start pulse signal”) in the shift register circuit according to the second aspect. The generation unit 13 ”includes a delay circuit that delays a start pulse generation signal (“ start pulse generation signal SP1 ”is a corresponding example) for a predetermined time.

  With this configuration, it is possible to optimally adjust and design the pixel writing timing and the display device operation timing.

  The shift register circuit according to the fourth aspect of the present invention (“shift register circuit 10” is a corresponding example) is preferably the shift register circuit according to the first aspect described above. The start pulse signal generation unit (“start pulse signal generation unit 13, start pulse signal generation unit 16” is a corresponding example) is capable of generating a start pulse generation signal formed in the clock signal according to the scan direction. Based on (“start pulse generation signal SP1” is a corresponding example), a start pulse generation signal is generated.

  With this configuration, the present invention can be further applied to a bidirectional scan type shift register circuit.

  The display device according to the fifth aspect of the present invention ("liquid crystal display module 400" is a corresponding example) is preferably the shift register circuit according to the first aspect, wherein the shift register circuit is an active matrix display panel. It is integrally formed on a transparent substrate (“transparent substrate 410” is a corresponding example).

  If comprised in this way, a shift register circuit can be further provided on flexible substrates, such as a glass substrate and resin, and peripheral circuits, such as an external semiconductor chip of a display apparatus, can be reduced as much as possible.

  The display device according to the sixth aspect of the present invention (“liquid crystal display module 400” is a corresponding example) is preferably the display device according to the fifth aspect described above, preferably based on the synchronizing signal of the video signal. A start pulse signal generation unit (an example corresponding to “start pulse signal generation unit 13”) that forms a start pulse generation signal (an example corresponding to “start pulse generation signal SP1”) corresponds to “clock signal CLK2”. And a drive unit (“drive IC 600” is a corresponding example) that outputs the clock signal to the shift register circuit.

  If comprised in this way, since a drive part can be integrally formed or incorporated as an external IC in the display device, it is possible to reduce the trouble (for example, trouble in designing and assembling work) when incorporating it into a portable device. Can be reduced.

  The driving semiconductor chip according to the seventh aspect of the present invention ("driving IC 600" is a corresponding example) is preferably a driving semiconductor chip for driving a display device according to the fifth aspect, preferably a video signal synchronization signal Based on the above, a start forming a start pulse generation signal (“start pulse generation signal SP1 or start pulse generation signal SP2” is an example corresponding to one example) corresponding to the clock signal (“clock signal CLK2 or clock signal CLK2” is one example) A pulse signal generator (“start pulse signal generator 13” is a corresponding example) is provided, and the clock signal is output to the shift register circuit (“shift register circuit 10” is a corresponding example).

  If constituted in this way, since the drive part which drives a display device can be made into an external component, while being able to simplify the manufacturing process of a display device and improving the yield of a display device, Semiconductor chips can be put on the market, increasing industrial utility value.

  A mobile device according to the eighth aspect of the present invention (an example of “mobile device 800” corresponds) is provided with a display device according to the fifth aspect (an example of “liquid crystal display module 400”).

  In this way, by incorporating a display device with high industrial utility value, productivity and price competitiveness of portable devices can be improved.

  According to the present invention, it is possible to reduce the circuit scale to achieve further miniaturization and weight reduction. Furthermore, a shift register circuit that can realize power saving by reducing the circuit scale, a display device including the shift register circuit, a driving semiconductor chip used in the display device, and a portable device including the display device Is to provide equipment.

  Next, the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described. FIG. 1 is a block diagram of a shift register circuit 10 according to the first embodiment of the present invention, and FIG. 3 is a block configuration diagram of a portable device 800 according to the embodiment of the present invention.

  In FIG. 3, the mobile device 800 is a mobile device including a display unit such as a digital still camera, a digital video camera, a mobile phone, a PDA (personal digital assistance), a car navigation system, or a music playback device. Reference numeral 700 denotes a portable device control unit for controlling display, reproduction, imaging, recording, and other functions of video data in the portable device 800. Reference numeral 600 denotes a driving IC chip for driving and controlling the liquid crystal display module 400, and includes a video signal processing unit 610 and a control unit 620 that process video data and control data supplied from the portable device control unit 700. The liquid crystal display module 400 is a low-temperature polycrystalline silicon TFT (thin film transistor) -LCD, and an H driver (horizontal drive circuit) 100, a V driver (vertical drive circuit) 300, and an active matrix type on a transparent substrate 410 such as glass. A liquid crystal panel 200 is formed. The video signal processing unit 610 and the control unit 620 can be integrally formed on the glass substrate 410.

  Further, when the peripheral circuit such as the H driver 100 is not integrally formed on the transparent substrate 410 such as glass or resin as in the case of the amorphous silicon TFT-LCD or the like, the peripheral circuit is provided with one or more external circuits. It can also be configured as an attached drive device (IC chip).

  Such an external IC chip (including the driving IC 600) may be mounted on the glass substrate 410 by a COB (Chip On Board), TAB (Tape Automated Bonding) method, or the like.

  The video signal processing unit 610 processes the video data (VD) input from the portable device control unit 700 and outputs a display video signal (VS) to the H driver 100, and a timing signal including horizontal and vertical synchronization signals. (TS) is output to the control unit 620. The control unit 620 receives a control signal (CD) from the portable device control unit 700, outputs a horizontal scanning control signal HS to the H driver 100, and outputs a vertical scanning control signal VS to the V driver 300. The horizontal scanning control signal HS includes clock signals CLK1 and CLK2 having opposite phases synchronized with the horizontal synchronizing signal, and the vertical scanning control signal VS includes clocks having opposite phases synchronized with the vertical synchronizing signal. Signals CLK3 and CLK4 are included.

  The H driver 100 and the V driver 300 include a shift register circuit 10 and a shift register circuit 30. As shown in FIG. 1A, the shift register circuit 10 has a configuration in which a plurality of shift register units SR1, SR2, SR3, SR4,... Are connected in series, and includes a NAND circuit 11 and an inverter 12. The start pulse signal (STH1) generation unit 13 is provided. The shift register units SR1, SR2, SR3, SR4,... Of the respective stages are supplied with clock signals CLK1, CLK2 having opposite phases to each other via respective clock input terminals clk1in, clk2in. .

  The clock signals CLK1 and CLK2 are input to the NAND circuit 11, and the AND circuit including the NAND circuit 11 and the inverter 12 constitutes a start pulse signal generation unit 13 that generates a start pulse signal (STH1).

  A start pulse signal (STH) output from the start pulse signal generator 13 is supplied to the input terminal (in) of the first-stage shift register unit SR1. The input terminals (in) of the shift register units SR2, SR3, SR4,... At the second and subsequent stages are output terminals of the shift register units SR1, SR2, SR3, SR4,. Pulse signals S1, S2, S3... Output from (out) are input as start pulse signals.

  The clock signals CLK1, CLK2 are input to the shift register units SR1, SR2, SR3, SR4,... As drive clocks, and the start pulse signals are sequentially transferred.

  Each of the shift register units SR1, SR2, SR3, SR4,... Is configured as shown in FIG.

  The start pulse signal input from the input terminal (in) is input to the first clocked inverter 20, and the output of the first clocked inverter 20 is input to the inverter 22 and the inverter 23. The output of the inverter 22 is input to the second clocked inverter 21, and the second clocked inverter 21 and the inverter 22 form a holding loop that holds the output of the first clocked inverter 20. .

  The clock signals CLK1 and CLK2 having opposite phases are supplied to the first clocked inverter 20 and the second clocked inverter 21 as drive clocks. That is, when the clock signal CLK1 is at a high level (CLK2 is at a low level), the first clocked inverter 20 is turned on (inverter operation), and the second clocked inverter 21 is turned off (output high impedance state). Conversely, when the clock signal CLK1 is at a low level (CLK2 is at a high level), the first clocked inverter 20 is turned off (output high impedance state), and the second clocked inverter 21 is turned on (inverter operation). To do.

  The first clocked inverter 20 receives the output of the preceding shift register unit SR. The second clocked inverter 21 and the inverter 22 form a holding loop that holds the output of the first clocked inverter 20.

  Thereby, the pulse signal input from the input terminal (in) is shifted by the first clocked inverter 20 in synchronization with the clock signals CLK1 and CLK2. The output of the first clocked inverter 20 is inverted by the inverter 23 and supplied as a start pulse signal to the next shift register units SR2, SR3, SR4,.

  For example, when a high level signal is input to the input terminal (in) and the clock signal CLK1 becomes high level, the low level inverted by the first clocked inverter 20 is inverted by the inverters 22 and 23. And the output terminal (out) goes high. Next, when the clock signal CLK1 becomes low level, the first clocked inverter 20 is turned off and the gate inverter 21 is turned on. Accordingly, the output of the inverter 22 is inverted and supplied to the input side, and the input of the inverter 22 is fixed at the low level and the output is fixed at the high level. For this reason, the output terminal (out) is maintained at a high level.

  Next, when the clock signal CLK1 becomes high level, if the input terminal (in) is already at low level, this low level is inverted by the first clocked inverter 20, and the output terminal (out) returns to low level.

  Thus, the shift register unit SR takes in the signal of the input terminal (in) every time the clock signal CLK1 rises, and maintains the state until the next rise of the clock signal CLK1.

  Next, the operation of the shift register circuit 10 will be described with reference to the operation timing chart of FIG. 1B.

  Control unit 620 outputs clock signals CLK1 and CLK2 synchronized with the horizontal synchronization signal. As shown in FIG. 1B, the control unit 620 forms a period (start pulse generation signal SP1) in which the high level of 1.5 cycles continues in the first clock of one horizontal scanning period in the clock signal CLK2.

  The start pulse signal generation unit 13 generates a start pulse signal (STH1) based on the clock signals CLK1 (high level) and CLK2 (high level: start pulse generation signal SP1), and shifts the generated start pulse signal (STH1). Output to the register unit SR1.

  The shift register unit SR1 transfers the start pulse signal (STH1) based on the clock signals CLK1 and CLK2, and outputs a pulse signal S1. The shift register unit SR2 at the next stage transfers the pulse signal S1 based on the clock signals CLK1 and CLK2 and outputs the pulse signal S2. Thereafter, this operation is continued up to the shift register unit at the final stage.

  The configuration of the shift register 10 can also be applied to the shift register 30 of the V driver 300.

  As described above, in the first embodiment, the shift register circuit 10 is provided with the start pulse signal generation unit 13 including the NAND circuit 11 and the inverter 12 to generate the start pulse signal (STH). There is no need to supply from the outside, and the circuit scale can be reduced by reducing the number of wirings, the circuit area, and the number of input terminals, and the power consumption can be reduced. Therefore, further miniaturization and weight reduction can be realized. Further, by reducing the circuit scale, it is possible to provide a shift register circuit, a display device, and a portable device including the display device, which can further reduce power consumption and have high industrial utility value.

  4 is a diagram showing a second embodiment of the shift register circuit 10 of the present invention, FIG. 4A is a block diagram of the shift register circuit 10 showing the second embodiment, and FIG. FIG. 4C is a circuit configuration diagram of the delay circuit 14, and FIG. 4C is an operation timing diagram of the shift register circuit 10 showing the second embodiment.

  In FIG. 4, the difference in configuration from the shift register circuit 10 according to the first embodiment is that a delay circuit 14 is inserted between the start pulse signal generator 13 and the input terminal (in) of the shift register unit SR1. It is a point. As a result, the start pulse signal (STH1) generated by the start pulse signal generator 13 is input to the delay circuit 14 as shown in FIG. 4B and output as the start pulse signal 2 (STH2) delayed by a predetermined time. The shift register units SR1, SR2, SR3, SR4,... Operate with a delay of the predetermined time.

  Thus, in the second embodiment, the operation timing can be optimally adjusted, and the shift register circuit having high industrial utility value, the display device including the shift register circuit, and the display device are used. The portable semiconductor device provided with the driving semiconductor chip and the display device thereof can be provided.

  FIG. 5 is a diagram showing a third embodiment of the shift register circuit 10 of the present invention, FIG. 5A is a block diagram of the shift register circuit 10 showing the third embodiment, and FIG. FIG. 5C is an operation timing chart at the time of forward scanning of the shift register circuit 10 showing the third embodiment, and FIG. 5C is an operation timing chart at the time of backward scanning.

  In the figure, the difference from the configuration of the shift register circuit 10 according to the second embodiment is that the third embodiment is a bidirectional scan type shift register circuit, and forward scan (from the left end to the right end of the drawing). In addition to the configuration of the second embodiment that operates at the time of scanning, the start pulse signal generation unit 16 includes a NOR circuit that generates a start pulse signal (STH3) during backward scanning (scanning from the right end to the left end of the drawing). And a delay circuit 15 for delaying and outputting the generated start pulse signal (STH3) for a predetermined time is connected to the rightmost stage (final stage) SR101 of the shift register unit SR, and further according to the scanning direction. Provided a selector switch (not shown) for switching the input terminal (in) and the output terminal (out) of the shift register unit SR. It is.

  At the time of forward scanning, the control unit 620 receives a clock signal CLK2 in which a high level of 1.5 cycles (start pulse generation signal SP1) is formed at the beginning of one horizontal scanning period as shown in FIG. 5B. Output. A start pulse signal generation unit 13 including a NAND circuit 11 and an inverter 12 outputs a start pulse signal (STH1) in response to clock signals CLK1 (high level) and CLK2 (high level), and a delay circuit 14 includes the start pulse signal ( A signal (STH2) obtained by delaying STH1) for a predetermined time is output to the leftmost shift register unit SR1.

  On the other hand, at the time of reverse scanning, the control unit 620 generates a clock signal CLK2 in which a period in which a low level of 1.5 cycles continues at the beginning of one horizontal scanning period (start pulse generation signal SP2) is formed as shown in FIG. 5C. Is output. The start pulse signal generation unit 16 including the NOR circuit 16 outputs a start pulse signal (STH3) in response to the clock signals CLK1 (low level) and CLK2 (low level: start pulse generation signal SP2), and the delay circuit 15 includes the start pulse signal. A signal (STH4) obtained by delaying (STH3) for a predetermined time is output to the rightmost shift register unit SR101.

  The shift register unit SR101 transfers the start pulse signal (STH4) based on the clock signals CLK1 and CLK2, and outputs the pulse signal S100 to the shift register unit SR100. The shift register unit SR100 transfers the pulse signal S100 based on the clock signals CLK1 and CLK2 and outputs the pulse signal S99 to the shift register unit SR99. Thereafter, this operation is performed up to the leftmost shift register unit SR1. continue.

  As described above, in the third embodiment, in the bidirectional type shift register circuit, the start pulse signal generation unit 13 including the NAND circuit 11 and the inverter 12 that generate the start pulse signal at the time of forward scanning is provided. Since the start pulse signal generation unit 16 including a NOR circuit that generates a start pulse signal at the time of direction scanning is provided, it is not necessary to supply the start pulse signal from the outside, and the number of wirings, circuit area, and number of input terminals are reduced. Thus, the circuit scale can be reduced and the power consumption can be reduced. Accordingly, a shift register circuit that can be further reduced in size and weight, and that can further reduce power consumption, has a high industrial utility value, a display device including the shift register circuit, and a driving device used in the display device A portable device including a semiconductor chip and its display device can be provided.

  Note that the configuration of the shift register circuit described above can be applied not only to the shift register circuit 10 of the H driver 100 shown in FIG. 3 but also to the shift register circuit 30 of the V driver 300.

  The embodiments disclosed herein are illustrative in all respects, and the present invention is not limited to the above-described embodiments, and should not be considered as limiting. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims for patent, and all modifications within the meaning and scope equivalent to the scope of claims for patent are included.

  For example, in the above-described embodiment, an example in which the present invention employs the liquid crystal panel 200 as an example of a display device has been described. Other display panels such as can be adopted.

  In the above-described embodiment, the mobile device, the mobile phone, the digital camera, the PDA (Personal Digital Assistance), the portable game machine, the small personal computer, the liquid crystal projector, and the like have been described as examples. You may employ | adopt for display apparatuses, such as a television, for example.

FIG. 1A is a block diagram of the shift register circuit 10 according to the first embodiment of the present invention, and FIG. 1B is an operation timing diagram. FIG. 2 is a block diagram of shift register units SR1, SR2, SR3, SR4,. It is a block block diagram of the portable apparatus 800 which concerns on embodiment of this invention. 4A is a block diagram of the shift register circuit 10 according to the second embodiment of the present invention, FIG. 4B is an operation timing diagram, and FIG. 4C is a circuit configuration diagram of the delay circuit 14. FIG. 5A is a block diagram of the shift register circuit 10 according to the third embodiment, FIG. 5B is an operation timing diagram during forward scanning, and FIG. 5C is an operation timing diagram during backward scanning. It is the block diagram which showed the structure of the conventional shift register circuit.

Explanation of symbols

10 shift register circuit 30 shift register circuit SR1, SR2, SR3, SR4,..., SR101 shift register unit clk1in, clk2in clock input terminal CLK1, CLK2, CLK3, CLK clock signal STH1, STH2, STH3, STH4 start pulse signal SP1, SP2 Start pulse generation signal SP1
in input terminal out output terminal 11 NAND circuit 12 inverter 13 start pulse signal generators 14 and 15 delay circuit 16 start pulse signal generator (NOR circuit)
20 First clocked inverter 21 Second clocked inverter 22, 23 Inverter 100 H (horizontal) driver 200 Liquid crystal panel (active matrix display panel)
300 V (vertical) driver 400 Liquid crystal display module (display device)
410 Transparent substrate 600 Driving IC (driving unit, driving semiconductor chip)
610 Video signal processing unit 620 Control unit (start pulse signal generation unit)
700 portable device control unit 800 portable device

Claims (8)

A shift register circuit that is connected in series with a plurality of shift register units that are driven in response to a plurality of clock signals that are out of phase with each other, accepts a start pulse signal, and sequentially transfers it according to the clock signal,
A shift register circuit comprising: a start pulse signal generation unit that generates a start pulse signal based on a start pulse generation signal formed in the clock signal.   The start pulse signal generation unit receives the plurality of clock signals, and based on the start pulse generation signal in phase with the one clock signal formed in one clock signal or the other clock signal, 2. The shift register circuit according to claim 1, wherein the shift register circuit comprises an AND circuit or a NOR circuit comprising a NAND circuit and an inverter circuit.   The shift register circuit according to claim 2, wherein the start pulse signal generation unit includes a delay circuit that delays the start pulse generation signal for a predetermined time.   The shift register circuit is capable of bidirectional scanning, and the start pulse signal generation unit generates a start pulse generation signal based on a start pulse generation signal formed in the clock signal according to the scan direction. The shift register circuit according to claim 1.   2. A display device, wherein the shift register circuit according to claim 1 is integrally formed on a transparent substrate of an active matrix display panel.   A start pulse signal generation unit that forms a start pulse generation signal in the clock signal based on a synchronization signal of a video signal, and a drive unit that outputs the clock signal to the shift register circuit. The display device according to claim 5.   6. The display device according to claim 5, further comprising a start pulse signal generation unit that forms a start pulse generation signal in the clock signal based on a synchronization signal of a video signal, and outputs the clock signal to the shift register circuit. A semiconductor chip for driving.   A portable device comprising the display device according to claim 5.

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