JP2006237674A - Patch antenna and rfid inlet - Google Patents

Patch antenna and rfid inlet Download PDF

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Publication number
JP2006237674A
JP2006237674A JP2005045088A JP2005045088A JP2006237674A JP 2006237674 A JP2006237674 A JP 2006237674A JP 2005045088 A JP2005045088 A JP 2005045088A JP 2005045088 A JP2005045088 A JP 2005045088A JP 2006237674 A JP2006237674 A JP 2006237674A
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antenna
slit
pair
opening
dielectric
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Takeshi Fujiwara
Masahide Tanaka
将英 田中
武 藤原
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Suncall Corp
サンコール株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a patch antenna and an RFID inlet that can be downsized to the utmost extent. <P>SOLUTION: The patch antenna includes a ground side and an antenna side via a dielectric body. An opening to expose the dielectric body is formed to the antenna side. The opening is configured such that a region of the antenna side demarcated by the dielectric body exposed via the opening forms a matching circuit with respect to a transmission reception element. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、パッチアンテナ、並びに、パッチアンテナ及び送受信素子を有するRFIDインレットに関する。 The present invention is a patch antenna, as well as an RFID inlet having a patch antenna and a transmission and reception device.

パッチアンテナ及び送受信素子を有するRFIDインレットは、識別情報の正確且つ効率的な送受信を行えるものとして、物流管理や人の入出退管理等の種々の分野において非常に注目されている。 RFID inlet having a patch antenna and the transceiver elements, as capable of performing accurate and efficient transmission and reception of the identification information, has received considerable attention in various fields of exit management, etc. entering and leaving logistics and human.

しかしながら、従来のRFIDインレットは、省サイズ化や、パッチアンテナと送受信素子との接続作業性に関して、十分な考慮がなされていなかった。 However, conventional RFID inlets, saving size reduction and, with respect to the workability of connecting the patch antenna and the transmitting and receiving elements, sufficient consideration has not been made.
図8は、従来のRFIDインレットにおけるパッチアンテナの一例を示す斜視図である。 Figure 8 is a perspective view showing an example of a patch antenna in a conventional RFID inlets.

前記パッチアンテナ100は、導体によって形成されるグラウンド面110と、該グラウンド面110上に載置された誘電体120と、導体によって形成されたアンテナ面130であって、前記誘電体120上に載置されたアンテナ面130とを有している。 The patch antenna 100 includes a ground plane 110 formed by a conductor, and placed on the dielectric 120 on the ground plane 110, an antenna surface 130 formed by a conductor, placing on the dielectric 120 and an antenna plane 130 location.
そして、前記送受信素子(図示せず)は、一対の接続端子の一方が給電点141において前記グラウンド面に接続され、且つ、他方が給電点142において整合回路150を介して前記アンテナ面130に接続されている。 Then, the transceiver device (not shown), one of the pair of connection terminals are connected to the ground plane at the feed point 141, and, connected to the antenna surface 130 and the other through the matching circuit 150 at the feed point 142 It is.

詳しくは、図8に示すように、従来のRFIDインレットにおいては、前記整合回路150が前記アンテナ面130の外部に設けられている。 Specifically, as shown in FIG. 8, in the conventional RFID inlets, the matching circuit 150 is provided outside of the antenna surface 130.
従って、RFIDインレット全体の縮小化を十分には図ることができなかった。 Therefore, it was not possible to achieve the sufficient reduction of the entire RFID inlet.

さらに、図8に示す従来例においては、前記送受信素子は、一対の接続端子の一方が前記誘電体120上に設けられた整合回路150を介して前記アンテナ面130に接続され、且つ、他方が前記誘電体120の下方に配置された前記グラウンド面110に接続されている。 Further, in the conventional example shown in FIG. 8, the transceiver device is connected to one of a pair of connection terminals via a matching circuit 150 provided on the dielectric 120 to the antenna surface 130 and, the other It is connected to the ground plane 110 which is disposed below the dielectric 120.
即ち、従来の構成においては、前記送受信素子は、前記誘電体120の厚みに相当する段差が生じた状態で、前記アンテナ面及び前記グラウンド面に接続されており、かかる接続作業が極めて困難であった。 That is, in the conventional configuration, the transceiver device in a state where the step corresponding to the thickness of the dielectric 120 is generated, is connected to the antenna plane and the ground plane, such connecting operation is very difficult It was.

本発明は、前記従来技術に鑑みなされたものであり、可及的な小型化を図り得るパッチアンテナ及びRFIDインレットの提供を、一の目的とする。 The present invention, wherein has been made in view of the prior art, to provide a patch antenna and an RFID inlet to obtain achieving as much as possible miniaturization, it is an object.
又、本発明は、送受信素子とパッチアンテナとの接続作業の簡略化を図り得るパッチアンテナ及びRFIDの提供を、他の目的とする。 Further, the present invention is to provide a patch antenna and an RFID obtain achieving simplification of work of connecting the reception device and the patch antenna, and other purposes.

本発明は、前記目的を達成するために、誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナであって、前記アンテナ面には、前記誘電体を露出させる開口が設けられており、前記開口は、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成されたパッチアンテナを提供する。 The present invention, in order to achieve the object, a patch antenna with a ground plane and the antenna plane dielectric interposed, to the antenna plane, an opening is provided to expose the dielectric , said openings, the area bounded by the dielectric exposed through the opening of the antenna surface is to provide an arrangement patch antenna to form a matching circuit for transmitting and receiving elements.

好ましくは、前記アンテナ面における前記領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接される。 Preferably, the region of the antenna surface, one end portion thereof close to the lower portion of the high-frequency voltage of the antenna surface.
前記開口が、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する態様においては、前記第2スリットを挟んだ一方側及び他方側が、前記送受信素子の一対の接続端子にそれぞれ接続される。 Said opening, a pair of first slits extending in parallel so as to face each other, in the embodiments having a second slit communicating said pair of first slits, one side and the other side sandwiching the second slit It is connected to a pair of connection terminals of the transmitting and receiving elements.

又、本発明は、誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナと、一対の接続端子を有する送受信素子とを備えたRFIDインレットであって、前記アンテナ面には、前記誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口が形成され、前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接されており、前記送受信素子は、前記一対の接続端子が前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続されているRFIDインレットを提供する。 Further, the present invention includes a patch antenna having a ground plane dielectric interposed and antenna plane, an RFID inlet having a receiving element having a pair of connecting terminals, to the antenna surface, the dielectric an opening for exposing the body, a pair of first slits extending in parallel so as to face each other, an opening and a second slit for communicating said pair of first slits are formed, said one of the antenna surface area bounded by the dielectric exposed in the opening, one end portion is close to the lower portion of the high-frequency voltage of the antenna surface, said transmission and reception device, the pair of connecting terminals to said second slit in sandwiched on one side and the other side to provide a RFID inlet which is connected to the antenna surface.

好ましくは、前記第2スリットが、前記高周波電圧の低い部位に近接される。 Preferably, the second slit is close to the lower portion of the high frequency voltage.
前記アンテナ面が、前記第1スリットと平行な長さ方向の距離がLで、且つ、前記第1スリットと直交する幅方向の距離がWの矩形とされた場合においては、例えば、前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置するように形成される。 The antenna surface, the distance of the first slit and parallel lengthwise direction at L, and, in the case where the distance in the width direction orthogonal to the first slit is a rectangular W, for example, the antenna surface the region in the one end, relates to a length direction, are formed so as to on the basis of the L / 2 located within ± L × 0.1.
これに代えて、前記アンテナ面が、前記第1スリットと平行な長さ方向の距離がLの円形又は楕円形とされる場合においては、例えば、前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置するように形成される。 Alternatively, the antenna surface, when the length of the first slit and parallel length direction is circular or oval L is, for example, the region in the antenna plane, one end portion, It relates lengthwise, are formed so as to on the basis of the L / 2 located within ± L × 0.1.

本発明に係るパッチアンテナによれば、アンテナ面に、誘電体を露出させる開口を設け、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成したので、整合回路がアンテナ面の外部に設けられていた従来構成に比して、可及的な小型化を図ることができる。 According to the patch antenna according to the present invention, formed on the antenna surface, an opening for exposing the dielectric, the area bounded by the dielectric exposed through the opening of the antenna surface is a matching circuit for transmitting and receiving elements and then, is, the matching circuit is compared with the conventional configuration has been provided outside the antenna surface, it is possible to as much as possible miniaturization.

又、本発明に係るRFIDインレットによれば、アンテナ面に、誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口を形成し、前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域を、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接させ、送受信素子の一対の接続端子を前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続させたので、整合回路がアンテナ面の外部に設けられていた従来構成に比して、可及的な小型化が図れると共に、前記送受信素子の一対の接続端子を同一平面内で接続させることができ、該送受信素子の接続作業を極めて効率化することができる。 Further, according to the RFID inlet according to the present invention, the antenna surface, an opening for exposing the dielectric, communicates with the pair of first slits extending in parallel to face each other, the pair of first slits second to form an opening having a slit, said region bounded by the dielectric exposed through the opening of the antenna plane, one end so it is close to the low frequency voltage portion of the antenna surface, transceiver since was connected at one side and the other side of the pair of connecting terminals across the second slit element to the antenna surface, as compared with the conventional configuration matching circuit is provided outside of the antenna surface, Kakyu with attained is specific compact, said pair of connection terminals of the transmitting and receiving elements can be connected in the same plane, it can be extremely efficient operation of connecting said transmission reception device.

以下に、本発明に係るパッチアンテナの好ましい実施の形態につき、添付図面を参照しつつ説明する。 Hereinafter, per the preferred embodiment of a patch antenna according to the present invention will be described with reference to the accompanying drawings.
図1は、本実施の形態に係るパッチアンテナ1の斜視図である。 Figure 1 is a perspective view of the patch antenna 1 according to this embodiment.
又、図2は、図1におけるII部拡大平面図である。 Also, FIG. 2 is an II enlarged plan view in FIG.

前記パッチアンテナ1は、電気的に接続されるICチップ等の送受信素子(図示せず)と共働して、外部に対して信号を送受信するRFIDインレットを形成する。 The patch antenna 1, in cooperation with emitting and receiving elements such as IC chips, which are electrically connected (not shown), to form the RFID inlet for transmitting and receiving signals to the outside.

詳しくは、前記パッチアンテナ1は、導体によって形成されるグラウンド面10と、該グラウンド面10上に載置された誘電体20と、該誘電体20を挟んで前記グラウンド面10に対して略平行に配置されたアンテナ面30とを備えている。 Specifically, the patch antenna 1 is approximately parallel to the ground plane 10 formed by a conductor, a dielectric 20 placed on the ground surface 10, relative to the ground surface 10 across the dielectric 20 and an antenna surface 30 arranged.

前記グラウンド面10は、例えば、前記誘電体20中の電磁波の波長をλとした場合に、1λ以上の矩形より大きな面積を有するAl又はCu等の導体(好ましくは金属)によって形成される。 The ground plane 10 is, for example, the when the wavelength of the electromagnetic wave in the dielectric 20 lambda, the conductor (preferably metal) such as Al or Cu has a larger area than the rectangle or 1λ formed by.
前記アンテナ面30は、例えば、前記誘電体20中の電磁波の波長をλとした場合に、0.5λ〜1.5λ×0.5λ〜1.5λの矩形状、若しくは、円形状又は楕円形状等の非矩形状に形成された厚さ0.001mm〜1mmのAL又はCu等の導体(好ましくは金属)によって形成される。 The antenna surface 30, for example, when the wavelength of the electromagnetic wave in the dielectric 20 and λ, 0.5λ~1.5λ × 0.5λ~1.5λ rectangular, or circular or elliptical shape AL or Cu or the like of the conductor thickness 0.001mm~1mm formed in non-rectangular shape of equal (preferably metal) is formed by.
又、前記誘電体20は、例えば、厚さ0.1mm〜3mmのFR−4(比誘電率εr=4.2〜4.8)等の絶縁物によって形成される。 Further, the dielectric 20 is formed by, for example, FR-4 (specific dielectric constant .epsilon.r = 4.2 to 4.8) insulating material such as thick 0.1 mm to 3 mm.

本実施の形態においては、図2に示すように、前記アンテナ面30には、前記誘電体20の一部を露出させる開口31が形成されている。 In the present embodiment, as shown in FIG. 2, the antenna surface 30, an opening 31 that exposes a portion of the dielectric 20 is formed.
該開口31は、前記アンテナ面30のうち該開口31を介して露出する誘電体20によって画される領域(以下、整合領域35という)が、前記送受信素子に対する整合回路を形成するように構成されている。 Opening 31, the area bounded by the dielectric 20 exposed through the opening 31 of the antenna surface 30 (hereinafter, referred to as matching region 35) is configured to form a matching circuit for the transmitting and receiving elements ing.
詳しくは、図2に示すように、前記開口は、互いに対向するように平行に延びる一対の第1スリット31aと、該一対のスリット31aを連通する第2スリット31bとを有している。 Specifically, as shown in FIG. 2, the aperture has a pair of first slits 31a extending in parallel so as to face each other, and a second slit 31b communicating the pair of slits 31a.

前記開口31は、前記整合領域35の一端部が前記アンテナ面30のうち高周波電圧の低い部位(以下、低電圧部位という)に近接するように形成され、これにより、該整合領域35が前記整合回路を構成するようになっている。 The opening 31, the alignment region 35 of the one end the lower portion of the high-frequency voltage of the antenna surface 30 (hereinafter, referred to as low-voltage region) is formed so as to approach the, thereby, the matching 該整 apply region 35 so as to constitute a circuit.
前記低電圧部位は、例えば、前記アンテナ面30における高周波電圧の最大値をVmaxとし、且つ、最小値Vminとした場合に、電圧Vが、 The low voltage region, for example, the maximum value of the high frequency voltage in the antenna surface 30 and Vmax, and, when the minimum value Vmin, the voltage V,
Vmin≦V≦Vmin+(Vmax−Vmin)×α(但し、0<α<1) Vmin ≦ V ≦ Vmin + (Vmax-Vmin) × α (where, 0 <α <1)
の条件を満たす部位と定義することができる。 It can be the site of satisfying the definition.
前記αはRFIDインレットに求められる性能に応じて決定されるが、0.2、より好ましくは、0.1とされる。 The α but is determined according to the performance required for the RFID inlets, 0.2, and more preferably, is 0.1.

これに代えて、本実施の形態におけるように、前記アンテナ面30が、前記第1スリット31aと平行な長さ方向Lに沿って延びる長さaの辺a1,a2と、前記第1スリット31aに直交する幅方向Wに沿って延びる長さbの辺b1,b2とを有する矩形状とされている場合には、前記低電圧部位は、長さ方向Lに関する中心線C(辺b1からa/2だけ離間され、且つ、該辺b1に平行な仮想線)を基準にして、長さaの±20%、より好ましくは、±10%の領域と、擬制することができる。 Alternatively, as in the present embodiment, the antenna surface 30, the side a1, a2 of length a and extending along the first slit 31a and parallel to the length direction L, the first slit 31a a if it is a rectangular shape having a side b1, b2 of length b and extending along the width direction W orthogonal to the low-voltage region from the center line C (side b1 of the length direction L in / only 2 spaced, and, based on the virtual line) parallel to 該辺 b1, ± 20% of the length a, more preferably, may be 10% of the area ±, are fictitious.
即ち、辺b1からの長手方向の距離Pが、 That is, the longitudinal distance P from the sides b1,
(a/2)−a×0.2≦P≦(a/2)+a×0.2 (A / 2) -a × 0.2 ≦ P ≦ (a / 2) + a × 0.2
より好ましくは、 More preferably,
(a/2)−a×0.1≦P≦(a/2)+a×0.1 (A / 2) -a × 0.1 ≦ P ≦ (a / 2) + a × 0.1
によって画される領域を、前記低電圧部位と擬制することができる。 A region bounded by said can be constructive and low voltage portions.

図示の形態においては、前記第2スリット31bは、前記一対の第1スリット31aの一端部に配置されている。 In the illustrated embodiment, the second slit 31b is disposed at one end of the pair of first slits 31a.
斯かる形態においては、前記一対の第1スリット31aの他端部と前記第2スリット31bとの間において、該一対の第1スリット31aに挟まれる領域が前記整合領域35を構成している。 In such form, between the other end portion and the second slit 31b of the pair of first slits 31a, a region between the said pair of first slits 31a constitute the matching region 35.

なお、本実施の形態においては、前述の通り、前記アンテナ面30を矩形状としたが、当然ながら、該アンテナ面30は斯かる形態に限定されるものではない。 Incidentally, in the present embodiment, as described above, although the antenna surface 30 and a rectangular shape, of course, the antenna surface 30 is not limited to this aspect.
例えば、該アンテナ面30を円形状又は楕円形状とすることも可能である。 For example, it is also possible to the antenna surface 30 and circular or elliptical shape.
斯かる場合には、第1スリット31aと平行な長さ方向に関する中心線(円形又は楕円形の中心を通り、且つ、第1スリット31aと直交する直線)を基準にして、長さ方向の距離aの±20%(より好ましくは、±10%)の範囲内を、前記低電圧部位と擬制することができる。 In such a case, (as a circular or at the center of the ellipse, and a straight line perpendicular to the first slit 31a) center line for the first slit 31a and parallel to the length direction as a reference, the longitudinal direction length ± 20% of a (more preferably, ± 10%) within the range of, the can be constructive and low voltage portions.

前記送受信素子は、前記整合回路を介して前記アンテナ面30に接続される。 The transceiver device is connected via the matching circuit to the antenna surface 30.
具体的には、前記送受信素子は、一対の接続端子が、前記第2スリット31bを挟んで一方側及び他方側にそれぞれ位置する第1給電点41及び第2給電点42(図2参照)において、前記アンテナ面30に接続されている。 Specifically, the transceiver device is provided with a pair of connection terminals, in the second first feeding point 41 and the second feeding point 42 located respectively on one side and the other side across the slit 31b (see FIG. 2) It is connected to the antenna surface 30.

このように本実施の形態に係るパッチアンテナ1においては、前記アンテナ面30に前記誘電体20を露出させる開口31を設け、該開口によって露出する誘電体20によって画される前記整合領域35を、送受信素子に対する整合回路として用いており、従って、整合回路がアンテナ面の外部に設けられた従来構成(図8参照)に比して、可及的な小型化を図ることができる。 Thus, in the patch antenna 1 according to this embodiment, the opening 31 exposing the dielectric 20 to the antenna surface 30 is provided, the alignment region 35 bounded by a dielectric 20 exposed by the opening, is used as a matching circuit for transmitting and receiving elements, therefore, can be the matching circuit is compared with the conventionally configured provided outside of the antenna plane (see FIG. 8), achieving as much as possible miniaturization.

又、本実施の形態においては、前述の通り、前記第2スリット31bを挟んで一方側及び他方側にそれぞれ位置する第1及び第2給電点41,42において、前記送受信素子の一対の接続端子を前記アンテナ面30に接続可能としており、該送受信素子の一対の接続端子が同一平面内において接続されるようになっている。 Further, in the present embodiment, as described above, in the first and second feed points 41, 42 respectively positioned on the one side and the other side across the second slit 31b, a pair of connection terminals of the transmitting and receiving elements the has been connectable to the antenna surface 30, a pair of connecting terminals of said transmission reception device is adapted to be connected in the same plane.
従って、一対の接続端子が、それぞれ、誘電体の厚みに相当する距離だけ上下に離間されたグラウンド面及びアンテナ面に接続される従来構成(図8参照)に比して、送受信素子の接続作業を極めて簡略化及び効率化することができる。 Accordingly, the pair of connection terminals, respectively, compared with the conventional configuration to be connected to only a ground plane spaced vertically and the antenna plane distance corresponding to the thickness of the dielectric (see FIG. 8), connection work of the transmitting and receiving elements it can be greatly simplified and more efficient.

さらに、本実施の形態においては、図2に示すように、前記第2スリット31bが、前記低電圧部位に近接するように、前記開口31を形成している。 Further, in the present embodiment, as shown in FIG. 2, the second slit 31b is, the so close to the low voltage region to form the opening 31.
斯かる構成によれば、前記第1給電点41が前記低電圧部位に位置することになり、該第1給電点41に接続される前記送受信素子における一方の接続端子が、グラウンド電圧に近い状態とされる。 According to such a configuration, will be the first feeding point 41 is positioned at the low voltage region, one connection terminal of the transceiver device which is connected to the first feeding point 41 is closer to the ground voltage state It is.
従って、本実施の形態に係るパッチアンテナ1の性能を、従来のパッチアンテナが持つ性能と同等とすることができる。 Therefore, the performance of the patch antenna 1 according to this embodiment can be the equivalent to the performance of traditional patch antenna.

なお、本実施の形態においては、前述の通り、前記第2スリット31bが前記低電圧部位に近接するように、該第2スリット31bをアンテナ面30の長手方向中心線Cの近傍に位置させたが(図2参照)、これに代えて、前記第2スリット31bを前記第一対の第1スリットの他端部(アンテナ面30の長手方向中心線Cから離間された側の端部)に位置させたり(図3参照)、前記第2スリット31bを前記一対の第1スリット31aの中間部に位置させることも可能である(図4参照)。 Incidentally, in the present embodiment, as described above, so that the second slit 31b is close to the low voltage portion and positions the second slit 31b in the vicinity of the longitudinal center line C of the antenna surface 30 to but (see Figure 2), instead of this, the second other end portion of the first slit of the slit 31b the first pair (end on the side spaced from the longitudinal centerline C of the antenna surface 30) or is located (see FIG. 3), it is also possible to position the second slit 31b in the middle portion of the pair of first slits 31a (see FIG. 4).

図3に示す形態においては、前記一対の第1スリット31aの一端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域が、前記整合回路として作用する前記整合領域35となる。 In the embodiment shown in FIG. 3, between the end portions of the pair of first slits 31a and the second slit 31b, a region sandwiched by the pair of first slits 31a are the alignment acting as the matching circuit a region 35.
又、図4に示す形態においては、前記一対の第1スリット31aの他端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域36と、前記一対の第1スリット31aの一端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域37とが、前記整合回路として作用する前記整合領域35となる。 Further, in the embodiment shown in Figure 4, between the other end portion and the second slit 31b of the pair of first slits 31a, an area 36 sandwiched by the pair of first slits 31a, the pair first in between the end portion and the second slit 31b of the first slit 31a, a region 37 sandwiched by the pair of first slits 31a becomes and the matching region 35 which acts as the matching circuit.
なお、図3及び図4に示す何れの形態においても、前記第1及び第2給電点41,42は、前記第2スリット31bを挟んで両側に配置される。 In any embodiment shown in FIGS. 3 and 4, the first and second feed points 41, 42 are arranged on both sides of the second slit 31b.

ここで、本実施の形態に係るパッチアンテナ1の一実施例に関して電磁界シミュレータを用いて行った解析結果について説明する。 Here, the analysis result will be described was carried out using an electromagnetic field simulator with respect to one embodiment of the patch antenna 1 according to this embodiment.
図5に、本解析に用いたアンテナ面30の平面寸法を示す。 Figure 5 shows the planar dimensions of the antenna surface 30 used in this analysis.
該アンテナ面30は、ALによって形成されるものとし、長手方向Lに沿った辺a1及び辺a2の長さa及び幅方向Wに沿った辺b1及び辺b2の長さbは共に26.4mmとした。 The antenna surface 30, and those formed by AL, the length b of the side b1 and edges b2 along the length a and the width direction W of the side a1 and edges a2 along the longitudinal direction L are both 26.4mm and the.
又、前記一対の第1スリット31aは長さmが7.2mmで、該一対の第1スリット31aの間隔は、それぞれの外側のエッジ間の間隔dを4mmとした。 Further, in the pair of first slits 31a length m is 7.2 mm, spacing of the pair of first slits 31a have a spacing d between the respective outer edges and 4 mm.
そして、前記第2スリット31bの幅を0.4mmとすると共に、該第2スリット31bをアンテナ面30の長手方向中心線Cに整列させた。 Then, while a 0.4mm width of the second slit 31b, aligning the second slit 31b in the longitudinal center line C of the antenna surface 30.

前記誘電体20の材質はFR−4(比誘電率εr=4.7)で、送受信素子50のインピーダンスは9.5−j56(Ω)とし、上部が自由空間とされた金属ボックス内に、前記アンテナ面30及び前記送受信素子50を配置させた。 The material of the dielectric 20 in the FR-4 (specific dielectric constant .epsilon.r = 4.7), the impedance of the transmitting and receiving device 50 is a 9.5-j56 (Ω), at the top in a metal box, which is a free space, the antenna It was arranged surface 30 and the transceiver device 50.

図6に、前記アンテナ面における電流密度分布を示す。 Figure 6 shows a current density distribution in the antenna plane.
前記アンテナ面30の長手方向Lに沿って、辺b1から辺b2へ向かって電流の波が生じており、長手方向Lに関する中心線C近傍で電流が最大(即ち、高周波電圧が最小)となっている。 Along the longitudinal direction L of the antenna surface 30, and a wave of current is generated toward the sides b1 to edge b2, current center line C vicinity in the longitudinal direction L becomes the maximum (i.e., the high-frequency voltage is minimum) ing.
斯かる中心線C近傍が前記低電位部位である。 Wherein the center line C vicinity such a low potential region.
なお、辺b1及び辺b2において、高周波電圧が最大となるが、その極性は逆である。 Note that, in the sides b1 and edges b2, although the high-frequency voltage is maximum, its polarity is reversed.

又、図7に、本解析に用いたアンテナ面30及び送受信素子50の放射特性を示す。 In addition, FIG. 7 shows the radiation characteristics of the antenna surface 30 and the transceiver device 50 used in this analysis.
図7は、far field と呼ばれるもので、前記アンテナ面30及び送受信素子50によって構成されるRFIDインレットから、上方へ離間された場所における電界強度を角度別にプロットしたものである。 Figure 7 is called a _far field, the RFID inlets constituted by the antenna surface 30 and the transceiver device 50 is a plot of electric field strength at the location spaced upward by an angle.
図7中のプロット○は、辺a1及び辺a2に接離する方向に沿った角度別の値であり、プロット□は、辺b1及び辺b2に接離する方向に沿った角度別の値である。 Plot ○ is in Figure 7, is an angle different values ​​along the direction toward or away from the side a1 and edges a2, plot □ at an angle different values ​​along the direction toward and away from the sides b1 and edges b2 is there.

図7から明らかなように、本実施の形態に係るパッチアンテナ1は、ほぼ3〜6dBiの利得があり、良好な放射特性が得られることが確認できる。 As apparent from FIG. 7, the patch antenna 1 according to this embodiment, there is a gain of approximately 3~6DBi, it can be confirmed that good radiation characteristics can be obtained.
グラウンド面に対して垂直方向に特に良好な利得が得られると共に、かなり低い打ち上げ角においても十分な利得が得られている。 With resulting particularly good gain in a direction perpendicular to the ground surface, and sufficient gain can be obtained even in fairly low launch angle.

図1は、本発明の一実施の形態に係るパッチアンテナの斜視図である。 Figure 1 is a perspective view of a patch antenna according to an embodiment of the present invention. 図2は、図1におけるII部拡大平面図である。 Figure 2 is an II enlarged plan view in FIG. 図3は、本発明の他の形態に係るパッチアンテナの部分拡大平面図であり、図2に相当する部位を示している。 Figure 3 is an enlarged fragmentary plan view of a patch antenna according to another embodiment of the present invention shows a portion corresponding to FIG. 図4は、本発明のさらに他の形態に係るパッチアンテナの部分拡大平面図であり、図2に相当する部位を示している。 Figure 4 is a partial enlarged plan view of a patch antenna according to another embodiment of the present invention shows a portion corresponding to FIG. 図5は、本発明の一実施例に係るパッチアンテナの平面図である。 Figure 5 is a plan view of a patch antenna according to an embodiment of the present invention. 図6は、図5に示すパッチアンテナにおけるアンテナ面の電流密度分布を示している。 Figure 6 shows a current density distribution of the antenna surface in a patch antenna shown in FIG. 図7は、図5に示すパッチアンテナの放射特性を示すグラフである。 Figure 7 is a graph showing the radiation characteristic of the patch antenna shown in FIG. 図8は、従来のパッチアンテナを示す斜視図である。 Figure 8 is a perspective view of a conventional patch antenna.

符号の説明 DESCRIPTION OF SYMBOLS

1 パッチアンテナ10 グラウンド面20 誘電体30 アンテナ面31 開口31a 一対の第1スリット31b 第2スリット41,42 給電点(送受信素子とパッチアンテナとの接続点) 1 patch antenna 10 ground plane 20 dielectric 30 antenna surface 31 opening 31a a pair of first slits 31b second slits 41 and 42 feed point (connection point between the transmitting and receiving elements and the patch antenna)

Claims (7)

  1. 誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナであって、 Ground plane dielectric interposed and a patch antenna having an antenna surface,
    前記アンテナ面には、前記誘電体を露出させる開口が設けられており、 Wherein the antenna surface, an opening is provided to expose the dielectric,
    前記開口は、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成されていることを特徴とするパッチアンテナ。 The opening, a patch antenna, wherein the area bounded by the dielectric exposed through the opening of the antenna surface is configured to form a matching circuit for transmitting and receiving elements.
  2. 前記アンテナ面における前記領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接されていることを特徴とする請求項1に記載のパッチアンテナ。 The region in the antenna plane, a patch antenna according to claim 1, characterized in that one end is close to the lower portion of the high-frequency voltage of the antenna surface.
  3. 前記開口は、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有しており、 It said opening has a pair of first slits extending in parallel so as to face each other, and a second slit for communicating said pair of first slits,
    前記第2スリットを挟んだ一方側及び他方側が、前記送受信素子の一対の接続端子にそれぞれ接続されることを特徴とする請求項1又は2に記載のパッチアンテナ。 The second one side and the other side across the slit, the patch antenna according to claim 1 or 2, characterized in that it is connected to the pair of connection terminals of the transmitting and receiving elements.
  4. 誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナと、一対の接続端子を有する送受信素子とを備えたRFIDインレットであって、 And the patch antenna having a ground plane dielectric interposed and antenna plane, an RFID inlet having a receiving element having a pair of connection terminals,
    前記アンテナ面には、前記誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口が形成され、 To the antenna surface, an opening for exposing the dielectric, and a pair of first slits extending in parallel so as to face each other, an opening and a second slit for communicating said pair of first slits formed It is,
    前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接されており、 Area bounded by the dielectric exposed through the opening of the antenna surface is close to the lower portion of the high-frequency voltage of one end the antenna surface,
    前記送受信素子は、前記一対の接続端子が前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続されていることを特徴とするRFIDインレット。 The transceiver device, RFID inlets, wherein the pair of connecting terminals is connected to the antenna surface in sandwiched on one side and the other side of the second slit.
  5. 前記第2スリットが、前記高周波電圧の低い部位に近接されていることを特徴とする請求項4に記載のRFIDインレット。 The RFID inlet according to claim 4 in which the second slit, characterized in that it is close to the lower portion of the high frequency voltage.
  6. 前記アンテナ面は、前記第1スリットと平行な長さ方向の距離がLで、且つ、前記第1スリットと直交する幅方向の距離がWの矩形とされており、 The antenna surface, length of the first slit and parallel lengthwise direction at L, and the distance in the width direction orthogonal to the first slit are a rectangular W,
    前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置することを特徴とする請求項4又は5に記載のRFIDインレット。 The region in the antenna plane, one end relates length direction, RFID according to claim 4 or 5, characterized in that located within ± L × 0.1 based on the L / 2 inlet.
  7. 前記アンテナ面は、前記第1スリットと平行な長さ方向の距離がLの円形又は楕円形とされており、 The antenna surface, length of the first slit and parallel length direction is circular or oval L,
    前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置することを特徴とする請求項4又は5に記載のRFIDインレット。 The region in the antenna plane, one end relates length direction, RFID according to claim 4 or 5, characterized in that located within ± L × 0.1 based on the L / 2 inlet.
JP2005045088A 2005-02-22 2005-02-22 Patch antenna and rfid inlet Pending JP2006237674A (en)

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