JP2006235995A - Signal processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a signal processing device which can generate random numbers whose randomness is further higher although it is a simple composition. <P>SOLUTION: This device can generate random numbers whose randomness is further higher by generating pseudo-random number assuming uncertain counter value as seed, while the uncertain counter value being able to be obtained reflecting fluctuation of processing time of serial bus 22 to this counter value by obtaining counter value of free run counter 20c after performing empty reading to a nonvolatile memory 21 through a serial bus 22. Moreover, since it is required only to mount a bus mounted to many general data processing circuits and a counter whose count cycle is shorter than fluctuation of processing time of the bus, the composition of this device can be simplified compared with the case that RTC (Real Time Clock) is mounted separately. In this way, this device can generate random numbers whose randomness is further higher although it has a simple composition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a signal processing apparatus, and is particularly suitable for application to a signal processing apparatus that generates pseudo-random numbers.

  In recent years, various content distribution services via networks such as the Internet have become widespread. In such a content distribution service, content data (hereinafter also referred to as content data) itself is provided from a predetermined server to a user terminal via a network, not via a medium such as a CD or a DVD. Therefore, there is a strong demand for preventing unauthorized use of content, and various security measures have been taken.

  As such security measures, for example, by using encryption using pseudo-random numbers for user authentication processing and data transmission / reception processing between the server and the terminal, it is possible to prevent these processing from being analyzed and falsified from the outside. Thus, a method for preventing unauthorized use of content is widely known.

By the way, when using pseudo-random numbers in this way, it is important in terms of security how difficult to predict and to generate pseudo-random numbers with high randomness. Therefore, conventionally, for example, the current time obtained from an RTC (real time clock) is set as a pseudorandom number random seed (hereinafter also referred to as seed), and pseudorandom numbers are generated from the seeds. Some are designed to improve randomness (see, for example, Patent Document 1).
JP 2002-344444 A (paragraph number [0053])

  However, when the RTC is used in this way, it is necessary to separately mount the RTC in a device for generating a pseudo random number (for example, a user terminal), and this RTC is difficult to integrate with other circuits. There is a problem that it becomes complicated and the cost of the terminal increases as a result.

  The present invention has been made in consideration of the above points, and proposes a signal processing apparatus that can generate a random number having a higher randomness with a simple configuration.

  In order to solve such a problem, in the signal processing device of the present invention, a signal processing unit and a memory connected to the signal processing unit via a bus are provided, and the signal processing unit counts more than the fluctuation of the bus processing time. It has a counter with a short cycle, a random number generator that generates random numbers from random number seeds, and a controller that controls the operation of the random number generator in response to an external request, and the counter counts with the activation of the signal processor The control unit transfers the random number request information to the random number generation unit according to the random number request information requesting a random number from the outside, and the random number generation unit uses the bus according to the random number request information. The counter value of the counter is acquired after transmitting and receiving data to and from the memory, and a random number is generated from the random number seed corresponding to the acquired counter value.

  In this way, in this data processing circuit, the counter value of the counter is acquired after transmitting and receiving data to and from the memory via the bus, thereby reflecting the fluctuation in the processing time of the bus in the counter value and generating an indefinite counter value. A random number having higher randomness can be generated by generating a random number from a random number seed corresponding to the indefinite counter value.

  Further, in this data processing circuit, it is only necessary to mount a bus mounted in many general signal processing circuits and a counter having a shorter count cycle than fluctuations in processing time of the bus. As compared with the above, the configuration can be simplified.

  According to the present invention, it is possible to obtain an indefinite counter value by reflecting the fluctuation of the processing time of the bus in the counter value by acquiring the counter value after transmitting / receiving data to / from the memory via the bus. And by generating a random number from a random number seed corresponding to this indefinite counter value, a random number with higher randomness can be generated, and a bus implemented in many general signal processing circuits, Since it is only necessary to mount a counter having a shorter count cycle than the fluctuation in bus processing time, the configuration can be simplified as compared with the case of separately mounting an RTC, and thus the configuration is simple. Thus, it is possible to realize a signal processing apparatus that can generate a random number with higher randomness.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment (1-1) Configuration of Content Playback Device In FIG. 1, reference numeral 1 denotes a content playback device capable of playing back music content distributed via the network NT as a whole. When the operation input unit 2 including various operation buttons provided on the housing surface of the apparatus 1 or a remote controller (not shown) is operated by the user, the operation input unit 2 recognizes this and responds to this operation. The operation input signal is sent to the input processing unit 3. The input processing unit 3 performs predetermined processing on the supplied operation input signal to convert the operation input signal into an operation command, and sends the operation command to a host CPU (Central Processing Unit) 5 via the bus 4. To do.

  The host CPU 5 reads various programs such as basic programs and application programs stored in advance in a ROM (Read Only Memory) 6 or a hard disk drive 7 into a RAM (Random Access Memory) 8 via the bus 4. The host CPU 5 develops these various programs on the RAM 7 and controls the whole in accordance with the developed various programs, and also performs predetermined arithmetic processing and processing (for example, content acquisition) according to an operation command given from the input processing unit 3. Processing, content reproduction processing, etc.).

  In practice, for example, when the user performs an operation for acquiring music content via the operation input unit 2, the host CPU 5 responds to the request on the network NT via the communication processing unit 9 and the network interface 10 sequentially. A content distribution server (not shown) is accessed, and a request signal for requesting distribution of music content is transmitted to the content distribution server.

  The content distribution server stores content data subjected to predetermined encryption (hereinafter also referred to as encrypted content data), and when accessed from the content playback device 1, The encryption corresponding to the requested music content is performed in response to the request signal sent from the content reproduction apparatus 1 only when the predetermined user authentication process is performed and it is confirmed that the content reproduction apparatus 1 is an authorized user. The encrypted content data is transmitted to the content reproduction apparatus 1 via the network NT. At this time, if the requested music content is charged, for example, the content distribution server executes a charging process for charging the user of the content reproduction apparatus 1 for the fee associated with the distribution of the music content.

  The host CPU 5 of the content reproduction apparatus 1 takes in the encrypted content data distributed from the content distribution server via the network interface 10 and the communication processing unit 9 in order, and records them in the hard disk drive 7.

  When the user performs a reproduction operation on the encrypted content data in the hard disk drive 7 via the operation input unit 2, the host CPU 5 reads the specified encrypted content data from the hard disk drive 7 in response to this. This encrypted content data is sent to the data processing circuit 11. The data processing circuit 11 decrypts the encrypted content data to return it to the content data, and sends it to the audio processing unit 12. The sound processing unit 12 performs sound processing such as digital-analog conversion processing and equalizing processing on the content data given from the data processing circuit 11, and sends out the sound signal obtained as a result to the speaker SP. Outputs audio based on the audio signal.

  Further, the data processing circuit 11 of the present embodiment has a pseudo random number generator (details will be described later) inside, and is also adapted to generate pseudo random numbers in response to a command from the host CPU 5. Yes. This pseudo-random number is used when the host CPU 5 performs user authentication processing and various data transmission / reception processing between the content reproduction apparatus 1 and the content distribution server, and also includes decryption processing and other processing performed in the data processing circuit 11. Etc.

  As described above, in the content reproduction apparatus 1, the data processing circuit 11 generates a pseudo random number and uses the pseudo random number in various processes, for example, in a user authentication process or a process in the data processing circuit 11. By encrypting the data to be handled with this pseudo-random number, it is possible to prevent these processes and the data handled in these processes from being easily analyzed and falsified from the outside, and to prevent unauthorized use of music contents. Has been made.

  Here, how the pseudo random numbers are actually generated in the data processing circuit 11 will be described together with the internal configuration of the data processing circuit 11.

(1-2) Internal Configuration of Data Processing Circuit and Pseudorandom Number Generation Procedure First, the internal configuration of the data processing circuit 11 will be described with reference to FIG. As shown in FIG. 2, the data processing circuit 11 is formed as a circuit board on which an IC (Integrated Circuit) chip constituting a DSP (Digital Signal Processor) 20 and an IC chip constituting a nonvolatile memory 21 are mounted. ing. The DSP 20 and the nonvolatile memory 21 are serially connected by a serial bus 22 on the circuit board. In the nonvolatile memory 21, for example, various data handled on the DSP 20 are recorded.

  The DSP 20 is a general-purpose processor that can execute various processes (such as the above-described decryption process and pseudo-random number generation process) in software according to firmware written in its own internal memory (not shown). Now, the case where the DSP 20 operates in accordance with the pseudo random number generation firmware will be described. For convenience of explanation, software functions for generating the pseudo random numbers are represented by function blocks (instruction processing unit 20a, pseudo random number generator). 20b, free run counter 20c).

  In the DSP 20, the instruction processing unit 20 a controls the whole (pseudo random number generator 20 b and free run counter 20 c) in accordance with various instructions from the host CPU 5. First, the instruction processing unit 20a is activated in response to an activation instruction from the host CPU 5 (that is, the DSP 20 is activated), and at this time, activates the free-run counter 20c and causes the free-run counter 20c to start counting.

  Thereafter, upon receiving a random number request command for requesting a random number from the host CPU 5, the command processing unit 20a transfers the random number request command to the pseudo-random number generator 20b. When the pseudo random number generator 20b receives a random number request command from the command processing unit 20a, the pseudo random number generator 20b first reads predetermined data from a predetermined address of the nonvolatile memory 21 via the serial bus 22. The pseudo-random number generator 20b acquires the counter value from the activated free-run counter 20c when the reading of the predetermined data is completed.

  At this time, the time required for reading the predetermined data is indefinite because it changes due to fluctuations in the processing time of the serial bus 22, and therefore the time from the start of the DSP 20 until the reading of the predetermined data is also indefinite.

  Here, in the data processing circuit 11 of this embodiment, in order to reflect the fluctuation of the processing time of the serial bus 22 in the counter value of the free-run counter 20c, the free-run counter 20c having a shorter counter cycle than this fluctuation. Was used. As a result, the counter value counted by the free-run counter 20c from when the DSP 20 is activated until the reading of the predetermined data is completed also becomes indefinite due to fluctuations in the processing time of the serial bus 22.

  The pseudo-random number generator 20b that has acquired the counter value in this way stores the counter value as seed in its own holding area 30, and then generates a pseudo-random number from the seed and sends it to the instruction processing unit 20a. . At this time, the pseudo random number generator 20b updates the seed stored in the seed holding area 30 with the generated pseudo random number. That is, the pseudo random number generator 20b updates seed with the generated pseudo random number every time it generates a pseudo random number.

  The instruction processing unit 20 a that has received the pseudo random number from the pseudo random number generator 20 b sends the pseudo random number to the host CPU 5.

  As described above, when a random number is requested, the pseudo random number generator 20 b first reads predetermined data from a predetermined address of the nonvolatile memory 21 via the serial bus 22. The reading of the predetermined data in this case is a process for making the counter value of the free-run counter 20c indefinite using the fluctuation of the processing time of the serial bus 22, and this is also referred to as idle reading hereinafter. After the non-volatile memory 21 is read idle in this way, the pseudo random number generator 20b acquires the counter value of the free-run counter 20c that becomes indefinite due to the idle reading, and generates the pseudo random number using the indefinite counter value as seed. To do. By doing so, the pseudo-random number generator 20b can generate a pseudo-random number with higher randomness based on an indefinite seed.

  Here, the pseudo-random number generation procedure (hereinafter also referred to as pseudo-random number generation procedure) by the data processing circuit 11 will be described in more detail with reference to the sequence chart of FIG. This sequence chart shows a pseudo-random number generation processing procedure by the host CPU 5, the DSP 20 (the instruction processing unit 20 a, the pseudo-random number generator 20 b and the free-run counter 20 c) constituting the data processing circuit 11 and the nonvolatile memory 21. At this time, the host CPU 5 operates in accordance with a program recorded in the ROM 6, and the DSP 20 operates in accordance with firmware written in an internal memory (not shown).

  The host CPU 5 transmits a DSP activation command for activating the DSP 20 to the instruction processing unit 20a of the DSP 20 in step SP1, for example, when the power is turned on or in response to a manual operation via the operation input unit 2.

  In step SP2, the instruction processing unit 20a is activated in response to a DSP activation instruction from the host CPU 5 (that is, the DSP 20 is activated). At this time, a free counter counter 20c is used to start counting. Transmit to the run counter 20c. In step SP3, the free-run counter 20c starts counting in response to being started according to a counter starting instruction from the instruction processing unit 20a.

  After that, for example, when the pseudo-random number is necessary to execute a specific process using the pseudo-random number (such as a user authentication process or various data transmission / reception process), the host CPU 5 sends a random number request command to the command processing unit in step SP4. To 20a. When receiving the random number request command from the host CPU 5, the command processing unit 20a transfers the random number request command to the pseudo random number generator 20b in step SP5.

  When the pseudo-random number generator 20b receives the random number request command from the command processing unit 20a, in step SP6, the pseudo-random number generator 20b reads a data read command for reading predetermined data from a predetermined address of the nonvolatile memory 21 (that is, for empty reading). The data is transmitted to the nonvolatile memory 21 via the bus 22. When the nonvolatile memory 21 receives the data read command from the pseudo random number generator 20b, in step SP7, in response to the data read command, the non-volatile memory 21 transfers the predetermined data recorded at a predetermined address via the serial bus 22. It transmits to the generator 20b. That is, the pseudo random number generator 20 b reads predetermined data from the nonvolatile memory 21 via the serial bus 22.

  Here, the time required for the processing of step SP6 and step SP7 becomes indefinite due to fluctuations in the processing time of the serial bus 22 as described above.

  When the reading of the predetermined data is completed, the pseudo random number generator 20b proceeds to step SP8 (FIG. 4), and in this step SP8, transmits a counter value request command for requesting a counter value to the free-run counter 20c. To do. When the free-run counter 20c receives the counter value request command from the pseudo random number generator 20b, the free run counter 20c acquires the counter value at this point in response to the counter value request command in step SP9, and uses the counter value as the pseudo random number generator. To 20b.

  The counter value obtained here indicates the time required for the processing of steps SP3-SP4-SP5-SP6-SP7-SP8-SP9. Since the time required for the processing of step SP6 and step SP7, which is a part of the processing from step SP3 to step SP9, is indefinite, the counter value indicating the entire processing time is also indefinite.

  When the pseudo random number generator 20b receives the counter value from the free-run counter 20c, in step SP10, the pseudo random number generator 20b initializes seed in the seed holding area 30 with the counter value, and proceeds to the next step SP11. That is, the counter value obtained from the free-run counter 20c is used as the initial value of seed. At this time, since the counter value is indefinite, the initial value of seed is also indefinite. As a result, the pseudorandom number generator 20b can obtain a different seed every time the DSP 20 is activated.

  In step SP11, the pseudo random number generator 20b generates a pseudo random number from the seed stored in the seed holding area 30, and proceeds to the next step SP12. In step SP12, the pseudo random number generator 20b updates the seed in the seed holding area 30 with the pseudo random number generated in step SP11, and proceeds to the next step SP13. In step SP13, the pseudo random number generator 20b outputs the generated pseudo random number to the instruction processing unit 20a.

  Upon receiving the pseudo random number output from the pseudo random number generator 20b, the instruction processing unit 20a returns this pseudo random number to the host CPU 5 in step SP14 (FIG. 5).

  In this way, the data processing circuit 11 can obtain an indefinite seed by using fluctuations in the processing time of the serial bus 22, and generates a pseudo-random number with higher randomness based on the indefinite seed. be able to.

  Thereafter, when a pseudo random number is required to execute a specific process using the pseudo random number again, the host CPU 5 transmits a random number request command to the command processing unit 20a again in step SP15. Upon receiving the random number request command from the host CPU 5, the command processing unit 20a transfers this random number request command to the pseudo random number generator 20b in step SP16.

  When receiving the random number request command from the command processing unit 20a, the pseudo random number generator 20b generates a pseudo random number from the seed stored in the seed holding area 30 in step SP17, and proceeds to the next step SP18. In step SP18, the pseudo random number generator 20b updates the seed in the seed holding area 30 with the pseudo random number generated in step SP17, and proceeds to the next step SP19. In step SP19, the pseudo random number generator 20b outputs the generated pseudo random number to the instruction processing unit 20a.

  Upon receiving the pseudo random number output from the pseudo random number generator 20b, the instruction processing unit 20a returns this pseudo random number to the host CPU 5 in step SP20.

  As described above, the data processing circuit 11 generates a pseudo random number with the counter value obtained from the free-run counter 20c as seed only when generating the first pseudo random number after starting the DSP 20, and when generating the second or subsequent pseudo random number, A pseudo random number is generated by using the previously generated pseudo random number as seed.

(1-3) Operation and Effect In the configuration described above, the data processing circuit 11 activates the DSP 20 in response to a DSP activation instruction from the host CPU 5, and activates the free-run counter 20c by the instruction processing unit 20a of the DSP 20 at this time. To start counting.

  Thereafter, upon receiving a random number request command from the host CPU 5, the command processing unit 20a of the data processing circuit 11 transfers the random number request command to the pseudo random number generator 20b. When the pseudo-random number generator 20b receives a random number request command from the command processing unit 20a, the pseudo-random number generator 20b performs idle reading to the nonvolatile memory 21 via the serial bus 22, and when this idle reading is completed, A counter value is acquired from the run counter 20c.

  The counter value acquired here is indefinite due to fluctuations in the processing time of the serial bus 22 at the time of idle reading. In practice, the fluctuation of the processing time of the serial bus 22 is caused by adjustment of communication timing between devices connected to the serial bus 22 (here, the DSP 20 and the nonvolatile memory 21), arbitration for preventing data collision, and clock. This is caused by signal misalignment or the like. The fluctuation is caused by such a factor, and the counter value becomes indefinite due to the fluctuation. To clarify this, here, immediately after the DSP 20 is started, the free-run counter 20c starts counting and continues. An experiment was performed in which a series of processes such as performing a blank reading to the nonvolatile memory 21 once and acquiring a counter value from the free-run counter 20c when the blank reading was completed 10 times.

  As a result of this experiment, as shown in FIG. 6, the counter value is “734599” for the first time, “734557” for the second time, “734419” for the third time, “734517” for the fourth time, and “734675” for the fifth time. The sixth time is “734542”, the seventh time is “734535”, the eighth time is “734586”, the ninth time is “734500”, the tenth time is “734493”, and the irregular values are different every time.

  Therefore, also from this experimental result, it was confirmed that the counter value of the free-run counter 20c becomes indefinite due to fluctuations in the processing time of the serial bus 22.

  Then, the pseudo random number generator 20b generates a pseudo random number from the seed using the counter value that is difficult and uncertain as described above as an initial value of the seed.

  In this way, the data processing circuit 11 can obtain a different counter value every time the DSP 20 is activated by reflecting the fluctuation of the processing time of the serial bus 22 in the counter value. By setting the initial value, it is possible to generate a pseudo-random number with higher randomness.

  In addition, the data processing circuit 11 uses an indefinite time that cannot be controlled from the hardware and program external to the data processing circuit 11, such as fluctuations in the processing time of the serial bus 22 provided in the data processing circuit 11. By doing so, for example, in an attempt to illegally use content, the host CPU 5 and the bus 4 are illegally controlled, and the time from the start of step SP1 to the start of step SP4 in the above-described pseudorandom number generation processing procedure is made constant. However, since an indefinite seed can always be obtained reliably, unauthorized use of the content can be prevented more reliably.

  Further, in the data processing circuit 11, since the seed is obtained by using the fluctuation of the processing time of the bus (serial bus 22) mounted on many general data processing circuits, the circuit has the following configuration. In addition to a simple bus (serial bus 22), a counter (free-run counter 20c) that can reflect fluctuations in the counter value only needs to be mounted. A circuit that generates pseudo-random numbers can be realized.

  According to the above configuration, the processing time fluctuation of the serial bus 22 is obtained by obtaining the counter value of the free-run counter 20c after performing idle reading into the nonvolatile memory 21 via the serial bus 22. It is possible to obtain an indefinite counter value by reflecting it in the above, and by generating a pseudo-random number from this seed with this indefinite counter value as a seed, a random number with higher randomness can be generated. In this case, it is only necessary to mount a bus (in this case, the serial bus 22) mounted on the general data processing circuit and a counter whose count cycle is shorter than the fluctuation of the bus processing time. Compared with this, the configuration can be simplified, and thus a random number with higher randomness can be generated while having a simple configuration. It can be.

(2) Second Embodiment Next, a second embodiment of the present invention will be described in detail. Since the second embodiment is the same as the first embodiment except that the configuration of the DSP 20 mounted on the data processing circuit 11 is different, the description of the same parts is omitted.

(2-1) Internal Configuration of Data Processing Circuit As shown in FIG. 7 in which the same reference numerals are given to the same parts as those in FIG. 2, the data processing circuit 11 of the second embodiment includes a pseudo random number in the DSP 20. A hash value generation unit 40 is newly provided between the generator 20b and the free-run counter 20c. The hash value generator 40 applies a hash function (one-way function) to the acquired counter value in order to discretize the counter value acquired by the free-run counter 20c. By doing so, the hash value generation unit 40 generates a hash value that becomes a discretized counter value, and transmits this hash value to the pseudo-random number generator 20b.

  Then, the pseudo random number generator 20b uses the hash value obtained from the hash value generation unit 40 as an initial value of seed, and generates a pseudo random number from the seed.

  As described above, in the second embodiment, the hash value generation unit 40 generates a hash value obtained by discretizing the counter value, and uses this hash value as an initial value of seed, thereby further increasing randomness. A pseudo-random number can be generated.

  Although the case where a hash function is used to discretize the counter value has been described here, the present invention is not limited to this, and various discretization functions such as a MAC function are used. May be.

(3) Other Embodiments In the above-described embodiment, the case where the DSP 20 and the nonvolatile memory 21 are connected by the serial bus 22 and the processing time fluctuation of the serial bus 22 is used is described. However, the present invention is not limited to this. For example, the DSP 20 and the nonvolatile memory 21 may be connected by a parallel bus, and the processing time fluctuation of the parallel bus may be used. The DSP 20 and the nonvolatile memory 21 may be connected to use the fluctuation in processing time of the bus.

  Further, in the above-described embodiment, the case where the counter value is acquired after performing the idle reading once to the nonvolatile memory 21 via the serial bus 22 is described, but the present invention is not limited to this. For example, the counter value may be obtained after performing idle reading a plurality of times, or in addition to empty reading to the nonvolatile memory 21, data is sent to the ROM 6, HDD 7, or hard disk drive 7 via the bus 4. The counter value may be acquired after transmitting / receiving (that is, idle reading). In this way, the randomness of the pseudo random number generated by the pseudo random number generator 20b can be further enhanced.

  Furthermore, in the above-described embodiment, in the explanation of the pseudo random number generation processing procedure, the DSP 20 of the data processing circuit generates a pseudo random number in response to a random number request command from the host CPU 5 and returns the generated pseudo random number to the host CPU 5. However, the present invention is not limited to this. For example, the host CPU 5 transmits an execution instruction for a specific process using a pseudo-random number to the DSP 20, and the DSP 20 receives the execution instruction. In response, a pseudo random number may be generated, a specific process using the pseudo random number may be executed, and a process result or a process completion notification may be returned to the host CPU 5.

  Furthermore, in the above-described embodiment, the case where the instruction processing unit 20a, the pseudo random number generator 20b, and the free-run counter 20c are provided as software functions in the DSP 20 of the data processing circuit 11 has been described. The present invention is not limited to this, and a part or all of the instruction processing unit 20a, the pseudo random number generator 20b, and the free-run counter 20c may be mounted on the data processing circuit 11 as hardware.

  Furthermore, in the above-described embodiment, when the instruction processing unit 20a receives a random number request command from the host CPU 5, it transfers this to the pseudo random number generator 20b, and the pseudo random number generator 20b responds to the random number request command with a non-volatile function. In the above description, a case has been described where idle reading is performed to the volatile memory 21, and after completion of the idle reading, the counter value is acquired from the free-run counter 20c to generate a pseudo-random number. When the processing unit 20a receives a random number request command from the host CPU 5, the command processing unit 20a performs idle reading to the nonvolatile memory 21, and after the idle reading is completed, the random number request command is transferred to the pseudo random number generator 20b. The pseudo random number generator 20b may acquire a counter value from the free-run counter 20c and generate a pseudo random number in response to the random number request command.

  Furthermore, in the above-described embodiment, the DSP 20 as the signal processing unit, the serial bus 22 as the bus, and the nonvolatile memory 21 as the memory constitute the data processing circuit and the content reproduction device 1 as the signal processing device. Although the case of doing so has been described, the present invention is not limited to this, and various other configurations may be used.

  Furthermore, in the above-described embodiment, in response to the command processing unit 20a as the control unit, the free-run counter 20c, and the random number request command as the random number request information transferred from the host CPU 5 via the command processing unit 20a, A pseudo random number generator 20b serving as a random number generation unit that obtains a counter value of the free-run counter 20c after performing idle reading to the nonvolatile memory 21 via the serial bus 22 and generates a random number using the acquired counter value as seed. However, the present invention is not limited to this, and various other configurations may be used.

  The present invention can be widely used in various circuits and devices for generating pseudo-random numbers.

It is a basic diagram which shows the whole structure of a content reproduction apparatus. It is a basic diagram which shows the internal structure of the data processing circuit by 1st Embodiment. It is a sequence chart which shows a pseudorandom number generation processing procedure. FIG. 4 is a sequence chart showing a pseudo-random number generation processing procedure continued from FIG. 3. 5 is a sequence chart showing a pseudo-random number generation processing procedure continued from FIG. 4. It is a table | surface which shows an experimental result. It is a basic diagram which shows the internal structure of the data processing circuit by 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Content reproduction apparatus, 2 ... Operation input part, 3 ... Input processing part, 4 ... Bus, 5 ... Host CPU, 6 ... ROM, 7 ... Hard disk drive, 8 ... RAM, 9 ... ... Communication processing unit, 10 ... Network interface, 11 ... Data processing circuit, 12 ... Audio processing unit, 20 ... DSP, 20a ... Command processing unit, 20b ... Pseudo-random number generator, 20c ... Free-run counter , 30 ... seed holding area, 40 ... hash value generator, NT ... network, SP ... speaker.

Claims (6)

A signal processing unit;
Comprising the signal processing unit and a memory connected via a bus,
The signal processor is
A counter having a shorter count cycle than fluctuations in the processing time of the bus,
A random number generator for generating random numbers from random number seeds;
A control unit that controls the operation of the random number generation unit in response to an external request,
The counter starts counting with the activation of the signal processing unit,
The control unit transfers the random number request information to the random number generation unit in response to random number request information for requesting a random number from the outside,
In response to the random number request information, the random number generation unit obtains a counter value of the counter after transmitting / receiving data to / from the memory via the bus, and generates a random number from a random seed corresponding to the acquired counter value. A signal processing device. The signal processing apparatus according to claim 1, wherein the random number generation unit reads data from a specific position of the memory via the bus according to the random number request information. A hash value generator for generating a hash value from the counter value,
The random number generation unit obtains a hash value of the hash value generation unit after transmitting / receiving data to / from the memory via the bus according to the random number request information, and a random number corresponding to the acquired hash value The signal processing device according to claim 1, wherein a random number is generated from a seed. The signal processing apparatus according to claim 1, wherein the bus is a serial bus. In a signal processing method by a signal processing device having a memory connected via a bus,
At the time of start-up, a count start step for starting counting at a count cycle shorter than the fluctuation of the bus processing time,
In response to random number request information for requesting a random number from the outside, after transmitting and receiving data to and from the memory via the bus, a counter value acquisition step for acquiring the counter value of the counter;
A signal processing method comprising: a random number generation step for generating a random number from a random number seed corresponding to the counter value acquired in the counter value acquisition step. For a signal processing device having a memory connected via a bus,
At the time of start-up, a count start step for starting counting at a count cycle shorter than the fluctuation of the bus processing time,
In response to random number request information for requesting a random number from the outside, after transmitting and receiving data to and from the memory via the bus, a counter value acquisition step for acquiring the counter value of the counter;
And a random number generation step of generating a random number from a random number seed corresponding to the counter value acquired in the counter value acquisition step.

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