JP2006210563A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a high-voltage resistance MOS transistor which is formed on a silicon substrate, including high-concentration oxygen impurity. <P>SOLUTION: An extended drain region 2 formed of n-type impurity and a source region 3, formed of n-type impurity in a concentration of about 3×10<SP>15</SP>to 1×10<SP>16</SP>cm<SP>-3</SP>having the depth of about 3 to 5 μm, are formed on a p-type silicon substrate 1. The p-type silicon substrate 1 has been manufactured with the CZ method and obtains p-type characteristics by introducing boron as an impurity. Concentration of this p-type impurity is 1×10<SP>15</SP>cm<SP>-3</SP>. Moreover, an embedded layer 10, formed of n-type impurity, is formed from the joining part of the extended drain region 2 and the semiconductor substrate 1 at the lower part of the n-type extended drain region 2 on the p-type silicon substrate 1, in the concentration range of about 3×10<SP>15</SP>cm<SP>-3</SP>to 1×10<SP>16</SP>cm<SP>-3</SP>and thickness of about 0.5 to 2 μm at the depth of about 10 to 50 μm. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a lateral MOS transistor structure.

  Various semiconductor structures have been proposed for semiconductor devices having a MOS transistor structure with high breakdown voltage characteristics.

  Hereinafter, the semiconductor device disclosed in Patent Document 1 will be described with reference to FIG.

  First, an extended drain region 102 made of n-type and a source region 103 made of n-type are formed on one surface of the p-type silicon substrate 101, respectively.

  A high-concentration n-type drain contact region 104 is formed on the surface of the extended drain region 102, and the n-type drain contact region 104 is connected to the drain electrode 105.

  A p-type substrate contact region 106 is formed on one surface of the silicon substrate 101 so as to be adjacent to the n-type source region 103, and the source region 103 and the substrate contact region 106 are connected to the source electrode 107. Thereby, the source region 103 is set to the same potential as the silicon substrate 101.

  Further, between the n-type extended drain region 102 and the n-type source region 103 in the surface portion of the silicon substrate 101, a p-type so as to surround the n-type source region 103 and the p-type substrate contact region 106. An anti-punch through region 108 is formed.

  In the anti-punch through region 108, when a high voltage is applied to the extended drain region 102, the depletion layer extending toward the channel region and the source region 103 are brought into contact with each other to be in a short circuit state (punch through state). To prevent that.

  Further, a gate electrode 109 is formed between the extended drain region 102 and the source region 103 in the surface portion of the silicon substrate 101 via a gate insulating film, and a region under the gate electrode 109 in the silicon substrate 101 is a channel region. Function as.

  In the semiconductor device having the above structure, when a high voltage is applied to the extended drain region 102 via the drain electrode 105, the extended drain region 102 and the silicon substrate 101 are in a reverse bias state. A depletion layer spreads from the junction with the silicon substrate 101.

Therefore, the high withstand voltage characteristic of the MOS transistor is realized by the withstand voltage of the depletion layer.
JP-A-3-227572

  In order to obtain a high breakdown voltage characteristic which is an important characteristic in a power IC, in Patent Document 1, a transistor structure characterized by an extended drain region and a substrate made of a silicon single crystal with less impurities such as oxygen (hereinafter referred to as silicon substrate) are used. It is necessary to use it.

However, a silicon substrate manufactured by the CZ ( Cz ochralski) method has a high concentration of impurities such as oxygen, and includes, for example, about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ^{−3 of} oxygen impurities.

Therefore, and FZ (F loat Z one) method in Patent Document 1, must be used a silicon substrate manufactured by MCZ (M agnetic Field Applied Cz ochralski ) method.

  However, compared to the CZ method used for general silicon substrate manufacturing, the FZ method and MCZ method are expensive to manufacture a silicon substrate, and there are many technical difficulties in increasing the substrate diameter. Have.

  In view of the above problems, an object of the present invention is to provide a semiconductor device having a high voltage MOS transistor that can use a silicon substrate formed by the CZ method.

  In order to solve the above problems, a semiconductor device of the present invention includes an n-type source region provided on one main surface of a p-type semiconductor substrate containing a high concentration of oxygen impurities, and an n-type provided on one main surface of the semiconductor substrate. Type drain contact region and n-type extended drain region, an n-type buried layer provided below the extended drain region while being separated from the extended drain region, and surrounding the source region between the source region and the extended drain region And an anti-punch through region provided in this manner, and a gate electrode provided on the anti-punch through region with a gate insulating film interposed therebetween.

  In the semiconductor device of the present invention, the semiconductor substrate is more preferably a silicon single crystal formed by the CZ method.

In the semiconductor device of the present invention, the oxygen impurity concentration is more preferably 1 × 10 ¹⁷ cm ⁻³ or more.

In the semiconductor device of the present invention, the p-type impurity concentration of the semiconductor substrate is more preferably 1 × 10 ¹⁵ cm ⁻³ or more.

  In the semiconductor device of the present invention, it is more preferable that a second buried layer which is separated from the anti-punch through region and is continuous with the buried layer is provided below the anti-punch through region.

  In the semiconductor device of the present invention, the p-type impurity of the silicon substrate can be set to a high concentration, and accordingly, a high voltage MOS transistor can be formed on the silicon substrate containing a high concentration of oxygen impurity.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a structural cross-sectional view of a semiconductor device according to a first embodiment of the present invention, and specifically shows a lateral MOS transistor.

First, an extended drain region 2 made of n-type impurities having a depth of about 3 to 5 μm and having a concentration of about 3 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^{−3 is formed on} the p-type silicon substrate 1 and n-type impurities. A source region 3 is formed.

The silicon substrate 1 is a substrate manufactured by the CZ method, and boron, which is an impurity, is introduced to obtain p-type characteristics. The concentration of this p-type impurity is 1 × 10 ¹⁵ cm ⁻³ .

  A high concentration n-type drain contact region 4 is formed on the surface of the extended drain region 2. The n-type drain contact region 4 is connected to the drain electrode 5.

  A p-type substrate contact region 6 is formed on one surface of the substrate 1 so as to be adjacent to the n-type source region 3, and the source region 3 and the substrate contact region 6 are connected to the source electrode 7. As a result, the source region 3 has the same potential as the substrate 1.

  Further, a p-type anti-punch through region 8 is formed between the extended drain region 2 and the source region 3 so as to surround the source region 3 and the substrate contact region 6.

  In the anti-punch through region 8, when a high voltage is applied to the extended drain region 2, the depletion layer extending toward the channel region and the source region 3 are brought into contact with each other to be in a short circuit state (punch through state). To prevent that.

  Further, between the extended drain region 2 and the source region 3, a gate electrode 9 is formed on the substrate 1 via a gate insulating film, and below the gate electrode 9 functions as a channel region.

Further, below the extended drain region 2, a concentration of about 3 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ is formed at a depth of about 10 to 50 μm from the junction between the extended drain region 2 and the substrate 1. The n-type buried layer 10 is formed with a thickness of about 0.5 to 2 μm.

  As described above, the semiconductor device according to the first embodiment of the present invention is configured.

  The first embodiment of the present invention is characterized in that a buried layer 10 made of an n-type impurity is provided below an n-type extended drain region 2 on a p-type silicon substrate 1.

  In this device configuration, in the substrate depth direction from the drain region 4, a first pn junction surface 11 formed by the extended drain region 2 and the p-type silicon substrate 1, and a second pn junction surface formed by the p-type silicon substrate 1 and the buried layer 10. 12 and the buried layer 10 and the third pn junction surface 13 made of the p-type silicon substrate 1 are sequentially formed.

  When the extended drain region 2 and the source region 3 are in a non-conduction state, the first pn junction surface 11 is in a reverse bias state, and the first depletion layer extends in the depth direction of the substrate 1. As the first depletion layer expands, the second pn junction surface 12 is in a forward bias state, the third pn junction surface 13 is in a reverse bias state, and the third pn junction surface 13 has a second depletion layer formed on the substrate. Expands in the depth direction.

  That is, the transistor structure according to the first embodiment of the present invention can obtain a desired breakdown voltage characteristic of the MOS transistor by the sum of the first depletion layer and the second depletion layer. Since the depletion layer does not require the same extent as the depletion layer formed by the prior art, the p-type impurity of the silicon substrate 1 can be made high in concentration.

  On the other hand, in order to obtain a high breakdown voltage in the MOS transistor structure shown in the prior art, it is required to further expand the region of the depletion layer formed from the junction between the extended drain region 2 and the silicon substrate 1. The p-type impurity in the substrate 1 must be low in concentration.

  If the p-type impurity in the silicon substrate 1 is made low in concentration, it is easily affected by oxygen impurities contained in the silicon substrate, so that a silicon substrate manufactured by the FZ method or MCZ method with little oxygen impurities is required.

  However, in the first embodiment of the present invention, the p-type impurity in the silicon substrate 1 can be made high in concentration by the device structure. Therefore, the oxygen impurity contained in the silicon substrate of the CZ method has an effect of lowering the concentration of the p-type impurity. Get smaller.

  Therefore, according to the first embodiment of the present invention, a high voltage MOS transistor can be formed using a silicon substrate by the CZ method.

Specifically, in the semiconductor device according to the first embodiment of the present invention, the drain breakdown voltage is 700 V, which is a silicon substrate manufactured by the MCZ method with a p-type impurity concentration of 1 × 10 ¹⁴ cm ^−3. When the MOS transistor described in the prior art is formed, the drain breakdown voltage characteristic equivalent to that can be obtained.

  In the semiconductor device according to the first embodiment of the present invention, when a silicon substrate manufactured by the FZ method or the MCZ method is used as in the background art, high breakdown voltage characteristics superior to the background art are obtained. I can do it.

  Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2, an SiO ₂ film 32a is formed on a silicon substrate 31 manufactured by the CZ method with a p-type impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ .

Next, as shown in FIG. 3, a resist film is formed which is patterned on the SiO ₂ film 32a, a SiO ₂ film 32a is etched and the resist is removed as a mask, forming a SiO ₂ film 32b of the patterned To do.

Next, as shown in FIG. 4, phosphorus is implanted at a dose of about 5 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² using the patterned SiO ₂ film 32b as a mask.

Next, as shown in FIG. 5, heat treatment is performed in an N ₂ atmosphere at 800 ° C. to 1200 ° C. for about ₂ to 4 hours, and a concentration of about 3 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ is obtained. Then, an n-type impurity layer having a thickness of about 3 to 5 μm is formed. This N-type impurity layer is an extended drain region 33.

Next, as shown in FIG. 6, after forming the SiO ₂ film and the Si ₃ N ₄ film, Si ₃ N ₄ the patterned resist film on the form, the SiO ₂ film and the Si ₃ N ₄ as a mask The film is etched and the resist is removed to form a patterned SiO ₂ film 34 and a Si ₃ N ₄ film 35.

Next, as shown in FIG. 7, a patterned resist film 36 is formed, and using this as a mask, boron is deposited at a dose of about 2 × 10 ¹² cm ^{−2 to} 5 × 10 ¹² cm ⁻² with SiO _2. Implantation is performed so as to penetrate the film 34 and the Si ₃ N ₄ film 35.

Next, as shown in FIG. 8, the patterned resist film 36 is removed, and thermal oxidation is performed using the Si ₃ N ₄ film as a mask to form element isolation SiO ₂ (38a, 38b), and Si ₃ N ₄ film and SiO ₂ film are removed. At the same time, thermal diffusion of B implanted in the step of FIG. 7 is performed to form a p-type anti-punch through region 37 having a concentration of about 1 × 10 ¹⁶ cm ⁻³ .

Next, as shown in FIG. 9, the resist film 39 is patterned, and using this as a mask, phosphorus is implanted at a dose of about 5 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² .

  Next, as shown in FIG. 10, the resist film 39 is removed and heat treatment is performed, and the phosphorus implanted in FIG. 9 is diffused to form an n-type buried layer 40. The n-type buried layer 40 is approximately 20 μm below the junction between the extended drain region and the silicon substrate 1 and has a thickness of approximately 0.5 to 2 μm.

Next, as shown in FIG. 11, a gate insulating film 41 and a gate electrode 42 are formed, followed by formation of a patterned resist film, and using it as a mask, arsenic is 1 × 10 ¹⁵ cm ^{−2 to} 5 −5. A source region 43 and a drain contact region 44 are formed by implanting about × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 12, patterned resist films 45a and 45b are formed, and using this as a mask, boron is implanted at about 1 × 10 ¹⁵ cm ^{−2 to} 5 × 10 ¹⁵ cm ⁻² to form a substrate contact. Region 46 is formed.

  Finally, as shown in FIG. 13, the formation of the interlayer insulating film 47, the flattening of the interlayer insulating film 47 by heat treatment, the formation of the contact holes 48a and 48b, the formation of the metal wirings 49a and 49b, and the protective film 50 are sequentially formed.

  The semiconductor device according to the first embodiment of the present invention is manufactured through the above steps.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

In the present embodiment, the buried layer 210 has a depth of about 3 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm at a depth of about 10 to 50 μm from the junction between the extended drain region 202 and the p-type semiconductor substrate 201. An n-type impurity layer having a concentration of ⁻³ and a thickness of about 0.5 to 2 μm is formed below the extended drain region 202 and the anti-punch through region 208.

  Other transistor structures and silicon substrate conditions are the same as those in the first embodiment.

  In the structure of this semiconductor device, the step of forming a patterned resist film can be eliminated before the buried layer 210 is implanted, and the number of steps can be reduced.

  Note that, in the semiconductor device according to the second embodiment of the present invention, when a silicon substrate manufactured by the FZ method or the MCZ method is used as in the background art, a high breakdown voltage characteristic superior to the background art is obtained. I can do it.

  The semiconductor device according to the present invention can set the p-type impurity of the silicon substrate to a high concentration, and accordingly, a silicon substrate formed by the CZ method can be used, which is useful as a low-cost power transistor.

Sectional drawing showing the semiconductor device of the first embodiment of the present invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention Sectional drawing of the structure of the semiconductor device of the 2nd Embodiment of this invention Structural sectional view showing a conventional semiconductor device

Explanation of symbols

1 p-type silicon substrate 2 extended drain region 3 source region 4 drain contact region 5 drain electrode 6 substrate contact 7 source electrode 8 anti-punch through region 9 gate electrode 10 buried layer 11 first pn junction surface 12 second pn junction surface 13 Third pn junction surface 201 p-type silicon substrate 202 extended drain region 203 source region 204 drain contact region 205 drain electrode 206 substrate contact 207 source electrode 208 anti-punch through region 209 gate electrode 210 buried layer

Claims (6)

An n-type source region provided on one main surface of a p-type semiconductor substrate containing a high concentration of oxygen impurities;
An n-type drain contact region and an n-type extended drain region provided on one main surface of the semiconductor substrate;
An n-type buried layer provided below the extended drain region while being separated from the extended drain region;
An anti-punch through region provided so as to surround the source region between the source region and the extended drain region;
And a gate electrode provided on the anti-punch through region via a gate insulating film. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon single crystal formed by a CZ method. The semiconductor device according to claim 1, wherein the oxygen impurity concentration is 1 × 10 ¹⁷ cm ⁻³ or more. 4. The semiconductor device according to claim 1, wherein the semiconductor substrate has a p-type impurity concentration of 1 × 10 ¹⁵ cm ⁻³ or more. 2. The semiconductor device according to claim 1, further comprising a second buried layer that is separated from the anti-punch through region and is continuous with the buried layer, below the anti-punch through region. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a high breakdown voltage lateral MOS transistor.

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