JP2006186187A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device which secures a large surface area for the opening of a photodiode and avoids blockage of light incident to the photodiode, and also to provide a method for manufacturing the imaging device. <P>SOLUTION: In a salicide formation process, a detecting wiring line 217 for connecting a floating diffusion 203 and a gate electrode 104g of an amplification transistor 104 is formed in the form of a high-melting-point metallic material not reacting with the silicide reaction on a non-silicon surface generated in the salicide formation process. Consequently, the wiring is located in a region narrower than in the prior art, and thus the opening surface area of a photodiode is made large. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a MOS type solid-state imaging device and a manufacturing method thereof.

  As is well known, in a MOS type solid-state imaging device, a MOS transistor is arranged in each pixel cell. The signal charge generated in the photodiode portion of each pixel cell is taken out as an electric signal for each pixel cell via the MOS transistor. Such a MOS type solid-state imaging device has a higher scanning freedom than a CCD (Charge Coupled Device) type solid-state imaging device, uses a CMOS process, has a low manufacturing cost, and has a simple driving method. It has features such as realizing a system-on-chip.

  Hereinafter, the structure and operation of a pixel cell of a conventional solid-state imaging device will be briefly described. FIG. 11A is a circuit diagram of a general MOS solid-state imaging device, and FIG. 11B is an enlarged circuit diagram of the pixel cell portion of FIG. 11A. FIG. 12 is a plan view showing an example of the pattern layout of the pixel cell of the MOS type solid-state imaging device. 11 and 12, a region surrounded by a two-dot chain line corresponds to one pixel cell. In addition, in order to make correspondence with FIG. 11 and FIG. 12 easy, the code | symbol of the part corresponding in FIG. 11 (b) is attached | subjected.

  As shown in FIG. 11B, each pixel cell 100 includes a photodiode 101, a transfer transistor 102, a reset transistor 103, and an amplification transistor 104. The cathode of the photodiode 101 and the sources and drains of the transistors 102 to 104 are constituted by N-type impurity regions 201 to 205 formed on the surface portion of a P-type semiconductor substrate, as indicated by dotted lines in FIG. Has been. In this example, the anode of the photodiode 101 is a P-type semiconductor substrate.

  In the example shown in FIG. 12, an impurity region 201 (hereinafter referred to as a charge storage layer 201) that constitutes the cathode of the photodiode 101 has a rectangular shape, and the transfer transistor 102 extends along the short side of the charge storage layer 201. An impurity region 202 (hereinafter referred to as a charge extraction layer 202) is provided. The charge storage layer 201 and the charge extraction layer 202 are disposed so as to partially overlap each other inside the semiconductor substrate and are electrically connected.

  As shown in FIG. 11B, the drain of the transfer transistor 102 and the source of the reset transistor 103 are common, and are configured as a common impurity region 203 (hereinafter referred to as a floating diffusion 203). In the example of FIG. 12, the floating diffusion 203 faces the charge extraction layer 202 with a gate electrode 102g (hereinafter referred to as transfer gate electrode 102g) of the transfer transistor 102 disposed in parallel with the long side of the charge storage layer 201 interposed therebetween. It is arranged at the position to

  Further, the drain of the reset transistor 103 and the drain of the amplification transistor 104 are also formed of a common impurity region 204 (hereinafter referred to as a potential diffusion layer 204). This potential diffusion layer 204 faces the floating diffusion 203 with a gate electrode 103g (hereinafter referred to as a reset gate electrode 103g) of the reset transistor 103 disposed along a direction perpendicular to the transfer gate electrode 102g interposed therebetween. Placed in position.

  Note that the transfer gate electrode 102g is configured to function as a common electrode for all the pixel cells arranged along the long side direction of the charge storage layer 201, and is illustrated in FIG. It is connected to the vertical driver circuit 107. Further, the reset gate electrode 103g of all the pixel cells shared by the transfer gate electrode 102g has an end located on the opposite side of the transfer gate electrode 102g by a reset line 121 arranged in parallel with the transfer gate electrode 102g. Similar to the transfer gate electrode 102g, it is connected to the vertical driver circuit 107 shown in FIG.

  Further, as shown in FIG. 12, a gate electrode 104g (hereinafter referred to as a detection gate electrode 104g) of the amplification transistor 104 disposed in parallel with the reset gate electrode 103g between the transfer gate electrode 102g and the reset line 121. An impurity region 205 (hereinafter referred to as an output layer 205) that constitutes the source of the amplification transistor 104 is disposed at a position opposite to the potential diffusion layer 204 across the electrode.

  The gate electrodes 102g, 103g, 104g and the reset line 121 described above are formed as a pattern of polysilicon or the like on the surface of the semiconductor substrate, and are formed on the surface of the semiconductor substrate immediately below the gate electrodes 102g, 103g, 104g. Are provided with a gate insulating film made of a silicon oxide film or the like. In FIG. 12, the group of wires are indicated by broken lines.

  On the other hand, on each gate electrode 102g, 103g, and 104g, a first metal wiring layer made of Al or the like is disposed via a first interlayer insulating film 225 (see FIG. 14) made of a silicon nitride film or the like. The

  In the example of FIG. 12, a detection wiring 211, a connection pattern 212, and a vertical signal line 111 are formed by this first metal wiring layer (shown by a solid line in FIG. 12).

  The detection wiring 211 is a wiring for connecting the detection gate electrode 104g and the floating diffusion 203, and the floating diffusion 203 and the detection gate electrode through the contact holes 231 and 232 penetrating the first interlayer insulating film 225. 104g. The connection pattern 212 is a pattern that serves as a connection portion between the power diffusion layer 204 and a second metal wiring layer, which will be described later, and the power diffusion layer via a contact hole 233 that penetrates the first interlayer insulating film 225. 204 is connected. Further, the vertical signal line 111 is a wiring connected to the output layer 205 of all the pixel cells arranged along the short side direction of the charge storage layer 201, and is connected to the output layer 205 through the contact hole 234. ing.

  As shown in FIG. 11A, one end of the vertical signal line 111 is connected to the output signal line 113 via the load transistor 105, and the other end thereof is connected to the noise suppression circuit 108 and the horizontal transistor 110. It is connected to the ground line 112. The gate of the horizontal transistor 110 is connected to the horizontal driver circuit 109.

  On each pattern of the first metal wiring layer, a second metal wiring layer made of Al or the like is formed via a second interlayer insulating film 226 (see FIG. 14) made of a silicon nitride film or the like. A protective film 227 (see FIG. 14) made of a silicon nitride film or the like is formed on the upper surface.

  FIG. 13 is a plan view showing a state in which the second metal wiring layer is formed in the upper layer of FIG. As shown in FIG. 13, a power supply wiring 213 having an opening above the charge storage layer 201 is formed as a second metal wiring layer. The power supply wiring 213 is connected to the connection pattern 212 through the via hole 235 that penetrates the second interlayer insulating film 226, and as a result, connected to the power supply diffusion layer 204.

  Further, the power supply wiring 213 is connected to the power supply 106 as shown in FIG. 11A, and has a function of supplying power to each transistor and preventing light from entering other than the charge storage layer 201. Yes.

  In the above structure, signal charges generated by photoelectric conversion in response to incident light are accumulated in the charge accumulation layer 201. Here, when the vertical driver circuit 107 applies a voltage to the transfer gate electrode 102g to turn on the transfer transistor 102, the signal charge flows into the floating diffusion 203 (hereinafter, abbreviated as FD 203 as appropriate), and the FD 203. Of the signal fluctuate in accordance with the amount of the signal charge.

  As described above, the FD 203 is connected to the detection gate electrode 104g by the detection wiring 211. Therefore, in this state, when the horizontal driver circuit 109 applies a voltage to the horizontal transistor 110 corresponding to the pixel cell 100 to turn on the horizontal transistor 110, the amplification transistor 104 becomes a source follower circuit and is stored in the FD 203. An output signal corresponding to the signal charge is output to the vertical signal line 111. Thereafter, when the vertical driver circuit 107 applies a voltage to the reset gate electrode 103g to turn on the reset transistor 103, the signal charge accumulated in the FD 203 is discharged from the FD 203 via the reset line 121, and the potential of the FD 203 Becomes equal to the potential of the power source diffusion layer 204. As a result, the FD 203 is initialized.

  Incidentally, in the layout of the pixel cell 100, in order to improve the sensitivity and saturation output of the pixel, it is preferable that the light receiving area of the photodiode 101 (the area of the charge storage portion 201 shown in FIG. 12) is as large as possible. However, the area that can be occupied by one pixel cell on the semiconductor substrate is limited by the chip size of the solid-state imaging device, the number of pixels to be formed, and the like. Therefore, in the layout of the pixel cell 100, it is preferable to reduce the area of the region other than the photodiode 101 as much as possible. For this reason, the gate electrode of each transistor and the pattern of the first metal wiring layer are arranged as close as possible, and these wirings are arranged so as not to prevent light incidence on the photodiode 101. It becomes important.

  In the example of FIG. 12, since it is not preferable to form the contact hole 232 immediately above the amplification transistor 104, the detection gate electrode 104g extends to the outside of the transistor region, and the contact hole 232 is formed at a position adjacent to the amplification transistor 104. A space for forming is provided. In order to secure this space, the interval between the transfer gate electrode 102g and the reset line 121 is widened, and as a result, the opening area of the photodiode 101 is reduced.

  Furthermore, since it is necessary to arrange the detection wiring 211 and the connection pattern 212 side by side in the first metal wiring layer, the pattern of the detection wiring 211 is arranged to overlap above the transfer gate electrode 102g. Yes. In this layout, as shown in FIG. 14 (A-A cross section in FIG. 12), a part of the light L incident obliquely on the photodiode 101 is blocked by the detection wiring 211 and incident on the photodiode 101. The problem that the quantity of light to reduce will also generate | occur | produce will occur.

  As a countermeasure, Patent Document 1 described later discloses a technique of using the electrode pattern of the detection gate electrode 104g as a wiring for connecting the detection gate electrode 104g and the FD 203 as shown in FIG. That is, the electrode pattern of the detection gate electrode 104g is extended to a position overlapping the contact 203a provided on the FD 203, and the FD 203 and the detection gate electrode 104g are connected.

According to this configuration, the contact hole 232 (and the contact hole 231) is not necessary, so that the interval between the transfer gate electrode 102g and the reset line 121 can be reduced. Further, since the detection wiring 211 is not necessary, the light L incident in an oblique direction is not blocked.
JP 2003-197892 A

  When the technique described in Patent Document 1 is adopted, since the detection gate electrode 104g is directly connected to the FD 203, the transfer gate electrode 102g and the detection gate electrode 104g are arranged in parallel. Since both are gate electrodes of the transistor, a pattern is formed by the same photolithography process. Therefore, the minimum distance d (see FIG. 15) between the transfer gate electrode 102g and the detection gate electrode 104g is limited by the resolution limit of the photolithography process.

  With the recent miniaturization of element dimensions, the area allocated to one pixel cell is expected to become smaller in the future. For this reason, in order to secure the opening area of the photodiode 101 as large as possible, it is necessary to make it possible to arrange the wiring in a narrower region.

  The present invention has been made in view of the above-described conventional circumstances, and it is possible to secure a large opening area of the photodiode as compared with the conventional case, and to perform a wiring arrangement that does not prevent light from entering the photodiode. It is an object of the present invention to provide a solid-state imaging device capable of performing the same and a manufacturing method thereof.

  In order to achieve the above object, the solid-state imaging device according to the present invention employs the following means. First, the present invention transfers a signal charge generated by photoelectric conversion in a photodiode to a floating diffusion that temporarily accumulates the signal charge, and sends a signal corresponding to the potential of the floating diffusion through an amplification transistor. It is assumed that a solid-state imaging device in which pixel cells to be output are arranged in a matrix.

  The solid-state imaging device according to the present invention has a configuration in which the floating diffusion and the gate electrode of the amplification transistor are connected by a wiring mainly composed of a refractory metal formed in the same wiring layer as the gate electrode. Is adopted. Here, the same wiring layer indicates that the wiring is connected without an insulating film, that is, without a through hole.

  Further, it is preferable that the wiring connecting the floating diffusion and the gate electrode of the amplification transistor is in contact with the floating diffusion and the amplification transistor through a refractory metal silicide. Furthermore, the wiring may adopt a configuration in which the refractory metal continuously transitions to the silicide at both ends thereof.

  On the other hand, in another aspect, the present invention can provide a method for manufacturing the solid-state imaging device. The method for manufacturing a solid-state imaging device according to the present invention transfers a signal charge generated by photoelectric conversion in a photodiode to a floating diffusion that temporarily accumulates the signal charge, and a signal corresponding to the potential of the floating diffusion. Is premised on a method of manufacturing a solid-state imaging device in which pixel cells that output through an amplification transistor are arranged in a matrix.

  In the method for manufacturing a solid-state imaging device according to the present invention, first, a conductive film mainly composed of a refractory metal that covers at least part of the gate electrode of the floating diffusion and the amplification transistor formed on the semiconductor substrate is formed. Form. Then, silicide is formed by reacting the conductive film with the material of the floating diffusion and the gate electrode of the amplification transistor which are in contact with the conductive film. In this state, an insulating film is formed on the silicide and the unreacted conductive film, and the insulating film is selectively removed, thereby insulating corresponding to the wiring connecting the floating diffusion and the gate electrode of the amplification transistor. A film pattern is formed. Using the insulating film pattern as a mask, the conductive film is selectively removed to form a wiring pattern that connects the floating diffusion and the gate electrode of the amplification transistor.

  According to the present invention, in the MOS type solid-state imaging device, the area necessary for arranging the wiring connecting the floating diffusion and the gate electrode of the amplification transistor can be made narrower than the conventional one. For this reason, the opening area (light receiving area) of the photodiode can be increased, and the detection sensitivity and the saturation output can be improved as compared with the solid-state imaging device employing the conventional wiring arrangement.

  Further, since the wiring connecting the floating diffusion and the gate electrode of the amplification transistor is formed in the same wiring layer as the gate electrode, metal wiring that prevents light from entering the photodiode can be reduced.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  FIG. 1 is a plan view showing an example of a pixel cell pattern layout of a solid-state imaging device to which the present invention is applied. FIG. 1 is a plan view showing a state in which the pattern of the first metal wiring layer is formed, as in FIG. 12, and the pattern of the second interlayer insulating film and the second metal wiring layer is shown. Not. 2 to 9 are cross-sectional views of the main part showing a part of the manufacturing process of the solid-state imaging device according to the present invention. 2 to 9, FIGS. 2A to 9A are cross-sectional views taken along the line AA in FIG. 1, and FIGS. 2B to 9B are FIGS. It is a figure which shows the cross section of BB shown in FIG.

  Hereinafter, the structure of the solid-state imaging device according to the present invention will be described together with the manufacturing process thereof. In the drawings, the same parts as those in the prior art are denoted by the same reference numerals.

  The solid-state imaging device of the present invention is the same as the conventional solid-state imaging device shown in FIG. 11 in terms of circuit configuration, and includes a photodiode 101, a transfer transistor 102, a reset transistor 103, and an amplification transistor 104. Further, the process until the gate electrodes 102g, 103g, and 104g of each transistor are formed is formed by a known CMOS process. FIG. 2 shows the gate electrodes 102g, 103g, 104g is formed.

  As shown in FIG. 1 and FIGS. 2A and 2B, each surface portion of a P-type silicon semiconductor substrate 200 (or an N-type silicon semiconductor substrate in which a deep P-type well is formed) An element isolation 224 that electrically isolates the pixel cell 100 and each of the active elements 101, 102, 103, and 104 is formed using a known element isolation method such as LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). Is done.

  In addition, an N-type impurity is introduced by an ion implantation method or the like, and a charge accumulation portion 201 (photodiode 101) is formed on the surface portion of the semiconductor substrate 200. Thereafter, a surface oxide film serving as a gate insulating film of each of the transistors 102, 103, and 104 is formed on the surface of the semiconductor substrate 200, and gate electrodes 102g, 103g, and 104g having sidewalls 223 are formed. In this embodiment, the gate electrodes 102g, 103g, and 104g are formed of polysilicon, and the sidewalls 223 are formed of a silicon oxide film.

  These gate electrodes 102g, 103g, and 104g are formed by a known salicide structure formation process, and the formation process will be briefly described here. In the salicide structure forming process described below, the charge storage layer 201 is covered with a resist film or the like and is not damaged during the process.

  First, a conductive film made of polysilicon is formed on the gate insulating film by a CVD method or the like, and patterns of the gate electrodes 102g, 103g, 104g and the reset line 121 are formed by photolithography and etching.

  Next, N-type impurities are introduced into the semiconductor substrate 200 by an ion implantation method or the like using the patterns of the gate electrodes 102g, 103g, and 104g as masks to form shallow impurity regions having a relatively low concentration. Then, a silicon oxide film covering the gate electrodes 102g, 103g, and 104g is deposited by using a CVD method, and each gate electrode 102g, 103g is subjected to etch back using anisotropic etching such as RIE (Reactive Ion Etching). 104 g of sidewalls 223 are formed.

  Then, using the gate electrodes 102g, 103g, and 104g provided with the sidewalls 223 as masks, N-type impurities are introduced into the semiconductor substrate 200 at a high concentration by ion implantation or the like, whereby the charge extraction layer 202, the FD 203, the power source A diffusion layer 204 and an output layer 205 are formed, and impurity regions corresponding to the transistors 102, 103, and 104 are completed. The element isolation 224 is formed in the semiconductor substrate 200 immediately below the gate electrodes 102g, 103g, and 104g excluding the regions of the transistors 102, 103, and 104, and directly below the reset line 121. Needless to say, they are electrically separated.

  Now, in the solid-state imaging device according to the present invention, the silicide block that covers the upper surface of the charge storage layer 201 with the gate electrodes 102g, 103g, 104g formed as described above, as shown in FIG. A film 218 is formed. The silicide block film 218 is formed, for example, by forming a silicon oxide film on the semiconductor substrate 200 by CVD or the like, and performing photolithography and etching on the silicon oxide film.

  As shown in FIG. 2A, the wiring resistance is reduced at the end of the silicide block film 218 in the vertical direction (the direction in which the vertical signal line 111 extends in FIG. 1) by forming a silicide described later. In order to be able to do so, it is positioned above the transfer gate electrode 102g and above the reset line 121 of the adjacent pixel cell. In the horizontal direction (the direction in which the reset line 121 extends in FIG. 1), a common silicide block film 218 is formed over all the pixel cells 100 formed along the direction.

  Next, as shown in FIGS. 3A and 3B, a refractory metal film 219 is deposited on the semiconductor substrate 200 on which the silicide block film 218 is formed. For example, the refractory metal film 219 may be formed by depositing a material such as cobalt or titanium on the entire surface of the semiconductor substrate 200 using a sputtering method or the like. Note that a titanium nitride film (not shown) may be deposited on the refractory metal film 219 as necessary. For example, when the refractory metal film 219 is a titanium film, this titanium nitride film can improve the controllability of the salicide reaction described later, and when the refractory metal film 219 is a cobalt film, Oxidation can be prevented.

  After the refractory metal film 219 is formed as described above, silicide is formed by reacting the refractory metal film 219 with silicon of the semiconductor substrate 200 or silicon of the gate electrodes 102g, 103g, and 104g. The first heat treatment is performed.

  By this first heat treatment, as shown in FIGS. 4A and 4B, the refractory metal film 219 and the silicon substrate 200, and the refractory metal film 219 and the gate electrodes 102g, 103g, and 104g are brought into contact with each other. Silicide 220 is formed in the existing region. At this time, the refractory metal film 219 formed on the element isolation 224, the sidewall 223, and the silicide block film 218 is not silicided because there is no reactive silicon.

  In the first heat treatment, the silicide 220 formed over the FD 203, the potential diffusion layer 204, and the output layer 205 functions as an electrode electrically connected to each layer. Therefore, in the state shown in FIGS. 4A and 4B, the FD 203, the potential diffusion layer 204, the output layer 205, and the gate electrodes 102g, 103g, and 104g are separated from the refractory metal film 219 via the silicide 220. Each is electrically connected.

  4A and 4B show a state in which an unreacted refractory metal remains on the FD 203. However, depending on the heat treatment conditions, the refractory metal 219 may all become silicide 220. is there. In the drawing, for the sake of convenience, the interface between the silicide 220 and the unreacted refractory metal film 219 is clearly shown. However, as is well known, silicide is generated by an alloying reaction between a refractory metal and silicon. It is. Therefore, between the unreacted refractory metal 219 and the silicide 220, the composition continuously changes from unreacted refractory metal to silicide.

  After the first heat treatment is completed, as shown in FIGS. 5A and 5B, an insulating film 221 made of, for example, a silicon oxide film is formed on the surface of the refractory metal film 219. Note that, when the semiconductor substrate 200 is exposed to a high temperature of 500 ° C. or higher in the process of forming the insulating film 221, silicon aggregation occurs in the silicide 220 and wiring resistance increases. In order to avoid this, it is preferable to employ a low-temperature process such as plasma CVD in which the semiconductor substrate is not exposed to a high temperature exceeding 500 ° C. for forming the insulating film 221.

Next, as shown in FIGS. 6A and 6B, a resist pattern 222 corresponding to the wiring connecting the FD 203 and the detection gate electrode 104g is formed on the insulating film 221 by photolithography. Then, by selectively etching the insulating film 221 using the resist pattern 222 as an etching mask, the pattern of the insulating film 221 shown in FIGS. 7A and 7B is formed. For the etching of the insulating film 221, for example, dry etching can be used. In this case, it is preferable to use an unsaturated CF-based gas such as C ₅ F ₈ or C ₄ F ₆ having a high selection ratio with respect to the refractory metal 219 or the silicide 220 as an etching gas.

  Then, as shown in FIGS. 8A and 8B, after removing the resist pattern 222 by ashing or the like, the unreacted refractory metal film 219 is selectively removed using the pattern of the insulating film 221 as an etching mask. As a result, the detection wiring 217 shown in FIGS. 9A and 9B is formed. The removal of the refractory metal film 219 can be performed, for example, by wet etching using a mixed solution of sulfuric acid and hydrogen peroxide as an etching solution.

  As described above, in the present invention, the detection wiring 217 that connects the FD 203 and the detection gate electrode 104g is formed of a refractory metal. According to this configuration, it is possible to form a wiring that connects the FD 203 and the detection gate electrode 104g in a narrower region than a conventional wiring using polysilicon used as a gate electrode.

  That is, the wiring (gate electrode) made of polysilicon is restricted by the layout rule defined based on the processing limit of the CMOS process, as is well known. For example, in a CMOS process corresponding to a 0.18 μm node, a polysilicon wiring has a minimum value of a line width L = 0.18 μm and a space width S between adjacent wirings S = 0.18 μm. For this reason, the minimum width required for newly arranging one polysilicon wiring between the polysilicon wirings arranged substantially in parallel is: space width + line width + space width = 0.18 + 0.18 + 0. 18 = 0.54 μm.

  On the other hand, in the present invention, when the pattern of the detection wiring 217 is formed, first, the resist pattern 222 is formed. Since the resist pattern 222 is an isolated pattern, the layout rule between the polysilicon wirings is not applied, and the space width d (overlapping margin) with the adjacent polysilicon wiring (transfer gate electrode 102g in FIG. 1) is not applied. Only will be constrained by the layout rules. The space width d is about 0.1 μm in the above-described CMOS process corresponding to the 0.18 μm node.

  Therefore, if the processing limit of the wiring made of a refractory metal is about the same as that of the polysilicon wiring (0.18 μm), it is newly made of one refractory metal between the polysilicon wiring and the polysilicon wiring. The minimum width required for arranging the wiring is space width + line width + space width = 0.1 + 0.18 + 0.1 = 0.38 μm.

  As described above, by adopting a wiring made of a refractory metal as a wiring connecting the FD 203 and the detection gate electrode 104g, the wiring is arranged more than the polysilicon wiring conventionally used for the wiring. This makes it possible to reduce the area of the necessary region.

  Note that after the formation of the above-described detection wiring 217 is completed, the second heat treatment is performed, for example, at 780 to 850 ° C. for 10 to 40 sec in an N 2 atmosphere. This heat treatment reduces the resistance of the silicide formed on the FD 203, the power supply diffusion layer 204, the output layer 205, the transfer gate electrode 102g, the reset gate electrode 103g, the detection gate electrode 104g, and the reset line 121.

  After the gate electrode formation step is completed as described above, the first interlayer insulating film 225, the first metal wiring layer, the second interlayer insulating film 226, the second metal wiring layer, and the protective film 227 are formed. The solid-state imaging device is completed by forming. In these steps, processing may be performed using a known CMOS process.

  As described above, according to the present invention, the area necessary for arranging the detection wiring 217 for connecting the floating diffusion 203 and the detection gate electrode 104g can be made smaller than the conventional one. For this reason, the opening area (light receiving area) of the photodiode can be increased, and the detection sensitivity and the saturation output can be improved as compared with the solid-state imaging device employing the conventional wiring arrangement.

  Further, a detection wiring 217 that connects the floating diffusion 203 and the detection gate electrode 104g is formed in the same wiring layer as the gate electrode. For this reason, it is not necessary to provide a wiring for connecting the floating diffusion 203 and the detection gate electrode 104g with a metal wiring formed in the upper layer of the gate electrode layer through the first interlayer insulating film 225. That is, as shown in FIG. 10, in the solid-state imaging device according to the present invention, there is no metal wiring that obstructs the light L incident on the photodiode 101 (charge storage layer 201), and more incident light is transmitted to the photodiode. 201.

  Furthermore, according to the method for manufacturing a solid-state imaging device according to the present invention, the silicide is formed on the semiconductor substrate in the process of forming the silicide formed to obtain electrical contact with the source and drain regions of the transistor. The detection wiring 217 is formed using a refractory metal film. For this reason, it is not necessary to significantly change the manufacturing process of the conventional solid-state imaging device, and the etching mask patterning process made of an insulating film and the etching process of the refractory metal film through the etching mask are added to the conventional processes It is possible to manufacture a solid-state imaging device having the above structure only by adding.

  By the way, when a refractory metal is used as a wiring material, there is a possibility that the wiring resistance becomes high and the electromigration life is reduced. However, in the solid-state imaging device according to the present invention, a refractory metal wiring is used as a wiring for connecting a floating diffusion and a detection gate electrode, in which a current hardly flows in the circuit configuration, and thus a problem occurs. There is no.

  The pattern layout of the pixel cell 100 illustrated in the above embodiment is a specific example, and the present invention is not limited to the above structure. Any layout can be adopted as long as the effects of the present invention can be obtained.

  Moreover, the process used in the said embodiment shows a specific example, and does not restrict | limit the technical scope of this invention. The present invention is characterized in that the floating diffusion and the detection gate electrode are connected by a wiring made of a refractory metal provided in the same wiring layer as the gate electrode. Therefore, even if the process is replaced with a known process equivalent to the process described above, the effects of the present invention can be obtained. Further, the process order is not limited to the order described above, and the process order can be changed as long as the same structure as that of the present invention can be formed.

  Furthermore, although the case where the signal charge is an electron has been described in the above embodiment, the signal charge can be obtained by setting all the conductivity types of the semiconductor substrate and the impurity layer formed in the semiconductor substrate to a reverse conductivity type. Of course, it is possible to construct a solid-state imaging device having holes as holes.

  INDUSTRIAL APPLICABILITY The present invention has an effect of ensuring a photodiode opening area and avoiding interference of incident light in a pixel cell pattern layout, and is useful for a solid-state imaging device.

1 is a plan view showing a layout of pixel cells of a solid-state imaging device according to the present invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the manufacturing process of the solid-state imaging device concerning this invention. Sectional drawing which shows the oblique incident light characteristic to the pixel cell of the solid-state imaging device concerning this invention. 1 is a circuit diagram showing a configuration of a MOS type solid-state imaging device. The top view which shows the layout of the pixel cell of the conventional solid-state imaging device. The top view which shows the layout of the pixel cell of the conventional solid-state imaging device. Sectional drawing which shows the oblique incident light characteristic to the pixel cell of the conventional solid-state imaging device. The top view which shows the other layout of the pixel cell of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Photodiode 102 Transfer transistor 102g Transfer gate electrode 103 Reset transistor 103g Reset gate electrode 104 Amplification transistor 104g Detection gate electrode 121 Reset line 203 Floating diffusion 203a Contact 204 Power supply diffusion layer 211 Detection wiring 217 Detection wiring 218 Silicide block film 219 High Melting point metal film 220 Silicide 221 Insulating film 222 Resist L Incident light

Claims (4)

In a solid-state imaging device in which pixel cells that transfer signal charges generated by photoelectric conversion in a photodiode to a floating diffusion and output a signal corresponding to the potential of the floating diffusion through an amplification transistor are arranged in a matrix ,
A solid-state imaging device, wherein the floating diffusion and the gate electrode of the amplification transistor are connected by a wiring mainly made of a refractory metal provided in the same wiring layer as the gate electrode.   2. The solid-state imaging device according to claim 1, wherein the wiring is connected to the floating diffusion and a gate electrode of the amplification transistor via silicide of the refractory metal.   The solid-state imaging device according to claim 2, wherein the wiring continuously transitions from the refractory metal to the silicide at both ends thereof. In a solid-state imaging device in which signal charges generated by photoelectric conversion in a photodiode are transferred to a floating diffusion, and pixel cells that output a signal corresponding to the potential of the floating diffusion through an amplification transistor are arranged in a matrix. In the manufacturing method,
Forming a conductive film mainly composed of a refractory metal that covers at least a part of the floating diffusion and a part of the gate electrode of the amplification transistor;
Reacting the conductive film with the material of the floating diffusion and the gate electrode of the amplification transistor to form silicide;
Forming an insulating film on the silicide and the unreacted conductive film;
Selectively removing the insulating film, and forming an insulating film pattern corresponding to a wiring connecting the floating diffusion portion and the gate electrode of the amplification transistor;
Selectively removing the conductive film using the insulating film pattern as a mask to form a pattern of the wiring;
A method for manufacturing a solid-state imaging device.

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