JP2006184779A - Inspection circuit and inspection method of thin-film transistor display array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inspection circuit and an inspection method for a thin-film transistor display array. <P>SOLUTION: An inspection circuit and an inspection method of a thin-film transistor display circuit to be used for inspecting the quality of the thin-film transistor array are provided. The inspection circuit comprises an array tester, a test sample base, and a sense amplifier array. The sense amplifier array comprises a plurality of transimpedance amplifiers and a parasitic capacitance discharge circuit. Each sense amplifier has a transimpedance amplifier, comprising an operational amplifier, two switches, and an operation capacitance. The transimpedance amplifier is used to form an integration circuit, and its output is transferred to a sampling/holding circuit, through an output switch and converted into a digital signal by an analog/digital converter. The source parasitic capacitance discharge circuit of the thin film transistor array forms, in this discharge circuit, the discharge path of electric charge of the parasitic capacitance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit inspection method, and more particularly to a method for testing a pixel memory capacity of a thin film transistor display capable of obtaining a reliable and precise pixel quality test result in a state where parasitic capacitance is much larger than the pixel capacity.

  As the pixels of liquid crystal displays (LCD) and organic light-emitting diode display panels (OLED) increase and the area of large-area displays increases, the parasitic capacitance Csp of the source line of the thin film transistor (TFT) array is the pixel (Pixel ) Much larger than memory capacity Cs. Therefore, the inspection signal obtained at the time of quality inspection at the quality control stage is too small and the accuracy is insufficient.

In general, in order to check the quality of a pixel capacitor, first, a voltage of several volts is charged to the pixel capacitor. At the same time, however, the parasitic capacitance of the source line of the thin film transistor is also charged. Can not. “Thin film transistor array inspection method and apparatus” filed by Japan Asia Electronics Co., Ltd., Japanese Patent No. 2931975 (Patent Document 1) and Taiwan Patent Publication No. 473622 (Patent Document 2) is an example of a solution.
Patent No. 2931975 Taiwan Patent Publication No. 473622 (Application No. 88108530)

FIG. 1 shows a test equivalent circuit diagram of a pixel capacity of a known technique. In the figure, Cs is a pixel capacitance, Csp is a TFT array source parasitic capacitance, and Csp >> Cs and ΔCs are standard capacitances whose values are known. S1 is a connection switch between Csp and ΔCs, and S2 is a pixel switch transistor. As shown in FIG. 1A, in the first stage, the pixel capacitor Cs is first charged with the voltage Vp, and then the pixel switch transistor S2 is turned off, and then the parasitic capacitor Csp is charged up to Vs, but Vs ≠ Vp. At this time, the additional capacitor CT that is in parallel with the pixel capacitor Cs at the time of inspection is also charged. At the next inspection, S2 is turned on, and the voltage Va1 of the parallel capacitance Cs‖Csp‖CT is measured. The difference ΔVs between this value and Vs is very small, ΔVs1 = Va1−Vs = Cs / CT * (Vp−Vs), and Va1, Vs, CT and Vp are already known, so the value of Cs is obtained. be able to. However, since the error is large, a second stage inspection must be performed as shown in FIG. When charging Csp, S1 is turned on, charging to ΔCs with Vs, and simultaneously charging Csp‖ΔCs‖CT. Here, ΔCs is a standard capacity whose value is known. Finally, S2 is turned on, voltage Va2 of Cs‖ΔCsp‖Cs‖CT is measured, and ΔVs2 = Va2-Vs = Cs / CT * (Vp−Vs) Further, based on ΔVs1 and ΔVs2, the value of Cs is obtained as in the following equation.
(Equation 1)
Cs = ΔCs * ΔVs1 * ΔVs2 / {(Vp−Vs) * (ΔVs1−ΔVs2)}

This method requires two-stage measurement, takes time, has a weak signal, has low reliability, and has poor accuracy. It cannot meet the demand of industry.
If a stronger signal can be obtained when measuring a minute pixel capacity, accuracy and reliability can be improved, and a result can be obtained by one measurement for each pixel. This saves time and effort.

  The present invention provides an inspection circuit and method for a thin film transistor display array, and in the inspection of a small pixel capacitance, the parasitic capacitance is transferred by a method of charge transfer in parallel with a huge parasitic capacitance of a source line of the thin film transistor array. It is an object to improve accuracy and reliability by obtaining a strong signal.

  The present invention provides an inspection circuit and method for a thin film transistor display array, and is capable of obtaining accurate results with a single measurement for each pixel, thereby saving time and labor. To do.

  In order to solve the above-mentioned problems and improve the drawbacks of the known technology, the invention of claim 1 is used to provide a power supply, wherein the inspection circuit of the thin film transistor display array is used to check the quality of the thin film transistor array and includes at least an array tester. Inspect the signal waveform, analyze and save the obtained results, provide the sample base, place the thin film transistor array, provide the control signal and sense amplifier control signal by the array tester, provide the sense amplifier array, the thin film transistor array The sense amplifier array is composed of a plurality of transimpedance amplifiers and a parasitic capacitance discharge circuit, and each sense amplifier has a transimpedance. An amplifier is provided, which is connected to a discharge circuit, two switches, Composed of a single capacitor, the operating capacitor feeds back the output to the negative input terminal of the amplifier, and a switch is connected to the negative input terminal and the output terminal of the operational amplifier so that the operating capacitor can be short-circuited and discharged. The two switches open and close the input end to determine whether or not to connect to the pixel memory capacity of the thin film transistor array. This transimpedance amplifier is used to form an integration circuit, and its output passes through the output switch to the sample / hold circuit. Transmitted and converted into a digital signal by an analog / digital converter, comprising a source line parasitic capacitance discharge circuit of a thin film transistor array, and composed of an amplifier circuit, two switches, and an operation capacitor, and the operation capacitor outputs the output of the amplifier. Feedback is provided to the negative input terminal, and the switch is connected to the negative input terminal and the output terminal of the operational amplifier. The other switch opens and closes the input terminal, determines whether to connect to the source line parasitic capacitance of the thin film transistor array, and connects the load resistance from the output of the operational amplifier to the ground. This is a test circuit for a thin film transistor display array in which a discharge circuit for charge of parasitic capacitance is formed by this discharge circuit.

According to a second aspect of the present invention, there is provided an inspection circuit for a thin film transistor display array according to the first aspect, wherein the thin film transistor array is a liquid crystal display panel (LCD).
A third aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein the thin film transistor array is an organic light emitting diode display panel (OLED).
According to a fourth aspect of the present invention, there is provided the inspection circuit for the thin film transistor display array according to the first aspect, wherein the thin film transistor array is a reflective liquid crystal on silicon (LCOS) panel.
A fifth aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein the thin film transistor is an amorphous silicon thin film transistor.
A sixth aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein the thin film transistor is a polycrystalline silicon thin film transistor.
A seventh aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein the thin film transistor is a recrystallized silicon thin film transistor.
The invention according to claim 8 is the inspection circuit for the thin film transistor display array according to claim 1, wherein the discharge circuit is an operational amplifier.
A ninth aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein the plurality of switches are controlled by a programmable output waveform of the array tester.
A tenth aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein an operation capacitance value of the transimpedance amplifier is 1 pF to 100 pF.
An eleventh aspect of the present invention is the inspection circuit for a thin film transistor display array according to the first aspect, wherein an operating capacity of the parasitic capacitance discharge circuit is larger than 10 pF.

  According to a twelfth aspect of the present invention, there is provided a method for inspecting an ineffective pixel (invisible region) of a thin film transistor display array, wherein at least the test pixel memory capacity of the nth row in the array is charged to the voltage Vs, Close the sense amplifier and discharge circuit short switch, discharge the operating capacity of the sense amplifier and discharge circuit, close the discharge circuit input switch, open the short switch, discharge the parasitic capacitance of the thin film transistor array through the discharge circuit , Transfer the charge, the transition time is long, close the sense amplifier input switch, activate the sense amplifier, integrate the current of the pixel memory capacity of the nth row and kth column, but do not output the result, Ineffective picture of a thin film transistor display array, in which a pixel (nth row, k + 1 column) is inspected and includes the above steps This is an inspection method for an element (invisible region).

  According to a thirteenth aspect of the invention, in the effective pixel (visible region) inspection method of the thin film transistor display array, at least the test pixel memory capacity of the nth row in the array is charged to the voltage Vs, and the pixel transistor is opened after the charging is completed. Close the sense amplifier and discharge circuit short switch, discharge the operating capacity of the sense amplifier and discharge circuit, close the sense amplifier input switch, activate the sense amplifier circuit, the pixel memory capacity of the nth row and kth column Integrates current, obtains integrated voltage Vd, closes output switch, activates sample / hold circuit, samples / holds integrated voltage, converts to analog signal via analog / digital converter, and transmits to tester The results can be analyzed and calculated, the discharge circuit input switch is closed, the short switch is opened, and the thin film transistor The parasitic capacitance of the data array is discharged through the discharge circuit to transfer the charge, so that the transfer time can be shortened and the efficiency can be increased so that the next pixel (the nth row and the second row) can be improved. This is a method for inspecting effective pixels (visible region) of a thin film transistor display array that includes the above steps.

The invention according to claim 14 is the method of inspecting invalid pixels (invisible regions) of the thin film transistor display array according to claim 12, wherein the charging voltage Vs of the pixel capacitance is 2 to 10 volts, or claim 13 This is an inspection method of effective pixels (visible region) of a thin film transistor display array.
A fifteenth aspect of the invention is a method for inspecting an effective pixel (visible region) of a thin film transistor display array according to the thirteenth aspect, wherein the integrated voltage Vd is set to be larger than 100 mV.

  In other words, the present invention firstly provides an inspection circuit for a thin film transistor display circuit, and is used for inspecting the quality of a thin film transistor array. Including at least: An array tester is provided to supply power, inspect the signal waveform, and analyze, calculate, and store the results. A sample pedestal is provided, a thin film transistor array is placed, and a control signal and a sense amplifier control signal are provided from the array tester. A sense amplifier array is provided, which is used to integrate the parasitic capacitance transition (discharge) of the source line of the thin film transistor array and the charge current of the pixel memory capacitance. The sense amplifier array includes a plurality of transimpedance amplifier units and a parasitic capacitance discharge circuit. Each sense amplifier includes a transimpedance amplifier, which includes an operational amplifier circuit and two switches. Composition with one operating capacity. This operating capacity feeds back the output to the negative input terminal of the operational amplifier, and one switch is connected to the negative input terminal and the output terminal of the operational amplifier, and is used for short-circuiting the operating capacity and discharging. The other switch opens and closes the input end and determines whether to connect to the pixel memory capacity of the thin film transistor array. This transimpedance amplifier is used to form an integration circuit, and its output is transmitted to a sample / hold circuit via an output switch, and converted to a digital signal via an analog / digital converter. The source line parasitic capacitance discharge circuit of the thin film transistor array is composed of an operational amplifier, two switches, and an operating capacitance. This operating capacity feeds back the output to the negative input terminal of the operational amplifier, and one switch is connected to the negative input terminal and the output terminal of the operational amplifier so that the operating capacity can be shorted and discharged. The other switch opens and closes the input terminal to determine whether or not to connect to the source line parasitic capacitance of the thin film transistor array, and connects the amplifier output to the ground with a load resistor. This discharge circuit discharges the parasitic capacitance. Used for path formation.

  Secondly, the present invention provides a method for inspecting invalid pixels (invisible regions) of a thin film transistor array, and includes at least the following steps. The test pixel memory capacity of the nth row in the array is charged to the voltage Vs, and the pixel transistor is opened after the charging is completed. Close the short switch of the sense amplifier and the discharge circuit, and discharge the operating capacity of the sense amplifier and the discharge circuit. The discharge circuit input switch is closed, the short switch is opened, the parasitic capacitance of the thin film transistor array is discharged through the discharge circuit, the charge is transferred, and the transfer time is lengthened. The transimpedance amplifier input switch is closed and the sense amplifier circuit is activated to integrate the current in the pixel memory capacity of the nth row and kth column, but the result is not output. Then, the next pixel (the nth row, the (k + 1) th column) is inspected.

  Thirdly, the present invention provides a method for inspecting an effective pixel (visible region) of a thin film transistor array, and includes at least the following steps. The test pixel memory capacity of the nth row in the array is charged to the voltage Vs, and the pixel transistor is opened after the charging is completed. Close the short switch of the sense amplifier and the discharge circuit, and discharge the operating capacity of the sense amplifier and the discharge circuit. The sense amplifier input switch is closed and the sense amplifier circuit is activated to integrate the current of the pixel memory capacity of the nth row and the kth column to obtain an integrated voltage Vd. The output switch is closed, the sample / hold circuit is started, the integrated voltage is sampled / held, converted to a digital signal through an analog / digital converter, and transmitted to a tester, so that the result can be analyzed and calculated. Close the discharge circuit input switch and open the short switch to discharge the parasitic capacitance of the thin film transistor array from the discharge circuit, transfer the charge, shorten the transition time and make the efficiency convenient for the next pixel inspection. increase. Then, the next pixel (the nth row, the k + 1th column) is inspected.

  The inspection circuit and method of the thin film transistor display array according to the present invention allows the parasitic capacitance to be discharged and transferred by the charge transfer method in parallel with the enormous parasitic capacitance of the source line of the thin film transistor array when inspecting the pixel capacitance with a small numerical value. By obtaining a strong signal, accuracy and reliability can be improved. Also, accurate results can be obtained with a single measurement for each pixel, saving time and effort.

The content of the present invention will be described with reference to the following examples and figures.
As shown in FIG. 2, it is a connection schematic diagram of a test circuit 200 of a display circuit of a low temperature poly-Si thin film transistor array according to an embodiment of the present invention. The row switch transistor 202 is also referred to as a read / write switch transistor, and is controlled by the row switch transistor gate control circuit 220 to close (ON) or open (OFF) the gate, and from the source or drain by the DC charging power source 214 or the inspection circuit. Connect to that row, for example, the nth row (n = 1 to N, N is the total number of rows), and the gate of the pixel switch transistor 204 is the kth column (k = 1 to K, K is the total number of columns). Connected to the column control gate electrode 216, the source of the pixel switch transistor 204 is connected to the drain of the row switch transistor 202, the drain of the pixel switch transistor 204 is connected to the positive electrode of the pixel capacitor 206, and the negative electrode of the pixel capacitor is the common of the array Connect to the terminal (Cs on Common) or connect to the gate control terminal (Cs on Gate) of the (k + 1) th row. All the sources of the row switch transistor 202 and the pixel switch transistor 204 have a source line parasitic capacitance Csp 208, whose value is much larger than the pixel capacitance Cs 206 (Csp >> Cs), and their charge and discharge time constants are very large. The source of the first row switch transistor 202 is connected to the switch 210, and this switch is connected to the DC charging power source 214 upward and to the sense array 212 downward. The gate of the first row switch transistor 202 is connected to the row switch control circuit 220. The sense array 212 is one of the features of the present invention and will be described in detail with reference to FIG. The output of the sense array 212 is connected to a sample / hold circuit of an analog / digital converter (A / D converter, ADC) 218, and a test signal is transmitted to a tester.

  FIG. 3 is a connection diagram 300 of a tester and a sample (Device Under Test, DUT) according to the embodiment of the present invention. An array tester 302 includes a programmable voltage generator 304, a waveform generator 306, a precision measurement unit 308, a pixel processor 310, and a central processing unit. A face circuit (CPU / interface) 312 is provided. The drive signal 316 generated by the programmable voltage generator supplies a voltage required by the sample 314, for example, a charge voltage, a transistor drive voltage, or the like. The sample 314 can be a liquid crystal display panel (LCD), an organic light emitting diode display panel (OLED), or a reflective liquid crystal (LCOS) panel, and the transistor can be, for example, an amorphous silicon thin film transistor or a polycrystalline thin film transistor. Alternatively, a recrystallized silicon thin film transistor or the like may be used. The waveform generator 306 generates a necessary sense amplifier control signal (Sense Amp Control Signal) 318 to control the inspection operation of the sense amplifier (Sens Amp) 326, and is connected to the pixel transistor by the switch 210 (see FIG. 2). The signal is transmitted to the sense amplifier 326 of the sense array 212 via the conductor 322, and the detected signal is transmitted to the analog / digital converter 324 via a sampling / hold circuit (not shown), and the digital signal. Then, the data is transmitted from the data line 320 to the pixel processor 310 for analysis, and the CPU 312 calculates the inspection result and creates a report or chart so that the inspector can read the inspection result. The circuit connection in FIG. 3 is not significantly different from the prior art, only the structure of the sense amplifier is different and the inspection method is different.

  FIG. 4 shows a circuit configuration of the sense amplifier 400 according to the embodiment of the present invention. A plurality of sense amplifiers 400 constitute one sense array 212. Each sense amplifier includes a transimpedance amplifier 404, a parasitic capacitance discharge circuit 402, an analog / digital converter 410, and switches SW1, SW2, SW3, SW4, and SW5. With The parasitic capacitance discharge circuit is an integrator, and includes an operational amplifier 406, an operation capacitor Cd412, SW1, and a load resistor 416. The value of the operating capacitance Cd412 is greater than 10 pF. Connect the input to the negative input terminal of the operational amplifier 406 via SW2, ground the positive input terminal, connect the negative input terminal to the output terminal with SW1 and Cd, and connect one load resistor 416 to the output terminal. Ground. Cd can be discharged when SW1 is on. When SW1 is off and SW2 is on, the charge of the parasitic capacitance connected to the input terminal (I / P) can be transferred, that is, the parasitic capacitance can be discharged. The transimpedance amplifier 404 is an integrator and includes an operational amplifier 408, an operation capacitor Cint 414, and SW3. The value of the operation capacitor Cint 414 is approximately 1 pF to 100 pF. The input is connected to the negative input terminal of the operational amplifier 408 via SW4, the positive input terminal is grounded, the negative input terminal is connected to the output terminal from SW3 and Cint, and the output terminal is connected to the analog / sample circuit with the sample / hold circuit from SW5. Connected to digital converter 410, the output (O / P) of the analog / digital converter provides a signal to the pixel processor. When SW3 is on, Cint capacity can be discharged, and when SW3 is off, SW4 and SW5 are on, the charge current on the pixel memory capacity can be integrated, transmitted to the analog / digital converter via the sample / hold circuit, and converted to a digital signal To do.

FIG. 5 is a control waveform diagram necessary for inspecting one pixel by controlling SW1 to SW5 in the circuit shown in FIG. 5A shows an inspection control waveform for an invalid pixel (invisible region), FIG. 5B shows an inspection control waveform for an effective pixel (visible region), and the mechanism will be described below.
FIG. 6 is a flowchart of the inspection for invalid pixels (invisible regions) in the embodiment of the present invention described above. First, in step 602, as shown in FIG. 2, the switch transistors in the n-th row are turned on, all the pixel transistors are turned on, the switch 210 is connected to a DC charging power source, and the pixel memory capacity in the n-th row is charged. When is completed, all the pixel transistors are turned off. Subsequently, the switch 210 is connected to one sense amplifier 400 (shown in FIG. 4) in the sense array 212. Returning to FIG. 6, in step 604, it is assumed that the inspection has been performed up to the n-th row and the k-th column, and in step 606, the inspection control waveform in FIG. 5A is in the T1 period, and at this time, SW1 and SW3 are turned on. As shown in FIG. 4, the TFT array source line parasitic capacitance Csp, the discharge circuit 402, and the sense amplifier operating capacitances Cd and Cint are reset (ie, discharged). In step 608, SW2 is turned on and SW1 is turned off in the period T2 in FIG. 5, and the current of Csp is discharged from the Csp discharge circuit 402, that is, the charge is transferred. The inspection must pass through this pixel. Therefore, at this opportunity, the discharge time of Csp is increased (that is, the SW2 ON time is increased), and the parasitic capacitance Csp is discharged for a sufficient time. In step 610, SW4 is turned on also within the period T2, and at this time, the transimpedance amplifier 404 is activated and the pixel transistor is turned on to integrate the current on the pixel memory capacitor Cs. This operation time overlaps with the Csp discharge time (see the control waveform in FIG. 5), and this step can be omitted if there is no need to measure invalid pixels. In step 612, the pixel in the nth row and the (k + 1) th column is inspected.

FIG. 7 is a flowchart of inspection for valid pixels (valid pixels) in the embodiment of the present invention described above. Steps 702 and 704 are the same as steps 602 and 604. In step 706, the inspection control waveform of FIG. 5B is in the T1 period, and at this time, SW1 and SW3 are turned on. As shown in FIG. 4, the TFT array source line parasitic capacitance Csp, the discharge circuit 402, and the operation of the sense amplifier are performed. The capacitors Cd and Cint are reset (ie, discharged). In step 708 and the period T2 in FIG. 5, SW4 is turned on, the sense amplifier is activated, and the pixel transistor 204 in the nth row and kth column is turned on at this time, as shown in FIG. Integrates the current formed by the charge. The integrated voltage Vd is greater than 100 mV. This signal voltage is several hundred times larger than the signal voltage obtained by the prior art, and the system and reliability can be improved. Accurate results can be obtained with a single inspection for each pixel, saving time and effort. In step 710, within the period T3 in FIG. 5, SW5 is turned on, the sample / hold circuit is started, the integrated voltage is sent to the analog / digital / converter and output as a digital signal, and the pixel processor 310 can process it. To. In step 712, SW2 is turned on and SW1 is turned off within the period T4 in FIG. 5, and charge transfer (that is, discharge of Csp) is performed. The purpose of this step is to perform a small amount of charge on the source line of the nth row at the same time as the pixel memory capacity is discharged to the sense amplifier when performing the inspection, and as the kth column increases, Since the charges of the parasitic capacitances in n rows are accumulated, this phenomenon is improved in this step so as not to affect the accuracy of the inspection. This discharge cycle is shorter than the discharge cycle of the invalid pixels, thereby shortening the inspection time and improving the inspection efficiency. Step 712 is preparation for inspection of the next pixel (nth row, k + 1th column). Since the transfer has been completed, step 714 can be immediately entered and the next pixel can be examined.
That is, according to the inspection circuit and method of the thin film transistor display array of the embodiment of the present invention described above, in the inspection of the pixel capacitance having a small numerical value, the charge transfer is performed in parallel with the huge parasitic capacitance of the source line of the thin film transistor array. By discharging and transferring the parasitic capacitance by the method and obtaining a strong signal, accuracy and reliability can be improved, and an accurate result can be obtained by one measurement for each pixel.

It is a test | inspection equivalent circuit schematic of the pixel capacity | capacitance of a well-known technique. 4 is a connection schematic diagram of a test circuit of a display circuit of a low temperature poly-Si thin film transistor array according to an embodiment of the present invention. It is the connection diagram 300 of the tester and sample (Device Under Test, DUT) of the Example of this invention. It is a circuit block diagram of the sense amplifier 400 of the Example of this invention. FIG. 5 is a control waveform diagram necessary for controlling one of SW1 to SW5 and inspecting one pixel. It is a test | inspection flowchart with respect to the invalid pixel (invisible area) of the Example of this invention. It is a test | inspection flowchart with respect to the valid pixel (visible region) of the Example of this invention.

Explanation of symbols

200 inspection circuit 202 row switch transistor 204 pixel switch transistor 206 pixel capacitance 208 source line parasitic capacitance Csp
210 Switch 212 Sense Array 214 DC Charging Power Supply 216 Column Control Gate Circuit 218 Analog / Digital Converter 220 Row Switch Control Circuit 300 Connection between Tester and Sample (DUT) 302 Array Tester 304 Programmable Voltage Generator 306 Waveform Generator 308 Precision Inspection Unit 310 Pixel processor 312 Central processing unit and interface circuit 314 Sample 316 Drive signal 318 Sense amplifier control signal 320 Data line 322 Conductor 324 Analog / digital converter 326 Sense amplifier 400 Sense amplifier 402 Parasitic capacitance discharge circuit 404 Transimpedance amplifier 406 Operational amplifier 408 operational amplifier 410 analog / digital converter 412 operation capacity 414 operation capacity 416 load resistance 602-714 step

Claims (15)

The inspection circuit of the thin film transistor display array is used to check the quality of the thin film transistor array.
It is equipped with an array tester, used to provide power, inspects the signal waveform, saves the results obtained by analysis calculation,
Provide the sample base, place the thin film transistor array, provide the control signal and sense amplifier control signal by the array tester,
Comprising a sense amplifier array, used to transfer or discharge the source electrode parasitic capacitance of the thin film transistor array, and to integrate the charge current of the pixel memory capacitance;
The sense amplifier array is composed of a plurality of transimpedance amplifiers and a parasitic capacitance discharge circuit.
A transimpedance amplifier is provided, which is composed of a discharge circuit, two switches, and an operating capacitor. The operating capacitor feeds back an output to the negative input terminal of the amplifier, and the switch is connected to the negative input terminal and the output terminal of the operational amplifier. The switch is connected to enable short-circuiting of the operation capacitor so that the discharge can be performed. Another switch opens and closes the input terminal to determine whether to connect to the pixel memory capacitor of the thin film transistor array. Used for circuit formation, the output is transmitted to the sample / hold circuit via the output switch, converted into a digital signal by the analog / digital converter,
It comprises a source line parasitic capacitance discharge circuit of a thin film transistor array, and is composed of an amplifier circuit, two switches, and one operation capacitor, the operation capacitor feeds back an output to the negative input terminal of the amplifier, and the switch is a negative input terminal of the operational amplifier. Connected to the output terminal, the operating capacitor is short-circuited so that the discharge can be performed, and another switch opens and closes the input terminal to determine whether to connect to the source line parasitic capacitor of the thin film transistor array, and to load A test circuit for a thin film transistor display array, wherein a resistor is connected from an output of an operational amplifier to a ground, and a discharge circuit for a charge of parasitic capacitance is formed by this discharge circuit.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the thin film transistor array is a liquid crystal display panel (LCD).   2. The inspection circuit for a thin film transistor array according to claim 1, wherein the thin film transistor array is an organic light emitting diode display panel (OLED).   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the thin film transistor array is a liquid crystal on silicon (LCOS) panel.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the thin film transistor is an amorphous silicon thin film transistor.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the thin film transistor is a polycrystalline silicon thin film transistor.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the thin film transistor is a recrystallized silicon thin film transistor.   2. The inspection circuit of a thin film transistor array according to claim 1, wherein the discharge circuit is an operational amplifier.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein the plurality of switches are controlled by a programmable output waveform of the array tester.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein an operation capacitance value of the transimpedance amplifier is 1 pF to 100 pF.   2. The inspection circuit for a thin film transistor display array according to claim 1, wherein an operating capacity of the parasitic capacitance discharge circuit is larger than 10 pF. The inspection method of the invalid pixel (invisible region) of the thin film transistor display array is at least:
Charge the test pixel memory capacity of the nth row in the array to the voltage Vs, open the pixel transistor after the completion of charging,
Close the short switch of the sense amplifier and the discharge circuit, discharge the operating capacity of the sense amplifier and the discharge circuit,
Close the discharge circuit input switch, open the short switch, discharge the parasitic capacitance of the thin film transistor array through the discharge circuit, transfer the charge, the transfer time is long,
Close the sense amplifier input switch, activate the sense amplifier, integrate the current of the pixel memory capacity of the nth row and kth column, but do not output the result,
Inspect next pixel (nth row, k + 1th column)
A method for inspecting invalid pixels (invisible regions) of a thin film transistor display array, comprising the above steps. The inspection method of the effective pixel (visible region) of the thin film transistor display array is at least:
Charge the test pixel memory capacity of the nth row in the array to the voltage Vs, open the pixel transistor after the completion of charging,
Close the short switch of the sense amplifier and the discharge circuit, discharge the operating capacity of the sense amplifier and the discharge circuit,
Close the sense amplifier input switch, activate the sense amplifier circuit and integrate the current of the pixel memory capacity of the nth row and kth column to obtain the integrated voltage Vd,
Close the output switch, start the sample / hold circuit, sample / hold the integration voltage, convert it to a digital signal via an analog / digital converter, and send it to a tester to analyze and calculate the result,
Close the discharge circuit input switch, open the short switch, discharge the parasitic capacitance of the thin film transistor array through the discharge circuit, transfer the charge, and shorten the transition time, so that it is convenient for the next pixel inspection, efficiency Can be raised,
Inspect next pixel (nth row, k + 1th column)
A method for inspecting an effective pixel (visible region) of a thin film transistor display array, comprising the above steps.   14. The method of inspecting invalid pixels (invisible regions) of a thin film transistor display array according to claim 12, or the thin film transistor display according to claim 13, wherein the charging voltage Vs of the pixel capacitance is 2 to 10 volts. Inspection method of effective pixel (visible region) of array.   14. The method for inspecting an effective pixel (visible region) of a thin film transistor display array according to claim 13, wherein the integrated voltage Vd is set to be larger than 100 mV.

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