JP2006181980A - Exposure head and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an exposure head which has organic EL elements and has a greatly small area. <P>SOLUTION: The exposure head is equipped with a substrate with a predetermined region, a plurality of the organic EL elements set in a staggering manner in the predetermined region, a plurality of driving circuits which are disposed among the plurality of organic EL elements in the predetermined region and make the plurality of organic EL elements emit light, and shift registers which are arranged correspondingly to the plurality of driving circuits in the periphery of the predetermined region and transmit emission data for making the organic EL elements emit light to the plurality of driving circuits. The predetermined region is provided in a strip form. The shift register is preferred to be set nearly in parallel to a longitudinal direction of the predetermined region. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an exposure head and an image forming apparatus. In particular, the present invention relates to an exposure head having an organic EL element and an image forming apparatus provided with the exposure head.

A conventional exposure head is disclosed in Japanese Patent Application Laid-Open No. 2004-50816 (Patent Document 1). For example, as shown in FIG. 11, the conventional exposure head disclosed in Patent Document 1 includes an organic EL array mounted on a long substrate such as glass, and a drive circuit connected to the organic EL array to control light emission of the organic EL. And.
JP 2004-50816 A

  However, the conventional exposure head has a problem that the width of the exposure head is large and the image forming apparatus becomes large.

  Accordingly, an object of the present invention is to provide an exposure head and an image forming apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  To achieve the above object, according to the first aspect of the present invention, a substrate having a predetermined region, a plurality of organic EL elements arranged in a staggered manner in the predetermined region, and a plurality of organic EL elements in the predetermined region A plurality of drive circuits that are arranged between the organic EL elements and emit light from the plurality of organic EL elements, and light emission data that is arranged corresponding to the plurality of drive circuits around a predetermined region and emits light from the organic EL elements. An exposure head comprising a shift register for transferring to the plurality of drive circuits is provided.

  In the above configuration, both the drive circuit for driving the organic EL element and the shift register are arranged on the same substrate as the organic EL element. And since a drive circuit is arrange | positioned between organic EL elements in the area | region where an organic EL element is arrange | positioned, it is not necessary to arrange | position a drive circuit around the said area | region. Therefore, according to the above configuration, an exposure head having an extremely small element area can be provided.

  In the exposure head, the predetermined region is preferably provided in a strip shape, and the shift register is preferably disposed substantially parallel to the longitudinal direction of the predetermined region.

  According to the above configuration, when the exposure head (substrate) is formed in a long shape, the number of elements arranged around the region where the organic EL element is provided can be significantly reduced in the width direction of the substrate. . Therefore, according to the above configuration, it is possible to provide an exposure head having a narrower width direction of the substrate.

  The exposure head is preferably provided between a plurality of organic EL elements and a plurality of drive circuits, and further includes a plurality of wirings connecting the plurality of drive circuits and the shift register.

  According to the above configuration, since it is not necessary to provide a region for arranging the wiring connecting the shift register and the drive circuit, an exposure head with a smaller area can be provided.

  According to a second aspect of the present invention, there is provided an image forming apparatus comprising the exposure head.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

<Overall configuration of exposure head>
FIG. 1 is a plan view of an entire exposure head according to an embodiment as viewed from above. An exposure head 1 shown in FIG. 1 is used to form a latent image by exposing a photosensitive member in an image forming apparatus such as a printer or a copying machine. The overall length of the exposure head 1 is slightly longer than the printing width in the main scanning direction. Since the actual sectional size of the exposure head 1 is extremely small, it cannot be fully expressed in FIG. Therefore, hereinafter, for convenience of explanation, details will be described using an enlarged view or the like as appropriate. Further, the exposure head 1 is provided with a connector 2 on one end side, and is connected to an image data transmission unit (described later) on the printer controller side via the connector 2. Further, the exposure head 1 is provided with a timing control IC 69 in the vicinity of the connector 2.

  FIG. 2 is a partial enlarged view of a portion A shown in FIG. 1 of the exposure head 1. 3 is a cross-sectional view taken along the line II of FIG. As shown in each drawing, the exposure head 1 includes a support frame 3, a condenser lens array 4, and a light emitting element array 8. As shown in FIG. 3, the exposure head 1 has a condensing lens array 4 disposed on one side of the light emitting element array 8 and a hygroscopic agent 31 laminated on the other side. The exposure head 1 has a structure in which the whole is accommodated in the support frame 3.

  The light emitting element array 8 includes a light emitting element group including a plurality of light emitting elements, a drive circuit that drives the light emitting element group, and a control circuit that controls the drive circuit on a glass substrate. In this embodiment, an organic electroluminescence (EL) element is employed as the light emitting element. The light emitting element groups are arranged in a staggered manner in the number of pixels in the main scanning direction of the exposure head 1 and in the sub scanning direction.

  The condensing lens array 4 is disposed on the upper side of the light emitting element array 8 and includes a condensing lens group that condenses the light emitted from the individual light emitting elements.

  The timing control IC 69 (see FIG. 1) includes a drive circuit that controls / drives a predetermined block of light emitting element groups arranged in a staggered pattern in the main scanning direction and the sub scanning direction of the exposure head 1. . In the exposure head 1 of the present embodiment, a plurality of control circuits are provided along the main scanning direction of the exposure head, and a timing control IC 69 disposed at the end of the exposure head 1 supplies image data to the control circuit 56. To do.

  FIG. 4 is a partial enlarged view of a portion B shown in FIG. 2 of the exposure head 1 and shows a detailed configuration of the condenser lens array 4. The condensing lens array 4 is mainly composed of a glass substrate or the like, and has a structure in which the condensing lens 13 is embedded in each through hole (light hole) 27 provided in the glass substrate. These condensing lenses 13 are condensing lenses 13 in which a predetermined number of condensing lenses 13 are arranged in the main scanning direction, and such a row is arranged in eight rows in the sub-scanning direction. An optical lens group is configured. Adjacent rows of the condenser lenses are shifted by half (half pitch) of the arrangement interval of the condenser lenses 13, so that the condenser lens groups are arranged in a staggered manner as a whole.

  Further, the light emitting element group of the light emitting element array 8 described above is formed in one-to-one correspondence with the arrangement of the condenser lens group of the condenser lens array 4. The arrangement of the light emitting element groups is substantially the same as the arrangement of the condenser lens groups shown in FIG. In this example, 7680 through holes 27 and light emitting elements are formed in the main scanning direction. Out of these 7680, odd-numbered through holes 27 and light emitting elements are arranged in the first column in the sub-scanning direction, and even-numbered through holes 27 and light emitting elements are arranged in the second column in the sub-scanning direction. In the same manner, a total of 8 rows of 7680 × 4 through holes 27 and light emitting portions are formed. The light emitted from each light emitting element of the light emitting element array 8 passes through the above-described through holes 27 and reaches each condenser lens 13, and is condensed by each condenser lens 13 and emitted to the outside of the exposure head 1. Is done.

  FIG. 5 is a diagram illustrating the arrangement state of the condenser lens array 4 in more detail. FIG. 6 is a view for explaining a state when the photosensitive member is exposed by the exposure head in the arrangement state shown in FIG. As described above, each condenser lens 13 is press-fitted into the through-hole 27, and the light emitting portion of each light emitting element of the light emitting element array 8 is disposed immediately below each condenser lens 13. For example, if the resolution in the main axis direction (main scanning direction) of the exposure head 1 is 600 dpi, the pitch A of the light emitting portions of each light emitting element is 1/600 inch, and the pitch of the light emitting portions on the same line in the main axis direction is 2A. (= 1/300 inch). When the light emission shift speed in the sub-axis direction (sub-scanning direction) matches the paper feed speed, the light emitting portion pitch B is B = A. The light emitting element array 8 of the present embodiment is configured as described above, and the light emitting portions of the respective light emitting elements are arranged in a plurality of rows in a staggered manner in the sub-axis direction. FIG. 6 shows a state in which the photoconductor is exposed at a pitch (A = B) of 600 dpi in each of the main axis direction and the sub-axis direction by the exposure head 1 in such an arrangement state.

  FIG. 7 is a diagram for explaining the light emitting element array 8 in more detail. 8 is a cross-sectional view in the II direction shown in FIG. As shown in FIG. 7, the light emitting element array 8 includes a light emitting unit 25, a control circuit 56, and a wiring group 95 on the glass substrate 60.

  The light emitting unit 25 is disposed in a strip shape at a substantially central portion in the width direction of the glass substrate 60. The control circuit 56 is arranged along the longitudinal direction of the glass substrate 60 on both sides of the light emitting unit 25 arranged in a strip shape. Further, the wiring group 95 is disposed along the longitudinal direction of the glass substrate 60 on both sides of the control circuit 56. Moreover, as shown in FIG. 8, the sealing agent 24 is provided so that the light emission part 25, the control circuit 56, and the wiring group 95 which were provided on the glass substrate 60 may be covered.

  FIG. 9 is an enlarged view of the light emitting unit 25. The light emitting unit 25 includes a plurality of organic EL elements 79 arranged in a staggered manner, and a plurality of drive circuits 78 arranged between the organic EL elements 79. That is, in the present embodiment, the plurality of drive circuits 78 are arranged in a staggered manner, and are connected to the scanning lines and the capacitor lines arranged between the organic EL elements 79 and the drive circuit 78. A detailed configuration of the light emitting unit 25 will be described later with reference to FIGS.

<Configuration of exposure control circuit>
FIG. 10 is a block diagram illustrating a configuration example of an exposure control circuit centering on a path of image data inside the image forming apparatus, and illustrates an exposure control circuit in a tandem printer. Based on FIG. 10, the function of each unit will be described while following the flow of image data.

  The image data of CMYK (C: cyan, M: magenta, Y: yellow, K: black) subjected to image processing by the printer controller 64 is subjected to parallel / serial conversion by the image data transmission unit 65, and each CMYK LS ( LVDS SARDES) signal 66. The CMYK LS signals 66 are sent to the CMYK exposure heads 1a, 1b, 1c, and 1d in the head control unit 68 on the printer engine side. Each exposure head 1a and the like includes a timing control IC 69 and a control circuit 56 connected in a daisy chain. Image data for one line in the main scanning direction is divided and received by each control circuit 56, serial / parallel converted, and sequentially held in a shift register in each control circuit 56. Thereafter, in synchronization with the printing operation of the printer mechanism, each light emitting element of the light emitting element array 8 is ON / OFF controlled in accordance with the gradation value of the image data.

  The mechanical controller 91 is connected to a signal line SIO included in the differential signal wiring 66, and performs command / status communication with the printer controller 64 via the signal line SIO. The mechanical controller 91 supplies a register clear signal (RCLR) and a timing control clock signal (TCCLK), which will be described later with reference to FIGS. 11 and 12, to each of the exposure heads 1a to 1d. Control energization.

  FIG. 11 is a block diagram showing a configuration of the light emitting element array 8 included in the exposure heads 1a to 1d. The exposure head 1 includes a control circuit 56 and a light emitting unit 25 formed on a glass substrate 60, and a timing control IC 69 bump-bonded to the glass substrate 60. The data control line 57 is connected to the input of the timing control IC 69 and receives one-line print data sent from the printer controller 64 (see FIG. 10) as a SERDES signal. The timing control IC 69 converts the received serial data into parallel data, and supplies it to the control circuits 56 via the light emission time data lines 85 as print data divided for the control circuits 56.

  The timing control IC 69 is connected to the control circuit 56 via shift register control lines 80 and 81, a register select signal line 82, and a count data output line 83, and controls each component. This will be described later with reference to FIG.

  The power supply line 58 is connected to the control circuit 56 and the light emitting unit 25 arranged in a predetermined number in the main scanning direction on the glass substrate 60, and supplies power to the control circuit 56 and the light emitting unit 25.

  FIG. 12 is a diagram for explaining in detail the circuit configuration of the light emitting element array 8 included in each of the exposure heads 1a to 1d. As described above, the exposure head 1 of this embodiment includes a predetermined number of control circuits 56 that cover the print width in the main scanning direction. In this example, the control circuit 56 of one block controls 768 light emitting elements, and as a whole, the control circuit 56 of 10 blocks is daisy chain connected, but this is optional. Further, in this example, the circuit configuration is such that one block of the control circuit 56 controls four light emitting elements arranged in the sub-scanning direction, but this number can be arbitrarily set as necessary. The configuration and function of each part will be described below along the signal flow.

  Light emission time data (gradation data) input from the data control line is converted from serial data to parallel data in a deserializer (not shown) in the timing controller input unit 86, and 768 registers 70o and 70e extend to the right. However, the signals are sequentially sent to the shift registers 71o and 71e in synchronization with the clock. Each register 70o, 70e outputs light emission time data to each shift register 71o, 71e. The timing controller 69 outputs a Shift Clk signal, an SRn / O signal, and an SRn / E signal (n is a natural number, respectively) signals that control the operation timing of the shift registers 71o and 71e. Further, the timing controller 69 outputs an OELn / O signal and an OELn / E signal O (n is a natural number, respectively) signals for controlling the operation timing of the light emitting element driving circuits 74o and 74e.

  Each of the shift registers 71o and 71e includes four registers corresponding to the light emitting element array 8 connected in the sub-scanning direction, and the light emission time data sent from each of the registers 70o and 70e is sequentially synchronized with the Shift Clk signal. shift. The shift registers 71o and 71e output light emission time data to the comparators 73o and 73e in accordance with the SRn / O signal and the SRn / E signal from the timing controller 69.

  The counter 72 is a counter for controlling the light emission time, and the number of bits of the counter (here, 6 bits) is the same as the bit length of the light emission time data entering the shift register 71. The input frequency of this counter is the reciprocal (frequency) of the result of time-converting the pixel pitch in the sub-scanning direction and dividing the period by the number of counts. Here, the counter 72 outputs a 6-bit count value to the comparator 73 (o, e).

  The comparator 73 (o, e) has a 6-bit light emission time sent from the shift register 71 (o, e) in synchronization with the timing input signal SRn (o, e) to the shift register 71 (o, e). The data is compared with the 6-bit count value from the counter 72, and the comparison result is obtained as the timing input signal SRn (o, e) from the timing controller 69 to the shift register 71 (o, e) is the counter. It is performed at a time interval obtained by dividing 72 clock cycles by the number of lines in the main scanning direction.

  The power adjustment circuit 77 supplies power to the drive circuit 78 (o, e) via the power supply line 51. As shown in FIG. 12, the power adjustment circuit 77 adjusts the power supplied to the drive circuit 78 (o, e), for example, based on an external resistance having an appropriate value at the Vref terminal provided in the light emitting element array 8. To do. The value of the external resistance is determined by, for example, laser trimming the external resistance.

  In the light emitting unit 25, the drive circuit 78 (o, e) outputs the output signal from the comparator 73 (o, e), that is, the voltage of the capacitor line 52, and the timing signal from the timing controller 69, that is, the scanning line 53. The organic EL element 79 connected to the drive circuit 78 (o, e) selected based on the voltage is driven in an active matrix.

  As shown in FIG. 12, the drive circuit 78 (o, e) is divided into odd lines and even lines in the area of the light emitting section 25. The inputs of the drive circuit 78 (o, e) are connected to the capacitor line 52, the scanning line 53, and the power supply line 51. The output of the comparator 73 (o, e) is connected to the capacitor line 52, and the voltage supplied to the drive circuit 78 (o, e) is controlled by controlling the voltage of the capacitor line 52. The scanning line 53 is connected to the scanning line output of the timing controller 69, and the timing controller 69 selects and drives the driving circuit 78 (o, e) of each line. The power supply line 51 is connected to the output of the power adjustment circuit 77, and the power adjustment circuit 77 supplies drive power for the organic EL element 79.

  FIG. 13 is a diagram showing a circuit configuration of the organic EL element 79 and a drive circuit 78 (o, e) for driving the organic EL element 79 in an active matrix. In FIG. 13, the power supply line 51 is connected to the source Sb of the driving transistor Tr2. In FIG. 13, an organic EL (OEL) element 79 is used as a light emitting element, K is its cathode terminal, and A is its anode terminal. The anode terminal A is connected to the drain Db of the driving transistor Tr2. The cathode terminal K is connected to the ground line 54. The scanning line 53 is connected to the gate Ga of the switching transistor Tr1. The capacitor line 52 is connected to the source Sa of the switching transistor Tr1. The drain Da of the switching transistor Tr1 is connected to the storage capacitor Ca and the gate Gb of the driving transistor Tr2. The other electrode of the storage capacitor Ca is connected to the source Sb of the driving transistor Tr2.

  The source Sb of the driving transistor Tr 2 of the organic EL element 79 is connected to the power supply line 51, and the drain Db is connected to the anode terminal A of the organic EL element 79. Further, the gate Gb of the driving transistor Tr2 is connected to the drain Da of the switching transistor Tr1.

  Next, the operation of the circuit of FIG. 13 will be described. When the scanning line 53 is energized while the voltage of the power supply line 51 is applied to the drain Da of the switching transistor Tr1 via the storage capacitor Ca, the switching transistor Tr1 is turned on. For this reason, the gate voltage of the driving transistor Tr2 decreases, the voltage of the power supply line 51 is supplied from the source Sb of the driving transistor Tr2, and the driving transistor Tr2 becomes conductive. As a result, the organic EL element 79 operates and emits light with a predetermined amount of light. The storage capacitor Ca is charged by the potential difference between the power supply line 51 and the capacity line 52.

  Even when the switching transistor Tr1 is turned off, the driving transistor Tr2 is still in the conductive state based on the electric charge charged in the storage capacitor Ca, so that the organic EL element 79 maintains the light emitting state. Therefore, when the active matrix is applied to the drive circuit of each light emitting unit formed in the light emitting element array 8, the switching transistor Tr1 is used to transfer image data (light emission time data or gradation data) by the shift register. Even when it is turned off, the operation of the organic EL element 79 can continue to emit light, and the pixel can be exposed with high luminance.

  FIG. 14 is a diagram showing the arrangement of the organic EL element 79 and the drive circuit 78 shown in FIGS. 9 and 13. As described with reference to FIG. 9, in the present embodiment, the organic EL elements 79 and the drive circuits 78 are alternately arranged in a staggered manner.

  The capacitor line 52 and the scanning line 53 are provided between the organic EL element 79 and the drive circuit 78. In the present embodiment, the capacitor line 52 extends between the organic EL element 79 and the drive circuit 78 mainly in the width direction of the light emitting element array 8 (see FIG. 7), that is, in the main scanning direction of the exposure head. ing. The scanning line 53 extends between the organic EL element 79 and the drive circuit 78 mainly in the longitudinal direction of the light emitting element array 8, that is, in the sub scanning direction of the exposure head. In other words, in the present embodiment, the capacitor line 52 and the scanning line 53 are provided in a lattice shape in the light emitting unit 25.

  The drive circuits 78 are arranged in a staggered manner in a region delimited by the capacitor lines 52 and the scanning lines 53. That is, the drive circuit 78 is disposed in a region surrounded by the capacitor lines 52 and the scanning lines 53 that are disposed in a lattice pattern.

  The drive circuit 78 and the capacitor line 52 and the scanning line 53 provided around the drive circuit 78 are covered with an insulating layer 44. The insulating layer 44 is provided with an opening 100 in a region surrounded by the capacitor line 52 and the scanning line 53 between the plurality of drive circuits 78, and the organic EL element 79 is provided inside the opening 100. As shown in FIG. 14, in the present embodiment, the opening 100 is provided in a circular shape, but may be provided in an elliptical shape or a rectangular shape.

  In the present embodiment, the capacitor line 52 and the scanning line 53 are provided such that the region where the organic EL element 79 is provided is larger than the region where the drive circuit 78 is provided. Specifically, a plurality of capacitor lines 52 are provided mainly at a predetermined interval in the main scanning direction. However, the drive circuit 78 sets the interval between adjacent capacitor lines 52 in the region where the organic EL element 79 is provided. It is provided so as to be wider than the interval between the adjacent capacitor lines 52 in the region.

  FIG. 15 is a cross-sectional view of the light-emitting element array 8 in the II direction shown in FIG. The light emitting element array 8 includes a power supply line 51, a capacitor line 52, and an anode electrode 17 provided on the glass substrate 60, and an organic EL element 79 and a drive circuit 78 provided on the upper layer thereof. . The scanning line 53 is provided around the drive circuit 78, and the drive circuit 78 and the scanning line 53 are covered with an insulating layer 44.

  The insulating layer 44 has an opening 100 so that the anode electrode 17 is exposed, and the organic EL element 79 is connected to the anode electrode 17 inside the opening 100. Specifically, the organic EL element 79 has a structure in which a hole transport layer 33, a light emitting layer 34, and an electron transport layer 94 are stacked, and the hole transport layer 33 is connected to the anode electrode 17. . A cathode electrode 35 is provided on the upper layer of the organic EL element 79 and is connected to the electron transport layer 94.

  Each of the hole transport layer 33, the light emitting layer 34, and the electron transport layer 94 is formed by discharging a liquid material containing the materials constituting them into the opening 100. That is, each of the hole transport layer 33, the light emitting layer 34, and the electron transport layer 94 discharges the liquid material into the opening 100 with the insulating layer 44 covering the drive circuit 78, the capacitor line 52, and the scan line 53 as a bank. Formed.

  Specifically, first, the opening 100 is formed in the insulating layer 44, and the anode electrode 17 is exposed at the bottom of the opening 100. Next, a liquid material containing a material constituting the hole transport layer 33 is discharged to the opening 100 to form a liquid layer on the anode electrode 17. Then, the hole transport layer 33 is formed on the anode electrode 17 by evaporating the solvent from the liquid layer.

  Similarly, after forming the hole transport layer 33, a liquid material containing a material constituting the light emitting layer 34 is discharged on the upper layer to form a liquid layer, and the solvent is evaporated from the liquid layer to emit the light emitting layer 34. Form. And after forming the light emitting layer 34, the liquid material containing the material which comprises the electron carrying layer 94 is discharged on the upper layer, a liquid layer is formed, a solvent is evaporated from the said liquid layer, and the electron carrying layer 94 is formed. Form. As a result, the organic EL element 79 is formed in the opening 100 using the insulating layer 44 as a bank.

<About control timing>
FIG. 16 is a timing chart for explaining the input signal timing of the timing controller 69. The control line of the timing controller 69 consists of five sets of differential lines, and FIG.

  The signal SP (P / N) is a start signal, and a pulse is generated before the emission time data is received. Thereafter, the signal SP (P / N) is generated every time before reception of 768 pixels × 6 bits = 4608 emission time data (FIG. 16 ( A)). The timing controller 69 counts the number of pulses of the SP (P / N) signal, compares it with the address value set in the control circuit 56, and takes in 768 × 6 data thereafter when they match.

  The signal SDCLK (P / N) is a serial data synchronization clock, and serial data is read in synchronization with both rising and falling edges of the clock (FIG. 16B). The period of the signal SDCLK is a value obtained by dividing the maximum light emission time of each light emitting element by the number of light emitting elements in the main scanning direction, further dividing by the light emission time data width, and multiplying that value by the number of reads in the period of the signal SDCLK. . These values are as follows, for example (A4, 600 dpi, 50 ppm tandem color printer).

Maximum light emission time = 170 (μsec)
Number of light emitting elements in main axis direction = 7680 (pieces)
Light emission time data width = 6 (bits)
Number of reads in SDCLK cycle = 2 (times)
SDCLK cycle = 170 (μsec) ÷ 7680 ÷ 6 × 2≈7.4 (nsec)
Therefore, the frequency of the signal SDCLK is about 135.5 MHz.

  The signal SD (P / N) is a set of 6-bit serial data (light emission time data), and is read in synchronization with the signal SDCLK as shown in FIG. 16 (FIG. 16C).

  FIG. 17 is a timing chart for explaining the input signal timing of the timing controller 69. The timing of two sets of input signals other than the input signals shown in FIG. 16 among the five sets of differential input signals of the light emitting element array 8 is shown.

  The signal RCLR (P / N) is a data clear signal of the shift registers 70o and 70e, and the light emission time data output to the shift register 71 (o, e) is cleared by this pulse (FIG. 17A). . The signal RCLR (P / N) also serves as a data clear signal for the light amount adjustment register.

  The signal TCCLK (P / N) is a reference clock related to the light emission time control of the light emitting element controlled by the timing controller 69, and based on this, the signal Shift Clk, the signal CCLK, the signal OELn / O, and the signal OELn / E. The timings of the signals SRn / O and SRn / E are determined (FIG. 17B).

  FIG. 18 shows the transfer timing of the light emission time data sent from the timing controller 69 to the shift registers 110o and 110e. The signal SPCLK is an image data transfer start signal (FIG. 18A), and the signal PDCLK is a synchronous clock during data transfer (FIG. 18B). The signal PADn (n: 0 to 5) is parallel light emission time data, and is sequentially written in the shift registers 110o and 110e in synchronization with the rise and fall of the signal PDCLK (FIGS. 18C to 18H). )).

  FIG. 19 is a timing chart for explaining details of the selector unit output signal timing of the timing controller 69.

  The signal TCCLK is a reference clock for controlling the light emission time of the light emitting elements, and the period is divided by dividing the maximum light emission time of each light emitting element by the light emission time control division number and further dividing by the number of lines in the sub-scanning direction. (FIG. 19A). For example, in the case of an A4, 600 dpi, 50 ppm tandem color printer, it is as follows.

Maximum light emission time = 170 (μsec)
Light emission time control division number = 26 = 64 (division)
Number of lines in the sub-scanning direction = 8 (lines)
TCCLK cycle = 170 (μsec) ÷ 64 ÷ 8≈332 (nsec)
Therefore, the frequency of the signal TCCLK is about 3 MHz.

  The signal SHIFT CLK is a clock for sequentially shifting the register holding values of the shift registers 71o and 71e, and is obtained by dividing the maximum light emission time of each element by the light emission time control division number (FIG. 19B )).

  The signal CCLK is a count input signal of the light emission timing control circuits 116o and 116e, and has the same frequency as the signal SHIFT CLK (FIG. 19C).

  The scanning line signal OEL1 / O and the register selection signal SR1 / O generate a pulse for one cycle of the TCCLK clock in synchronization with the rising edge of the first TCCLK from the falling edge of the SHIFT CLK at the same timing (FIG. 19 ( D) and FIG. 19 (E)).

  The signal OEL ON / OFF indicates the ON time (light emission time) of the organic EL element 79. In this example, the light emission time range is from 0 microsecond to the maximum light emission time 170 microsecond (FIG. 19F). )).

  The light emission operation will be described with reference to these signals. The light emission time data output from the first-stage register of the shift register 71o by the register selection signal SR1 / O is compared with the counter value, and an ON or OFF signal is output to the capacitor line 52. On the other hand, at the same timing, the scanning line signal OEL1 / O is output to the first stage driving circuit 78 at regular intervals.

  As described above, if the capacitance line 52 is ON when the scanning line signal OEL1 / O is ON, the organic EL element 79 is lit. Even when the scanning line signal OEL1 / O is turned off, the organic EL element 79 is kept on. Further, if the capacitance line 52 is OFF when the scanning line signal OEL1 / O is ON, the organic EL element 79 is turned off.

  FIG. 20 is a timing chart illustrating signal timings of the selector unit of the timing controller 69 and the light emitting element driving circuit. In FIG. 20, the light emission control timing of the light emitting elements of 8 lines including the even lines and the odd lines in the sub-scanning direction will be described.

  The scanning line signal OELn / O and the register selection signal SRn / O generate pulses corresponding to one cycle of the TCCLK clock in synchronization with the rising edge of the nth TCCLK from the falling edge of the SHIFT CLK at the same timing. Since the register selection signal SRn / O selects the n-th line register of the shift register 71, the light emission time data output from the register is compared with the counter value by the comparator 73, and the capacitor line 52 is turned ON or OFF. A signal is output. On the other hand, at the same timing, the scanning line signal OELn / O selects the nth light emitting element scanning line. As described above, the drive circuit 78 can turn on / off the light emitting element only when the scanning line is selected depending on the state of the capacitor line 52 at that time. Therefore, the plurality of drive circuits 78 can be driven in a time-sharing manner by shifting the selection timing of the scanning lines connected to other light emitting element drive circuits that share the capacitor line 52.

  When all the light emission based on the light emission time data of each register of the shift register 71 is completed, the light emission time data of each register of the shift register 71 is shifted to the next register every 64 pulses of SHIFT CLK, and light is emitted in the same manner. At this time, by moving the relative positions of the photoconductor and the organic EL array in the sub-scanning direction, exposure based on the same light emission time data can be performed on the same pixel on the photoconductor.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

FIG. 3 is a plan view of the entire exposure head as viewed from above. 2 is a partially enlarged view of a portion A shown in FIG. 1 of the exposure head 1. FIG. It is sectional drawing in the II line direction shown in FIG. FIG. 3 is a partially enlarged view of a portion B shown in FIG. 2 of the exposure head 1 and shows a detailed configuration of the condenser lens array 4. It is a figure explaining still in detail about the arrangement state of condensing lens array. It is a figure explaining the state at the time of exposing a photoreceptor with the exposure head of the arrangement | sequence state shown in FIG. It is a figure explaining the light emitting element array 8 still in detail. It is sectional drawing of the II direction shown in FIG. 3 is an enlarged view of a light emitting unit 25. FIG. 2 is a block diagram illustrating a configuration example of an exposure control circuit centering on a path of image data inside the image forming apparatus. FIG. It is a block diagram which shows the structure of the light emitting element array 8 contained in exposure head 1a-d. It is a figure explaining the circuit structure of the light emitting element array 8 contained in each exposure head 1a-d in detail. It is a figure which shows the circuit structure of the organic EL element 79 and the drive circuit 78 (o, e) for driving this with an active matrix. It is a figure which shows arrangement | positioning of the organic EL element 79 and the drive circuit 78 which were shown in FIG.9 and FIG.13. It is sectional drawing of the light emitting element array 8 in the II direction shown in FIG. 4 is a timing chart for explaining input signal timing of a timing controller 69. 4 is a timing chart for explaining input signal timing of a timing controller 69. It shows the transfer timing of the light emission time data sent from the timing controller 69 to the shift registers 110o and 110e. 6 is a timing chart for explaining details of a selector unit output signal timing of the timing controller 69; 6 is a timing chart for explaining signal timings of a selector unit of a timing controller 69 and a light emitting element driving circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Exposure head, 2 ... Connector, 3 ... Support frame, 4 ... Condensing lens array, 8 ... Light emitting element array, 13 ... Condensing lens, 17 ... Anode Electrode, 21... Control line pad, 24... Sealant, 25. Light emitting part, 27... Through hole, 31. ... Light emitting layer, 35 ... Cathode electrode, 44 ... Insulating layer, 51 ... Power supply line, 52 ... Capacity line, 53 ... Scan line, 54 ... Ground line, 56 ... Control circuit, 57 ... Data control line, 58 ... Power supply line, 60 ... Glass substrate, 64 ... Printer controller, 65 ... Image data transmission unit, 66 ... Differential signal wiring, 68... Head controller, 69... Timing controller, 70. 71, shift register, 72, counter, 73, comparator, 74, light emitting element drive circuit, 77, power adjustment circuit, 78, drive circuit, 79, organic EL element

Claims (4)

A substrate having a predetermined area;
A plurality of organic EL elements arranged in a staggered pattern in the predetermined region;
A plurality of drive circuits arranged between the plurality of organic EL elements in the predetermined region, and emitting light from the plurality of organic EL elements;
A shift register arranged corresponding to the plurality of drive circuits in the periphery of the predetermined region and transferring light emission data for emitting light from the organic EL elements to the plurality of drive circuits;
An exposure head comprising:   2. The exposure head according to claim 1, wherein the predetermined area is provided in a strip shape, and the shift register is disposed substantially parallel to the longitudinal direction of the predetermined area.   2. The apparatus according to claim 1, further comprising a plurality of wirings provided between the plurality of organic EL elements and the plurality of drive circuits, and connecting the plurality of drive circuits and the shift register. 2. The exposure head according to 2.   An image forming apparatus comprising the exposure head according to claim 1.

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