JP2006165112A - Through-electrode formation method and method for manufacturing semiconductor device using same, and semiconductor device obtained thereby - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a through-electrode formation method to stably form a through electrode which is superior in conductivity and has no change in conductivity. <P>SOLUTION: A non-through hole 24 is formed which has an opening 24a on one surface of a substrate 21 and a bottom 24b in the inside thereof, and an insulating film 26 is formed on the inner wall of the substrate 21 facing on the non-through hole 24. In this case, the non-through hole 24 is formed in a manner that an area of the substrate 21 being on the bottom 24b of the non-through hole 24 may be larger than that of the opening 24a. Then, a conductive plug 35a as a conductor is put into the non-through hole 24 with the insulating film 26, and the other surface of the substrate 21 is retreated until the conductive plug 35a as a conductor is exposed outside. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a through electrode forming method, a semiconductor device manufacturing method using the same, and a semiconductor device obtained by the method.

  Electronic devices such as computers and communication devices are equipped with a semiconductor device in which a large number of elements such as transistors and resistors are integrated on a semiconductor substrate. The performance of such a semiconductor device greatly affects the performance of the entire electronic device.

  In recent years, semiconductor devices are also mounted in electronic devices typified by portable information devices such as mobile phones. Such electronic devices such as portable information devices are required to be reduced in size and weight, and semiconductor devices mounted on the electronic devices are also reduced in size and density. In order to reduce the size and density of a semiconductor device, a multi-chip semiconductor device in which a plurality of semiconductor devices are stacked has been proposed (for example, see Patent Document 1). Multi-chip semiconductor devices are being further developed because they have a small planar area, a simple structure, and a small thickness.

  FIG. 12 is a simplified cross-sectional view showing an example of the configuration of the multichip semiconductor device 1. The multichip semiconductor device 1 is configured by stacking a plurality (three in FIG. 12) of chips 2. Each chip 2 passes through the semiconductor substrate 3, a semiconductor substrate 3 on which elements (not shown) are integrated, an interlayer insulating film 4 formed on the surface of elements integrated on the semiconductor substrate 3, and the semiconductor substrate 3. And a through electrode 5 that is formed in the through hole and electrically connects the chips 2 to each other. A sidewall insulating film 6 is formed between the semiconductor substrate 3 and the through electrode 5 so that the semiconductor substrate 3 and the through electrode 5 are insulated. On the surface of the semiconductor substrate 3 opposite to the side on which the interlayer insulating film 4 is provided, a back surface insulating film 7 and a back surface wiring (not shown) are formed. In such a multichip semiconductor device 1, the chips 2 are electrically connected to each other by the through electrodes 5 provided on each chip 2 and the bump electrodes 8 that connect the through electrodes 5 to each other.

  The chip 2 included in such a multichip semiconductor device 1 is manufactured by the following procedure. First, an element is integratedly formed on one surface of a wafer-like semiconductor substrate 3, an interlayer insulating film 4 is formed on the surface of the integrated element, and the surface of the semiconductor substrate 3 on which the element is formed (hereinafter referred to as the element). A non-through hole that does not penetrate the semiconductor substrate 3 is formed from the side that may be referred to as a main surface. Next, a sidewall insulating film 6 is formed on the inner wall facing the non-through hole of the semiconductor substrate 3, and a conductive material is filled into the non-through hole in which the sidewall insulating film 6 is formed. Thereafter, the other surface (hereinafter also referred to as the back surface) opposite to the main surface of the semiconductor substrate 3 is polished and receded by mechanical grinding or the like, and the filled conductive material is removed from the semiconductor substrate 3. The through electrode 5 is formed by exposing the back surface outward. Next, the back surface insulating film 7 and the back surface wiring are formed on the back surface of the semiconductor substrate 3 on which the through electrode 5 is formed. In this way, the wafer-like semiconductor substrate 3 on which the electrode, the insulating film and the like are formed is cut, and the chip 2 is cut out.

  Here, the sidewall insulating film 6 is formed by forming a silicon oxide film or a silicon nitride film on the inner wall facing the non-through hole of the semiconductor substrate 3 by using, for example, a CVD method (Chemical Vapor Deposition). Is done. However, the formation of the sidewall insulating film 6 by such a CVD method takes time for film formation, leading to an increase in manufacturing cost. Therefore, as a method of easily forming the sidewall insulating film 6 at a low cost, a method of applying an insulating material to the inner wall facing the non-through hole of the semiconductor substrate 3 using a stencil printing method, a spray method or the like is used.

  FIG. 13 is a diagram for explaining a method of forming the insulating films 13a and 13b and the through electrodes 14a and 14b in the non-through holes 11a and 11b. In the following description, alphabets are omitted except when a specific non-through hole and an insulating film are designated and described. When an insulating material is applied to the inner wall of the semiconductor substrate 12 facing the non-through hole 11 by a stencil printing method, a spray method, or the like, the non-through hole 11 generally has a non-opening area and a non-open area as shown in FIG. It is formed so that the area of the substrate facing the bottom of the through hole 11 (hereinafter sometimes referred to as the bottom of the non-through hole 11) is substantially equal.

  An insulating material such as a resin is applied to the inner wall of the semiconductor substrate 12 facing the non-through hole 11 (hereinafter also referred to as the inner wall of the non-through hole 11) by stencil printing, spraying, or the like. . Here, the insulating material tends to flow through the inner wall of the non-through hole 11 to the bottom of the non-through hole 11 by its own weight. The insulating material is held in a state where the surface area of the insulating material that tends to flow toward the bottom of the non-through hole 11 and the insulating material that tries to stay on the inner wall of the non-through hole 11 is reduced by the surface tension. . As a result, as shown in FIG. 13B, the insulating material is not applied so much in the vicinity of the opening but is applied in a large amount near the bottom of the inner wall of the non-through hole 11. Here, an angle θ1 formed by the normal unit vector v1 of the surface 15 of the insulating film 13 obtained by curing the insulating material applied to the inner wall of the non-through hole 11 and the normal unit vector v2 of the main surface of the semiconductor substrate 12 is formed. Is between 60 ° and 88 °. The inner product of the respective normal unit vectors v1 and v2 is 0.034 to 0.5.

  Next, as shown in FIG. 13C, the conductor 16 is filled in the non-through hole 11 in which the insulating film 13 is formed in the above state, and mechanical polishing, etching, etc. are performed as shown in FIG. The back surface of the semiconductor substrate 12 is retracted by the method described above, and the filled conductor 16 is exposed on the back surface of the semiconductor substrate 12 to form the through electrode 14.

  When the through electrode 14 is formed by the conventional method as described above, the area of the through electrode 14 exposed to the outside differs between the main surface side and the back surface side of the semiconductor substrate 12. Further, for example, as shown in FIG. 13, when two through electrodes 14a and 14b are formed, if the depth at which the non-through hole 11a is formed differs from the depth at which the non-through hole 11b is formed, In the non-through holes 11a and 11b, the areas of the through electrodes 14a and 14b exposed from the back surface of the semiconductor substrate 12 are also different.

  The semiconductor substrate 12 on which such a through electrode 14 is formed tapers due to a reduction in the area of the through electrode 14 exposed on the back surface side, and the resistance value increases, so that stable conductivity cannot be obtained. In addition, there is a problem in that the area exposed from the back surface is different between the through electrode 14a and the through electrode 14b, and the resistance value of each through electrode varies.

Japanese Patent Laid-Open No. 10-223833 (page 5-6, FIG. 1)

  An object of the present invention is to provide a through electrode forming method and a semiconductor device manufacturing method capable of stably forming a through electrode having excellent conductivity and no variation in conductivity, and a semiconductor device manufactured by the manufacturing method. Is to provide.

The present invention relates to a method for forming a through electrode penetrating a substrate.
A non-through hole forming step of forming a non-through hole having an opening on one surface of the substrate and having a bottom inside the substrate;
An insulating film forming step of forming an insulating film on the inner wall of the substrate facing the non-through hole;
A conductor filling step of filling a non-through hole in which an insulating film is formed with a conductor;
A through hole forming step of retracting the other surface of the substrate until the conductor is exposed to the outside,
Non-through holes are
In the method of forming a through electrode, the area of the substrate facing the bottom of the non-through hole is formed to be larger than the area of the opening.

In the present invention, the non-through hole is
The surface of the substrate facing the bottom of the non-through hole is formed to be substantially circular.

In the present invention, the non-through hole is
A vector directed from the inner wall of the substrate facing the non-through hole to the inside of the non-through hole, and in a virtual cross section perpendicular to one surface of the substrate, the bottom peripheral edge of the non-through hole, and the bottom peripheral edge of the non-through hole A normal unit vector of a virtual plane connecting the peripheral edge of the opening of the non-through hole on the inner wall surface of the substrate formed in a row,
A vector directed outward from one surface of the substrate, wherein an inner product with a normal unit vector of one surface of the substrate is −0.5 or more and −0.034 or less. And

  Moreover, this invention is a manufacturing method of the semiconductor device using the formation method of the penetration electrode as described in any one of the above.

Moreover, this invention is a semiconductor device manufactured by the manufacturing method of the said semiconductor device,
A through electrode penetrating the semiconductor substrate from one surface, which is a surface on which the semiconductor element is formed, of the semiconductor substrate toward the other surface opposite to the one surface;
Including an insulating film provided between the through electrode and the semiconductor substrate,
Insulating film
The cross-sectional area in a virtual plane perpendicular to the thickness direction of the semiconductor substrate increases as it goes from one surface of the semiconductor substrate to the other surface,
The through electrode is
The semiconductor device is characterized in that an area in a virtual plane including one surface of the semiconductor substrate is substantially equal to an area in a virtual plane including the other surface of the semiconductor substrate.

  According to the present invention, a through electrode forming method includes a non-through hole forming step of forming a non-through hole having an opening on one surface of a substrate and having a bottom inside the substrate, and a substrate facing the non-through hole. An insulating film forming step for forming an insulating film on the inner wall of the substrate, a conductor filling step for filling the non-through hole in which the insulating film is formed with a conductor, and a penetration for retreating the other surface of the substrate until the conductor is exposed to the outside. A non-through hole is formed such that the area of the substrate facing the bottom of the non-through hole is larger than the area of the opening. When such a non-through hole is formed, the shape of the insulating film formed on the inner wall of the substrate facing the non-through hole is suitable, and the filled conductor is one side of the substrate (hereinafter referred to as the main surface). And the area on the virtual plane including the other surface of the substrate (hereinafter sometimes referred to as the back surface) is substantially equal. As a result, the exposed areas are different between the main surface and the back surface, and an increase in the resistance value of the electrode due to the tapered shape of the through electrode can be prevented. Even when a plurality of through electrodes are formed, there is no variation in the area on the virtual plane including the main surface and the back surface of the electrode between the electrodes. Therefore, it is possible to obtain a through electrode having excellent conductivity and having no variation in conductivity between the plurality of electrodes.

  According to the invention, the non-through hole is formed so that the surface of the substrate facing the bottom of the non-through hole has a substantially circular shape. When the surface of the substrate facing the bottom of the non-through hole is formed in, for example, a rectangular shape, the rectangular corner of the bottom of the non-through hole is formed during the insulating film forming step of forming an insulating film on the inner wall of the substrate facing the non-through hole. A large amount of insulating film material is stored in the portion. If a large amount of the insulating film material is stored in this way, the area exposed on the back surface of the substrate of the filled conductor after the through hole forming step is performed is larger than the area exposed on the main surface of the substrate. May also be reduced, leading to an increase in resistance. If the surface of the substrate facing the bottom of the non-through hole is formed to have a cornerless shape, that is, a substantially circular shape, it is possible to prevent storage of the insulating film material in the corner portion of the bottom portion. The surface of the substrate facing the bottom of the hole is preferably formed in a substantially circular shape.

  Further, according to the present invention, the non-through hole is a vector directed from the inner wall of the substrate facing the non-through hole to the inside of the non-through hole, and in a virtual cross section perpendicular to the main surface of the substrate, the bottom peripheral edge of the non-through hole And a normal unit vector of a virtual plane that connects the peripheral edge of the bottom of the non-through hole to the peripheral edge of the opening of the non-through hole on the inner wall surface of the substrate, and outward from the main surface of the substrate The inner product of the vector and the normal unit vector of the main surface of the substrate is -0.5 or more and -0.034 or less. When the non-through hole is formed in this way, the insulating film formed on the inner wall of the substrate facing the non-through hole has a surface facing the center of the non-through hole of the insulating film substantially perpendicular to the main surface of the substrate. Formed to be. Therefore, when a conductor is filled in a non-through hole in which such an insulating film is formed between the substrate and the substrate, the surface of the conductor in contact with the insulating film can also be made substantially perpendicular to the main surface of the substrate. As a result, after the through-hole forming step, a conductor having the same area is exposed on the main surface and the back surface of the substrate, and a through electrode having excellent conductivity and no variation in conductivity between the plurality of electrodes is formed. be able to.

  Further, according to the present invention, since the semiconductor device can be manufactured using the through electrode forming method as described above, a through electrode having excellent conductivity and having no variation in conductivity among a plurality of electrodes is formed. be able to. Therefore, also in the manufactured semiconductor device, signal delay and the like are prevented, and the performance is improved.

  According to the invention, the semiconductor device is manufactured by the method for manufacturing a semiconductor device as described above, and is provided between the through electrode penetrating the semiconductor substrate from the main surface to the back surface of the semiconductor substrate, and between the through electrode and the semiconductor substrate. The cross-sectional area in a virtual plane perpendicular to the thickness direction of the semiconductor substrate increases from the main surface of the semiconductor substrate to the back surface, and the through electrode is formed on the main surface of the semiconductor substrate. And the area in the virtual plane including the back surface of the semiconductor substrate are substantially equal. A semiconductor device provided with such a through electrode has excellent performance because it has a through electrode with excellent conductivity and no variation in conductivity.

  FIG. 1 is a diagram for explaining an outline of a semiconductor device manufacturing method according to an embodiment of the present invention. The manufacturing method of the semiconductor device of this embodiment includes a step of forming the through electrode 27 that penetrates the semiconductor substrate 21 using the through electrode forming method of the present invention. The method of forming the through electrode 27 in this embodiment includes a non-through hole forming step of forming a non-through hole 24 having an opening 24a on one surface of the semiconductor substrate 21 and a bottom 24b inside the semiconductor substrate 21; An insulating film forming step of forming a sidewall insulating film on the inner wall of the semiconductor substrate 21 facing the non-through hole 24; a conductor filling step of filling the non-through hole 24 in which the sidewall insulating film 26 is formed with a conductor 35; A through hole forming step of retracting the other surface of the semiconductor substrate 21 until the conductor 33 is exposed to the outside. The non-through hole 24 has an area of the semiconductor substrate 21 facing the bottom portion 24b of the non-through hole 24. It is formed so as to be larger than the area of 24a.

  A method for manufacturing the semiconductor device according to the present embodiment will be described below with reference to FIG. First, semiconductor elements (not shown) are integrated and formed on one surface of the semiconductor substrate 21 to form a semiconductor circuit. Hereinafter, one surface, which is a surface on which semiconductor elements (not shown) are integrated, may be referred to as a main surface. Next, an interlayer insulating film 22 is formed on the main surface of the semiconductor substrate 21, and a surface electrode (not shown) is formed on the surface thereof. The semiconductor substrate 21 is, for example, single crystal silicon, and the plane orientation is not particularly limited. As the thickness of the semiconductor substrate 21, for example, a thickness of 700 μm is used.

  Interlayer insulating film 22 is made of, for example, silicon dioxide, and is provided to insulate semiconductor substrate 21 and the semiconductor circuit formed on semiconductor substrate 21 from a surface electrode (not shown). A surface electrode (not shown) is formed of, for example, a copper-aluminum alloy film, a titanium film, a titanium nitride film, or the like, and is provided as a connection terminal between the semiconductor circuit and an external device.

  As shown in FIG. 1A, the semiconductor substrate 21 on which the semiconductor element (not shown), the interlayer insulating film 22 and the surface electrode are formed on the main surface has an opening 24a on the main surface of the semiconductor substrate 21. Then, the non-through hole 24 having the bottom 24 b is formed inside the semiconductor substrate 21. The non-through hole 24 is formed so as not to penetrate the surface opposite to the main surface of the semiconductor substrate 21 (hereinafter sometimes referred to as the back surface) by, for example, reactive ion etching (RIE) method. . Hereinafter, the non-through hole forming step for forming the non-through hole 24 will be described.

  FIG. 2 is a diagram illustrating a method for forming the non-through hole 24. The non-through hole 24 in which the area of the semiconductor substrate 21 facing the bottom 24b, which is the most characteristic feature of the present invention, is larger than the area of the opening 24a is formed as follows. In FIG. 2, the description of the interlayer insulating film 22 shown in FIG. 1 is omitted.

  First, as shown in FIG. 2A, a photoresist solution is applied to the semiconductor substrate 21 on which the interlayer insulating film 22 and the surface electrode are formed, exposure and development are performed, and hard baking is performed. A pattern mask 23 having a resist opening at a position predetermined to form 24 is obtained. As the photoresist liquid for forming the pattern mask 23, a general positive resist can be used. Examples of the positive resist include novolak and diazonaphthoquinone type resists. The photoresist liquid is applied to the semiconductor substrate 21 using a spin coating method or the like. The pattern mask 23 formed by applying by spin coating or the like has a thickness of about 8 μm, for example. The resist opening is formed in a circular shape having a diameter of 40 μm, for example.

  After the pattern mask 23 is formed, the surface electrode is etched. Specifically, a portion of the surface electrode exposed through the resist opening of the pattern mask 23 is removed by wet etching. In wet etching, for example, a general mixed aqueous solution of phosphoric acid, acetic acid, and nitric acid can be used to remove the copper-aluminum alloy film. For removing the titanium film and the titanium nitride film, a general liquid mixture of hydrogen peroxide and hydrofluoric acid can be used. For removal of the titanium nitride film, a mixed aqueous solution of sodium hydroxide, hydrogen peroxide and an organic compound may be used. Further, the etching of the surface electrode is not limited to the above-described wet etching, and a dry etching method can also be used.

  When the portion of the surface electrode exposed through the resist opening is removed, the portion of the interlayer insulating film 22 exposed through the resist opening is removed. The removal of the interlayer insulating film 22 can be realized by a known method such as dry etching or wet etching. For example, wet etching using a hydrofluoric acid buffer solution is preferably used. By removing the interlayer insulating film 22, the semiconductor substrate 21 is exposed through the resist opening as shown in FIG.

  Next, non-through holes 24 are formed in the semiconductor substrate 21. The non-through holes 24 can be formed in the semiconductor substrate 21 by a dry etching method such as a reactive ion etching method. As an etching gas used for reactive ion etching, a gas containing fluoride is preferably used. As the gas containing fluoride, for example, a mixed gas of sulfur hexafluoride and argon having high normal incidence is preferably used. In the step shown in FIG. 2B, silicon constituting the semiconductor substrate 21 is volatilized by reacting with sulfur hexafluoride gas to form silicon tetrafluoride.

  In the step shown in FIG. 2C, the inner wall of the semiconductor substrate 21 facing the non-through hole 24 (hereinafter, may be referred to as the inner wall of the non-through hole 24) and the non-through hole, for example, with tetrafluorocarbon gas. A protective film 25 is formed on the surface of the semiconductor substrate 21 facing the bottom 24 b of 24 (hereinafter sometimes referred to as the bottom 24 b or the bottom 24 b of the non-through hole 24). In the step shown in FIG. 2D, the non-through hole 24 in which the protective film 25 is formed is formed on the bottom 24b of the non-through hole 24 in the protective film 25 by argon gas having high perpendicular incidence. Only the protective film 25 is removed. Next, etching is performed with sulfur hexafluoride gas, and the non-through holes 24 are dug down.

  By repeating the dug-down of the non-through hole 24 shown in FIG. 2D and the formation of the protective film 25 shown in FIG. 2C, for example, a plurality of times every 5 to 6 seconds, non-penetration is performed. The hole 24 is formed in a desired size. When each step is repeated in this manner, the amount of tetrafluorocarbon gas used is gradually reduced in the formation step of the protective film 25 shown in FIG. 2C, and the non-through holes 24 shown in FIG. In the drilling process, the amount of sulfur hexafluoride gas used is gradually increased. As a result, the non-through hole 24 in which the area of the bottom 24b is larger than the area of the opening 24a can be formed.

  By the non-through hole forming step as described above, the non-through hole 24 as shown in FIG. 1A (a) is formed. The inner wall of the non-through hole 24 actually has a bottom portion 24b that is gradually increased from the main surface to the back surface of the semiconductor substrate 21 as shown in FIG. In order to avoid this, the inner wall of the non-through hole 24 is approximated to a straight line in the cross-sectional views of the drawings except for FIG.

  3 is a cross-sectional view of the semiconductor substrate 21 having the non-through holes 24 formed in a truncated cone shape by the method shown in FIG. 2, and FIG. 4 is a view of the semiconductor substrate 21 having the non-through holes 24 from the main surface side. It is a top view. The non-through hole 24 is formed in a truncated cone shape in which the opening 24a and the bottom 24b are circular, and the diameter rb of the bottom 24b is larger than the diameter ra of the opening 24a. Therefore, the non-through hole 24 is formed such that the area of the bottom 24b is larger than the area of the opening 24a. The non-through hole 24 is formed so that the area converges from the bottom 24b to the opening 24a.

  Exemplifying the size of the non-through hole 24, the diameter ra of the opening 24a is 40 μm, the diameter rb of the bottom 24b is 51 μm, and the depth d is 100 μm. When the non-through-hole 24 having such a size is formed, the normal unit vector va of the surface connecting the peripheral edge of the bottom 24b of the non-through-hole 24 and the peripheral edge of the opening 24a of the non-through-hole 24, and the semiconductor substrate 21 main The inner product of the surface and the normal unit vector vb is −0.054 (θ2 = 93.1 °).

  Here, the non-through hole 24 is a vector from the inner wall of the semiconductor substrate 21 facing the non-through hole 24 toward the inside of the non-through hole 24, and in a virtual cross section perpendicular to one surface of the semiconductor substrate 21, the non-through hole 24. A normal unit vector of a virtual plane connecting the peripheral portion of the bottom 24b of the base plate 24 and the peripheral portion of the opening 24a of the non-through hole 24 of the inner wall surface of the semiconductor substrate 21 formed continuously with the peripheral portion of the bottom 24b of the non-through hole 24. Hereinafter, simply referred to as a normal unit vector va of the inner wall surface of the non-through hole 24), va is a vector directed outward from one surface of the semiconductor substrate 21, and is a normal line of one surface of the semiconductor substrate 21. When the unit vector (hereinafter simply referred to as the normal unit vector vb of the main surface of the semiconductor substrate 21) is vb, the inner product of va and vb is −0.5 or more and −0.034 or less. Like to Arbitrariness. That is, the angle θ2 formed by the normal unit vector va of the inner wall surface of the non-through hole 24 and the normal unit vector vb of the main surface of the semiconductor substrate 21 is preferably 92 ° or more and 120 ° or less. The reason for limiting the angle θ2 will be described later.

  As described above, when the non-through hole is formed such that the area of the bottom is larger than the area of the opening, the area of the bottom can be increased without increasing the area of the opening of the non-through hole. There is no increase in the area occupied by the through electrodes on the main surface of the semiconductor substrate, and the area of the main surface of the semiconductor substrate is not reduced. Therefore, the area where the surface electrode formed on the main surface of the semiconductor substrate can be formed does not change, the surface electrode can be miniaturized, and a semiconductor device having stable conductivity can be manufactured.

  After forming the non-through holes 24 as described above, the pattern mask 23 formed on the main surface of the semiconductor substrate 21 in which the non-through holes 24 are formed is peeled off as shown in FIG. 1A (b). The pattern mask 23 can be peeled off by a known method, for example, using a commercially available resist stripper. After the pattern mask 23 is peeled off, as shown in FIG. 1A (c), an insulating film forming step is performed in which a sidewall insulating film 26 is formed on the inner wall of the semiconductor substrate 21 facing the non-through hole 24.

  FIG. 5 is a diagram for explaining an insulating film forming process for forming the sidewall insulating film 26 by stencil printing. In the insulating film forming step shown in FIG. 5, an insulating material 32 is applied to the inner wall of the semiconductor substrate 21 facing the non-through hole 24 using a stencil printing method. In the insulating film forming process using the stencil printing method, first, the semiconductor substrate 21 is fixed on a printing stage provided in a chamber (not shown), and the center of the non-through hole 24 is the center of the mask opening of the printing mask 31. The positions of the printing mask 31 and the printing stage are adjusted so as to substantially match.

  The printing mask 31 is made of, for example, stainless steel having a thickness of 60 μm, and has a structure attached to a stainless steel plate frame via a tape and a screen, so that it can be elastically deformed. The mask opening of the printing mask 31 is formed in a cylindrical shape penetrating the printing mask 31 in the thickness direction, and the diameter of the opening is substantially equal to the diameter of the opening 24a of the non-through hole 24, for example, 40 μm. . The printing mask 31 is not limited to the metal mask made of stainless steel as described above, and may be a screen mask.

  Next, the height of the printing stage is adjusted so that the print mask 31 and the semiconductor element (not shown) formed on the semiconductor substrate 21 and the interlayer insulating film 22 do not come into contact with each other, and an interval of 10 to 200 μm is obtained. The insulating material 32 is supplied in the chamber, and the pressure in the chamber at this time is 1.0 kPa or more and 5.0 kPa or less which is lower than the atmospheric pressure (101.3 kPa) in this embodiment.

  The insulating material 32 used for printing is, for example, an epoxy resin such as a bisphenol A resin to which an aromatic amine curing agent or an acid anhydride curing agent is added, and silicon dioxide having an average particle diameter of about 5 μm is a filler. Can be used.

  Such an insulating material 32 is moved to the opening of the printing mask 31 by the squeegee 33. The squeegee 33 is made of, for example, urethane rubber, and is provided so that an inclination angle formed by the front end portion facing the print mask 31 and the print mask 31 is 45 °, for example. The squeegee 33 is not limited to the one made of urethane rubber, and may be made of other materials. Further, the inclination angle of the tip of the squeegee 33 facing the printing mask 31 is not limited to 45 °, and can be appropriately changed according to the type of the insulating material 32 and the like.

  Hereinafter, the insulating film forming process for forming the sidewall insulating film 26 by applying the insulating material 32 to the inner wall of the non-through hole 24 will be described with reference to FIG. In the present embodiment, the insulating film is formed on the inner wall and the bottom 24b of the non-through hole 24.

  First, the insulating material 32 is supplied onto the print mask 31, and the print mask 31 supplied with the insulating material 32 is lowered toward the semiconductor substrate 21 by the pressing force of the squeegee 33. Further, the squeegee 33 moves the insulating material 32 toward the opening of the printing mask 31.

  When the squeegee 33 passes through the opening of the non-through hole 24, the elastically deformable printing mask 31 is raised and separated from the semiconductor substrate 21. When the printing of the insulating material 32 is completed, the printing stage is lowered. At this time, as shown in FIG. 5A, the insulating material 32 remains in the opening of the non-through hole 32 due to the action of surface tension, and closes the opening of the non-through hole 32 in a cap shape. Here, the internal space 34 of the non-through hole 24 closed in a cap shape has a pressure lower than the atmospheric pressure.

  After supplying the insulating material 32 to the non-through hole 24 in this way, the pressure in the chamber is returned to atmospheric pressure. By returning the pressure in the chamber to the atmospheric pressure, the pressure in the inner space 34 of the non-through hole 24 closed by the insulating material 32 becomes smaller than the pressure in the chamber. Using the pressure difference, the insulating material 32 is sucked toward the bottom of the non-through hole 24 as shown in FIG. As described above, when the insulating material 32 is sucked into the non-through hole 24 due to the difference between the pressure in the chamber and the pressure in the internal space 34 of the non-through hole 24, the non-through hole 24 is formed without causing a void or the like. Insulating material 32 can be filled. Such filling of the non-through holes 24 with the insulating material 32 may be repeated a plurality of times according to the filling amount of the insulating material 32.

  When the non-through hole 24 is filled with the insulating material 32, the semiconductor substrate 21 with the non-through hole 24 filled with the insulating material 32 is put into an oven heated to a temperature higher than the curing temperature of the insulating material 32 (for example, about 150 ° C.). Then, the insulating material 32 is cured by heating for a predetermined time (for example, 1 hour). When the insulating material 32 is cured in this way, the volume after curing becomes 20 to 30% of the insulating material filled in the non-through hole 27 before being cured, as shown in FIGS. 1A (c) and 5 (c). As shown, a sidewall insulating film 26 is formed.

  Here, the reason for limiting the angle θ2 when the above-described non-through hole is formed will be described. When supplying and curing the insulating material 32, the insulating material 32 tends to flow toward the bottom 24 b of the non-through hole 24 through the inner wall of the non-through hole 24 due to its own weight. In addition, the surface area of the insulating material 32 that tends to flow toward the bottom of the non-through hole 24 and the insulating material that tries to stay on the inner wall of the non-through hole 24 are reduced by the surface tension of the insulating material 32. Retained.

  In the present embodiment, as shown in FIG. 3 described above, the angle θ2 formed by the normal unit vector va of the inner wall surface of the non-through hole 24 and the normal unit vector vb of the main surface of the semiconductor substrate 21 is 92 °. It is 120 degrees or less. That is, the inner wall of the non-through hole 24 approximated to a straight line in the cross-sectional view is formed so as to be inclined in the range of 92 ° to 120 ° with respect to the main surface of the semiconductor substrate 21. Therefore, the state in which the surface area of the insulating material 32 that tends to flow toward the bottom of the non-through hole 24 and the insulating material 32 that tries to stay on the inner wall of the non-through hole 24 is small is the non-penetration of the sidewall insulating film 26. This is achieved in a state where the surface facing the center of the hole 24 is substantially perpendicular to the main surface of the semiconductor substrate 21.

  Therefore, as described above, when the normal unit vector of the inner wall surface of the non-through hole 24 is va and the normal unit vector of the main surface of the semiconductor substrate 21 is vb, the non-through hole 24 has a relationship between va and vb. The inner product is preferably formed to be −0.5 or more and −0.034 or less.

  Here, when θ2 is smaller than 92 °, that is, when the inner product of va and vb is larger than −0.034, the surface of the side wall insulating film 26 facing the center of the non-through hole 24 is formed on the semiconductor substrate 21. As compared with the normal line of the main surface, the bottom portion 24b of the non-through hole 24 is inclined toward the center side. On the other hand, when θ2 exceeds 120 °, that is, when the inner product of va and vb is less than −0.5, the surface of the side wall insulating film 26 facing the center of the non-through hole 24 is the main surface of the semiconductor substrate 21. Compared with the normal of the surface, the bottom 24b of the non-through hole 24 is inclined toward the peripheral side.

  After the sidewall insulating film 26 is formed as described above, the conductor 35 serving as the material of the through electrode 27 is filled in the non-through hole 24 in which the sidewall insulating film 26 is formed as shown in FIG. Then, a conductor filling step for obtaining the conductive plug 35a is performed.

  The conductive plug 35 a formed by being filled with the conductor 35 is exposed at the end facing the bottom 24 b of the non-through hole 24 by a process described later, and becomes a through electrode 27 that penetrates the semiconductor substrate 21. In the present invention, the conductive plug that is in a state of penetrating through the semiconductor substrate is commonly referred to as a through electrode in the present invention.

  FIG. 6 is a diagram for explaining an outline of an example of the conductor filling step. In FIG. 6A, in order to form the through electrode 27, the conductor 35 is filled into the gap inside the non-through hole 24 in which the sidewall insulating film 26 is formed. As the conductor 35, for example, a metal ball such as silver having a particle diameter of about several μm to several tens of μm is used. A metal ball is embedded in the void inside the non-through hole 24 and heat treatment is performed at a temperature of about 160 ° C., whereby the conductor 35 is placed in the non-through hole 24 in which the sidewall insulating film 26 is formed as shown in FIG. The conductive plug 35a is formed by filling.

  When the conductor 35 is filled in the gap inside the non-through hole 24 in which the side wall insulating film 26 is formed in this way, the surface of the side wall insulating film 26 facing the center of the non-through hole 24 is substantially perpendicular to the main surface of the semiconductor substrate 21. It becomes. Therefore, the conductive plug 35 a has substantially the same area in the virtual plane including the opening 24 a of the non-through hole 24 and the area in the virtual plane including the bottom 24 b of the non-through hole 24.

  Next, as shown in FIG. 1B (e), a through hole forming step is performed in which the back surface of the semiconductor substrate 21 on which the conductive plug 35a is formed is retracted until the conductive plug 35a is exposed to the outside. In the present embodiment, since the depth of the non-through hole 24 is about 100 μm, in the through hole forming step, the thickness of the semiconductor substrate 21 is set to about 80 μm by backside grinding to expose the conductive plug 35a to the outside. An electrode 27 is formed.

  As a method for retracting the back surface of the semiconductor substrate, a known method can be used. As a method for performing the through hole forming step, for example, a dry etching method such as a reactive ion etching method or a plasma etching method, a wet etching method using hydrofluoric acid or nitric acid, a mechanical polishing method, or the like can be used. A combination of these techniques can also be used.

  As described above, the through electrode 27 formed by exposing the conductive plug 35a to the outside of the semiconductor substrate 21 has an area in a virtual plane including the main surface, which is one surface of the semiconductor substrate 21, and the semiconductor substrate. The area on the virtual plane including the back surface which is the other surface of 21 is substantially equal. In such a through electrode 27, since the exposed area is substantially equal between the main surface and the back surface, it is possible to prevent an increase in the resistance value of the through electrode 27 due to the difference in the exposed area between the main surface and the back surface. it can. Even when a plurality of through electrodes 27 are formed, there is no variation in the exposed area of the through electrodes 27 between the electrodes. Therefore, by using the through electrode forming method of the present invention, it is possible to form a through electrode having excellent conductivity and having no variation in conductivity between a plurality of electrodes.

  Even if the depth at which the non-through hole is formed is small, there is no variation in the exposed area of the through electrode 27 between the electrodes. Therefore, even when a thick semiconductor substrate is used, it is not necessary to dig deeply into the non-through hole, so that the manufacturing time can be shortened and the manufacturing cost can be prevented from increasing.

  Here, the shape of the non-through hole 24 is not limited to the truncated cone shape as shown in FIGS. 3 and 4 and may be other shapes. For example, the non-through hole may have a bottom and an opening formed in a rectangular shape.

  FIG. 7 is a cross-sectional view of a semiconductor substrate 42 in which a non-through hole 41 in which a bottom 41a and an opening 41b are formed in a rectangular shape, and FIG. 8 mainly shows the semiconductor substrate 42 in which the non-through hole 41 is formed. It is the top view seen from the surface side. In the non-through hole 41, the opening 41a and the bottom 41b are formed in a substantially square shape, and the length xb of one side of the bottom 41b is longer than the length xa of one side of the opening 41a. Therefore, the non-through hole 41 is formed such that the area of the bottom 41b is larger than the area of the opening 41a.

  Exemplifying the size of the non-through hole 41, the length xa of one side of the opening 41a is 40 μm, the length xb of one side of the bottom 41b is 49 μm, and the depth d is 100 μm. When the non-through hole 41 having such a size is formed, the normal unit vector va of the surface connecting the peripheral portion of the bottom 41b of the non-through hole 41 and the peripheral portion of the opening 41a of the non-through hole 41, and the semiconductor substrate 42 main The inner product of the surface with the normal unit vector vb is −0.045 (θ2 = 92.6 °).

  Thus, the shape of the bottom of the non-through hole is not limited to being formed in a truncated cone shape, and may be formed in another shape. However, when an insulating material is applied to the inner wall of the non-through hole whose bottom is formed in a rectangular shape, a large amount of the insulating material may be deposited at the corners of the rectangular bottom. A surface of the side wall insulating film formed of an insulating material that faces the center of the non-through hole is formed in the vicinity of the corner portion of the bottom portion so as to be closer to the center than the portion other than the corner portion. In such a case, the surface facing the center of the non-through hole of the side wall insulating film in the vicinity of the bottom may be inclined toward the center of the bottom of the non-through hole compared to the normal line of the main surface of the semiconductor substrate. When such a non-through hole is filled with a conductor to form a through electrode, the size of the through electrode exposed on the main surface of the semiconductor substrate may be different from the size of the through electrode exposed on the back surface. is there. Therefore, it is most preferable that the bottom of the non-through hole is formed in a shape having no corners, that is, a substantially circular shape. In the present invention, the substantially circular shape includes a circular shape.

  Further, the supply of the insulating material 32 to the non-through holes 24 is not limited to the method using the stencil printing method as shown in FIG. 5 described above. It may be done. The formation of the sidewall insulating film 26 is not limited to the method using the pressure difference between the inside of the chamber and the internal space 34 as described above.

  FIG. 9 is a diagram illustrating an insulating film forming process for forming the sidewall insulating film 26 by a spray method. In the spray method, an insulating film is formed on the inner wall of the non-through hole 24 by applying a particulate insulating material 52 into the non-through hole 24 using the spray 51 from above the main surface of the semiconductor substrate 21. The nozzle diameter of the spray 51 is preferably about 1 to 2 mm, and the particle diameter of the particulate insulating material 52 is preferably about 5 μm. The distance h between the spray 51 and the main surface of the semiconductor substrate 21 is preferably about 30 to 100 mm.

  The particulate insulating material 52 enters the bottom of the non-through hole 24 through the inner wall of the non-through hole 24 and is deposited from the peripheral edge of the bottom of the non-through hole 24. Here, since the area of the bottom 24b of the non-through hole 24 is larger than the area of the opening 24a, the surface of the sidewall insulating film 26 formed by the insulating material 52 supplied by the spray 51 faces the center of the non-through hole 24. It is substantially perpendicular to the main surface of the semiconductor substrate 21.

  However, when the insulating material 32 is supplied to the non-through holes 24 by the stencil printing method as shown in FIG. 5, the insulating material to the fine non-through holes 24 having a diameter of about 40 μm. The supply of 32 can be performed easily and economically. Further, since the supply amount of the insulating material 32 can be easily controlled, the accuracy of the film thickness of the sidewall insulating film 26 to be formed can be increased. Therefore, the stencil printing method is preferably used for supplying the insulating material to the non-through holes.

  Further, the method of performing the conductor filling step is not limited to the method of embedding the metal ball in the gap inside the non-through hole 24, and other known methods can also be used. As a method for filling the conductor, for example, a CVD method, a plating method, or the like can be used. Further, similarly to the insulating film forming step shown in FIG. 5, a paste such as silver or copper can be filled by stencil printing. When the pressure difference between printing and filling is used by using the stencil printing method, the conductive plug 35a containing no voids can be formed.

  When the through electrode 27 is formed by using the through electrode forming method of the present invention as described above, as shown in FIG. 1B (f), an insulating film for forming a back surface insulating film 28 on the back surface of the semiconductor substrate 21. A forming step is performed. The insulating film forming step can be performed using a known method, and a diagram for explaining the outline thereof is omitted. In the insulating film forming step, for example, a back surface insulating film material such as silicon dioxide is applied to the entire back surface of the semiconductor substrate 21 and patterned by photolithography so as to open a portion of the through electrode 27, and then the remaining photoresist. The back insulating film 28 is formed by performing ashing for removing the substrate, baking the substrate, and drying the semiconductor substrate 21.

  When the back surface insulating film 28 is formed, as shown in FIG. 1B (g), the back surface wiring 29 for electrically connecting the through electrode 27 and the external circuit is formed by, for example, a plating method. In the back surface wiring formation step by plating, a conductive film is formed on the back surface of the semiconductor substrate 21 by sputtering using a conductive material, a plating resist is applied on the conductive film, and the plating resist remains on portions other than the wiring pattern. To pattern. Next, backside wiring plating is performed in which the wiring pattern portion, which is a portion where no plating resist is formed, is plated by electric field plating or the like. Thereafter, the plating resist is stripped by a stripping method using a stripping solution such as an alkaline stripping solution, and the exposed conductive film is removed by etching, whereby the back surface wiring 29 is formed. As described above, the semiconductor device of the present invention is manufactured.

  FIG. 10 is a schematic cross-sectional view showing a multichip semiconductor device 61 obtained by stacking semiconductor devices 62 manufactured by the manufacturing method of the present invention. The semiconductor device 62 of the present invention manufactured as described above is laminated using bump electrodes 63 formed by plating or the like using backside wiring, and electrical connection between the semiconductor devices 62 is performed, so that a multichip semiconductor is provided. A device 61 is formed. Here, the bump electrode 63 is not limited to being formed immediately below the through electrode 27.

  FIG. 11 is a diagram showing a method of forming the bump electrode 11 without using the back surface wiring. The electrical connection between the semiconductor devices 62 is not limited to being performed by forming the bump electrode 63 after forming the back surface wiring 29. For example, a method of forming the bump electrode 73 on the back surface of the semiconductor substrate 21 without forming the back surface wiring 29 as in the method shown in FIG. In such a method, a support glass 71 and a protective tape 72 as shown in FIG. 11A are used instead of performing the back surface wiring forming step shown in FIG. 1B (g). The support glass 71 is made of, for example, quartz glass, and improves the handleability of the thinned semiconductor device by back grinding. A conductive paste is embedded in the protective tape 72, and a bump electrode 73 can be formed on the back side of the semiconductor substrate as shown in FIG. 11B by electroplating using the protective tape 72 as a power feeding layer. The bump electrode 73 may be formed by electroless plating.

  The multichip semiconductor device obtained by stacking and connecting the semiconductor devices of the present invention as described above is a multichip semiconductor device in which a plurality of semiconductor devices having the semiconductor substrate 21 thinned to about 100 μm are stacked. Can greatly contribute to space saving. As a result, it can greatly contribute to the improvement of the performance of an electronic device, for example, a portable information device, on which the multichip semiconductor device is mounted.

It is a figure for demonstrating the outline | summary of the manufacturing method of the semiconductor device which is 1 aspect of this invention. It is a figure for demonstrating the outline | summary of the manufacturing method of the semiconductor device which is 1 aspect of this invention. 5 is a diagram illustrating a method for forming a non-through hole 24. FIG. It is sectional drawing of the semiconductor substrate 21 which has the non-through-hole 24 formed in the truncated cone shape by the method shown in FIG. FIG. 3 is a plan view of a semiconductor substrate 21 having a non-through hole 24 as viewed from the main surface side. It is a figure explaining the insulating film formation process which forms the side wall insulating film 26 by the stencil printing method. It is a figure explaining the outline | summary of an example of a conductor filling process. It is sectional drawing of the semiconductor substrate 42 in which the non-through-hole 41 in which the bottom part 41a and the opening part 41b are formed in a rectangular shape is formed. It is the top view which looked at the semiconductor substrate 42 in which the non-through-hole 41 is formed from the main surface side. It is a figure explaining the insulating film formation process which forms the side wall insulating film 26 by the spray method. It is a schematic sectional drawing which shows the multichip semiconductor device 61 obtained by laminating | stacking the semiconductor device 62 manufactured by the manufacturing method of this invention. It is a figure which shows the method of forming the bump electrode 11 without using a back surface wiring. 2 is a cross-sectional view schematically showing an example of a configuration of a multichip semiconductor device 1. FIG. It is a figure explaining the method of forming insulating film 13a, 13b and penetration electrode 14a, 14b in non-through-hole 11a, 11b.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Semiconductor substrate 22 Interlayer insulating film 23 Pattern mask 24 Non-through-hole 24a Non-through-hole opening 24b Non-through-hole bottom 25 Protective film 26 Side wall insulating film 27 Through-electrode 28 Back surface insulating film 29 Back surface wiring 35 Conductor 35a Conductive plug

Claims (5)

In the formation method of the through electrode penetrating the substrate,
A non-through hole forming step of forming a non-through hole having an opening on one surface of the substrate and having a bottom inside the substrate;
An insulating film forming step of forming an insulating film on the inner wall of the substrate facing the non-through hole;
A conductor filling step of filling a non-through hole in which an insulating film is formed with a conductor;
A through hole forming step of retracting the other surface of the substrate until the conductor is exposed to the outside,
Non-through holes are
A method of forming a through electrode, wherein the area of the substrate facing the bottom of the non-through hole is larger than the area of the opening. Non-through holes are
2. The method for forming a through electrode according to claim 1, wherein the surface of the substrate facing the bottom of the non-through hole is formed in a substantially circular shape. Non-through holes are
A vector directed from the inner wall of the substrate facing the non-through hole to the inside of the non-through hole, and in a virtual cross section perpendicular to one surface of the substrate, the bottom peripheral edge of the non-through hole, and the bottom peripheral edge of the non-through hole A normal unit vector of a virtual plane connecting the peripheral edge of the opening of the non-through hole on the inner wall surface of the substrate formed in a row,
A vector directed outward from one surface of the substrate, wherein an inner product with a normal unit vector of one surface of the substrate is −0.5 or more and −0.034 or less. The method of forming a through electrode according to claim 1 or 2.   The manufacturing method of the semiconductor device using the formation method of the penetration electrode as described in any one of Claims 1-3. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 4,
A through electrode penetrating the semiconductor substrate from one surface, which is a surface on which the semiconductor element is formed, of the semiconductor substrate toward the other surface opposite to the one surface;
Including an insulating film provided between the through electrode and the semiconductor substrate,
Insulating film
The cross-sectional area in a virtual plane perpendicular to the thickness direction of the semiconductor substrate increases as it goes from one surface of the semiconductor substrate to the other surface,
The through electrode is
A semiconductor device, wherein an area on a virtual plane including one surface of a semiconductor substrate is substantially equal to an area on a virtual plane including the other surface of the semiconductor substrate.

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