JP2006065396A - Memory management device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory management system capable of improving reliability against a memory failure. <P>SOLUTION: An FPGA 10 stores a memory management table 12 for managing an access destination of a memory 20 holding at least one of a program and data, a memory failure detection part 13 detecting a failure of the memory 20, an alternative memory 15 holding at least one of the program and the data, and a table update part 14 changing the access destination in the memory management table 12 to the alternative memory 15 if a memory failure is detected by the memory failure detection part 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory management apparatus that detects a memory failure when a computer system is provided with a volatile memory such as a DRAM and restores it to a normal state that does not hinder the operation of software.

  Conventionally, for example, when a BIOS (Basic Input Output System) or the like is loaded into a memory such as a DRAM at the time of system startup, if a failure occurs in a part of the memory, it is loaded into an area where no memory failure has occurred. There was something like that (see, for example, Patent Document 1).

JP 2001-67229 A

  However, in a conventional memory management device, for example, when a failure occurs in a memory controller that controls the memory, the memory itself cannot be accessed. Therefore, when such a situation occurs, there is a problem that the BIOS or the like cannot be loaded into the memory from an external flash memory or the like.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a memory management system capable of improving reliability against a memory failure.

  A memory management device according to the present invention detects a memory failure and a memory management table for managing an access destination of a memory holding at least one of a program and data in a variable integrated circuit having an arithmetic processing function. A memory failure detection unit, a replacement memory holding at least one of a program and data, and a table update unit that changes an access destination in the memory management table to a replacement memory when a memory failure is detected by the memory failure detection unit; It is equipped with.

  In the memory management device of the present invention, an alternative memory is provided in a variable integrated circuit having an arithmetic processing function, and when the memory failure detection unit detects a memory failure, the access destination is changed to the alternative memory. Therefore, the reliability against memory failure can be improved.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram showing a memory management system according to Embodiment 1 of the present invention.
The illustrated memory management device includes an FPGA (field programmable gate array) 10, a memory 20, and a flash memory 30, and these configurations are provided on the CPU board 1. The FPGA 10 is a variable integrated circuit having an arithmetic processing function, and includes a memory controller 11, a memory management table 12, a memory failure detection unit 13, a table update unit 14, an alternative memory 15, and a processor 16.

  The memory controller 11 is a control unit that controls the memory 20. The memory management table 12 is a management table for storing the configuration of the memory 20 and managing the access destination of the memory 20. The memory failure detection unit 13 is a functional unit that detects a failure of the memory 20. The table update unit 14 is a functional unit that updates the memory management table 12. That is, the table update unit 14 has a function of setting the access destination in the memory management table 12 in the alternative memory 15 when a memory failure is detected by the memory failure detection unit 13. The alternative memory 15 is, for example, a memory composed of a DRAM similar to the memory 20, and is a memory for holding at least one of a program and data similarly to the memory 20. The processor 16 is a processor provided in the FPGA 10 and has a function of performing processing such as initialization processing of the memory 20 and loading processing of the BIOS from the flash memory 30 to the memory 20.

  The memory 20 is a memory for holding at least one of a program and data composed of, for example, a DRAM or the like, and includes a plurality of banks (eight banks in the illustrated example). The management of the memory 20 such as failure detection in the memory failure detection unit 13 is performed for each bank. The flash memory 30 is a memory for storing software such as BIOS. In the illustrated example, eight banks are illustrated as a plurality of banks in the memory 20, but the present invention is not limited to this value.

Next, the operation will be described.
FIG. 2 is a flowchart showing the operation of the first embodiment.
When the system is started, the memory 20 is first reset (step ST1). Next, the table updating unit 14 sets an initial value 0 to the bank number indicating the bank being processed in the memory 20 (step ST2), and the processor 16 initializes the bank 0 in the memory 20 via the memory controller 11. (Step ST3). When the system is activated, the memory failure detection unit 13 detects a failure in each bank in the memory 20 (step ST4). That is, the memory failure detection unit 13 monitors an access state to the memory 20 by the processor 16.

  In step ST4, if the memory failure detection unit 13 does not detect a memory failure, the table update unit 14 increments the bank number of the memory management table 12 (step ST5), and if the bank number is less than 8 (step ST6). Returning to step ST3, the processor 16 proceeds to the initialization process for the next bank. On the other hand, if the memory failure detection unit 13 detects a failure in any of the memory banks in step ST4, the table update unit 14 replaces the bank number of the failed memory bank with the alternative memory 15 (step ST7), and memory management The table 12 is updated (step ST8). As a result, the processor 16 initializes the replaced alternative memory 15.

  In addition, after the initialization process of the memory 20, the processor 16 loads the BIOS from the flash memory 30 to the memory 20, and also when the memory failure detection unit 13 detects a failure in any of the memory banks, Similarly to the operation, the table update unit 14 changes the memory management table 12 to an address corresponding to the alternative memory 15. As a result, the processor 16 loads the BIOS into the replacement memory 15 replaced from the flash memory 30 and thereafter accesses the replacement memory 15 instead of the memory bank in which the failure in the memory 20 has occurred.

  As described above, according to the first embodiment, a memory management table for managing an access destination of a memory that holds at least one of a program and data, a memory failure detection unit that detects a memory failure, a program, A variable memory having an arithmetic processing function, an alternative memory that holds at least one of data, and a table update unit that changes an access destination in the memory management table to an alternative memory when a memory failure is detected by the memory failure detection unit Therefore, it is possible to prevent the occurrence of an inaccessible state to the memory caused by an external memory controller as in the past, and as a result, to improve the reliability against a memory failure. Can do.

  Further, according to the first embodiment, since the variable integrated circuit having the arithmetic processing function is a field programmable gate array, the reliability against a memory failure can be further improved.

It is a block diagram which shows the memory management apparatus by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of Embodiment 1 of this invention.

Explanation of symbols

  10 field programmable gate array (FPGA), 12 memory management table, 13 memory failure detection unit, 14 table update unit, 15 alternative memory, 20 memory.

Claims (2)

A memory management table for managing an access destination of a memory holding at least one of a program and data;
A memory failure detection unit for detecting a failure of the memory;
An alternative memory for holding at least one of program and data;
Memory management provided in a variable integrated circuit having an arithmetic processing function, and a table updating unit that changes an access destination in the memory management table to the alternative memory when a memory failure is detected by the memory failure detection unit apparatus.   The memory management device, wherein the variable integrated circuit having an arithmetic processing function is a field programmable gate array.

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