JP2006020119A - Pull-down detection circuit - Google Patents

Pull-down detection circuit Download PDF

Info

Publication number
JP2006020119A
JP2006020119A JP2004196514A JP2004196514A JP2006020119A JP 2006020119 A JP2006020119 A JP 2006020119A JP 2004196514 A JP2004196514 A JP 2004196514A JP 2004196514 A JP2004196514 A JP 2004196514A JP 2006020119 A JP2006020119 A JP 2006020119A
Authority
JP
Japan
Prior art keywords
pull
frame
reference value
determination
sensitivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004196514A
Other languages
Japanese (ja)
Inventor
Yasushi Ito
Seiji Matsunaga
Junichi Onodera
靖 伊藤
純一 小野寺
誠司 松永
Original Assignee
Fujitsu General Ltd
株式会社富士通ゼネラル
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, 株式会社富士通ゼネラル filed Critical Fujitsu General Ltd
Priority to JP2004196514A priority Critical patent/JP2006020119A/en
Publication of JP2006020119A publication Critical patent/JP2006020119A/en
Application status is Withdrawn legal-status Critical

Links

Images

Abstract

PROBLEM TO BE SOLVED: To optimize determination sensitivity of a 24-frame source video signal included in a 60-frame interlace signal.
SOLUTION: A total time DT in which a 24 frame determination signal C output from a 24 frame determination circuit 10 is “1” (24 frame source determination) in the past 30 seconds is detected, and a sensitivity reference value is set according to the time DT. The sensitivity reference value REF of the comparator 13 is determined by the circuit 20. If the time DT is large, the REF is decreased, and if the time DT is small, the REF is increased.
[Selection] Figure 1

Description

  The present invention detects whether or not a currently input 60-frame interlace (hereinafter referred to as “60-frame interlace”) video signal such as NTSC, 480I, and 1080I is a pull-down video signal. The present invention relates to a pull-down detection circuit.

  When converting 24 frames per second film image to 60 frames interlace format, one frame is read twice for odd field and even field, and the next one frame is for odd field, even field, odd This is performed by reading three times for the field and repeating this (2-3 pull-down processing). Also, when converting 30 frames of film video per second to 60 frames interlace format, one frame is read twice for odd field and even field, and this is repeated (2-2 pull-down processing). Is called.

  On the other hand, since the plasma display device (PDP device) performs progressive scanning, when displaying 60 frames of interlaced video on the PDP device, 60 frames per second of 60 frames of interlaced field signal. Progressive scanning conversion (IP conversion: interlace → progressive conversion) is required to convert the signal into a frame signal of 60 frames per second.

  In this IP conversion, a frame signal of 60 frames per second can be obtained by double-speed converting a field signal of 60 frames per second and superimposing the images of the two fields before and after at 1/60 seconds. When the superposition is performed in the odd field and the even field set from the same frame, it can be converted into a progressive scanning signal having the same image quality as the original image.

  Therefore, in an IP converter that converts a 60-frame interlaced signal including a 24-frame source or 30-frame source video signal and a normal video signal into a sequentially scanned frame signal, the current field signal is a 24-frame source video signal. It is necessary to detect whether the video signal is a 30-frame source video signal, that is, whether the video signal is pulled down.

  A circuit for detecting a video signal of 24 frame source or 30 frame source as described above is called a pull-down detection circuit. By incorporating such a pull-down detection circuit in the IP converter, IP conversion corresponding to the source of the input signal can be performed.

  The pull-down detection circuit described above normally has an on / off setting, and when it is set to on, the source of the input signal is automatically determined to determine whether or not to perform pull-down detection processing. In order to determine the source of the input signal, the magnitude of the inter-field difference value is used, but in order to reduce error detection as much as possible, the determination sensitivity is set so as not to perform pull-down processing on a suspicious image. This is because when the input signal source is other than the 24-frame source or the 30-frame source, pull-down processing may result in an unsightly video such as a comb.

After the determination sensitivity is once determined to be pull-down, the determination sensitivity is switched to provide a hysteresis characteristic so that the determination is difficult to deviate (see, for example, Patent Document 1), the noise level of the input source, and other conditions The determination sensitivity is switched by (see, for example, Patent Document 2).
JP-A-4-72966 Japanese Patent Laid-Open No. 2003-17984

  However, even when there is no noise or the like in the 24-frame source or 30-frame source video, when the still image scene or the dark scene continues, the inter-field difference value becomes small and pull-down detection may not be performed.

  For example, if the input video signal is a DVD video (24-frame source), it is desirable to perform pull-down processing on the entire program. However, since the normal pull-down detection circuit determines the size of the difference value between the fields, the 24-frame source cannot be detected if the change in the difference value between the fields becomes small, such as an image with little motion or a dark image. There is. Furthermore, since this determination is performed only in the current input state, it is difficult to determine whether or not the DVD video continues thereafter.

  An object of the present invention is to provide a pull-down detection circuit that solves the above-described problems by enabling the determination sensitivity of pull-down detection to be adjusted according to the pull-down determination result within a predetermined time in the past.

  A pull-down detection circuit according to a first aspect of the present invention includes a pull-down determination circuit that activates a pull-down determination signal when the input 60-frame interlace signal is a 24-frame source or 30-frame source video signal, And a sensitivity reference value setting circuit for setting a sensitivity reference value of the pull-down determination circuit by detecting a total time when the pull-down determination signal is active.

  According to a second aspect of the present invention, in the pull-down detection circuit according to the first aspect, the sensitivity reference value setting circuit has a high determination sensitivity of the pull-down determination circuit when the total time during which the determination signal is active is large. The sensitivity reference value is set such that the sensitivity reference value is set to be low when the total time is small.

  According to a third aspect of the present invention, in the pull-down detection circuit according to the first or second aspect, the sensitivity reference value setting circuit is configured such that when the current pull-down determination signal is active, the total time is less than the predetermined time. The total time is added by one unit time. When the total time is other than 0 when inactive, the unit is subtracted by one unit time, and the sensitivity reference value is set according to the total time.

  According to the pull-down detection circuit of the present invention, since the pull-down determination sensitivity is adjusted according to the total time that the pull-down determination signal within the past predetermined time is active, the past pull-down determination result can be effectively reflected. It is possible to make a judgment by predicting the subsequent source according to the past source. In addition, as described above, even when a still image scene or dark scene follows a 24-frame source or 30-frame source video, and the difference value between fields becomes small and pull-down detection is difficult, pull-down detection is performed with high sensitivity. It can be easily broken.

  In the present invention, it is determined whether or not the same source video continues in the future based on the pull-down determination result within a certain period of time from the present time, and the determination sensitivity is adjusted to make it easy or difficult to detect the pull-down.

  FIG. 1 is a block diagram of a pull-down detection circuit for 24 frames according to one embodiment of the present invention. Reference numeral 10 denotes a 24-frame determination circuit, which includes a 24-frame detection circuit 11, an up-down counter 12 that functions as an integration circuit, and a comparator 13. The 24-frame detection circuit 11 detects / non-detects a 24-frame source by inputting a 60-frame interlaced field signal A and detecting a difference between the fields. In the case of a 24-frame source field signal, a pattern in which “1” is output once in 5 fields and “0” is output in other fields can be detected. Therefore, the value obtained by adding the detection signals for the previous 5 fields is “1”. ”Is detected and determined to be a 24 frame source, and other sources are other sources, so that the 24 frame detection signal B is set to“ 1 ”when it is a 24 frame source, and is set to“ 0 ”when it is not detected.

  The 24-frame detection signal B is output for each field. When it is “1”, the counter 12 is counted up, and when it is “0”, it is counted down. In this counter 12, “1” is counted once per time, but “0” is counted once per time, for example, 10 times, so that the downcount is weighted with respect to the upcount. It is attached. As a result, when the 24-frame source is continuously detected, the counter 12 continues to count up and finally counts up to the maximum count value, but when the 24-frame source is not detected, the count value is rapidly increased. Decrease and finally count down to zero.

  The count value of the counter 12 is compared with the sensitivity reference value REF in the comparator 13. When the count value is larger than the sensitivity reference value REF, the 24-frame determination signal C indicates “1” (active), and when not, “0”. (Inactive).

  Therefore, if the sensitivity reference value REF is made small, the 24-frame determination signal C is stable even when the 24-frame detection signal B shows “1” over a long period and sometimes “0” due to noise or the like. Therefore, “1” is indicated, and the filter function for preventing the detection failure of the 24-frame source is exhibited, and the determination sensitivity of the 24-frame source is increased. However, when the 24-frame detection signal B continues to indicate “0”, the 24-frame determination signal C is rapidly set to “0”. If the sensitivity reference value REF is increased, the filter function is weakened, and the 24-frame determination signal C is unlikely to be “1”, that is, the determination sensitivity of the 24-frame source is lowered.

  Reference numeral 20 denotes a sensitivity reference value setting circuit for setting the sensitivity reference value REF. The sensitivity reference value REF is determined depending on how much time the 24-frame determination signal C is “1” over the past T1, for example, T1. To decide. As shown in FIG. 2, when the period when the 24-frame determination signal C is “1” is ◯, the period when it is “0” is x, and the period of T1 is 30 seconds, the total period of ◯ is 0. The sensitivity reference value is set to REF = R1 in the range of 10 to 10 seconds, REF = R2 in the range of 11 to 20 seconds, and REF = R3 in the range of 21 to 30 seconds. R1, R2, and R3 have a relationship of R1> R2> R3.

  From the above, the sensitivity reference value REF becomes smaller and the sensitivity becomes higher as the time when the 24-frame determination signal C indicates “1” in the past becomes longer, and the 24-frame determination signal C is continuously output. For this reason, when a 24-frame source field signal is being input, even if the 24-frame source video continues slightly in a still image or a dark scene, a situation in which the 24-frame determination signal C becomes “0” is prevented. it can.

  FIG. 3 is a flowchart of processing of the sensitivity reference value setting circuit 20. This process is executed at intervals of 1 second. First, it is determined in step S1 whether or not the current 24-frame determination signal C is “1”. If it is “0”, the time DT when the 24-frame determination signal C becomes “1” in the past 30 seconds. Is determined at step S4, and when DT = 0, the sensitivity reference value is set to R1 at step S6. As long as the 24-frame determination signal C is “0”, this is repeated every second, and the sensitivity reference value does not change from R1.

  If the 24-frame determination signal C becomes “1” when one second has passed, the process proceeds from step S1 to step S2. At this time, since DT ≠ 30, 1 is added to the current DT (= 0) in step S3. This is because the current 24-frame determination signal C is “1”. At this time, DT = 1, and the sensitivity reference value does not change from R1 in step S6.

  Thereafter, the above process is repeated as long as the 24-frame determination signal C indicates “1”. If DT ≦ 10, the sensitivity reference value remains R1, but if 11 <DT ≦ 20, the sensitivity reference value becomes R2. If 21 <DT, it becomes R3.

  On the other hand, when the 24-frame determination signal C is changed from “1” to “0”, the process proceeds from step S1 to step S2. Here, since DT ≠ 0, 1 is subtracted from the current DT, and the sensitivity reference value is set to one of R1 to R3 in step S6 or S7 for this subtraction result. In the above description, the DT maximum value is 30 (step S2) and the minimum value is 0 (step S4).

  In the above description, the 24-frame pull-down detection circuit for detecting whether or not the currently input field signal is a 24-frame source has been described. However, the 30-frame pull-down detection circuit is the 24-frame detection circuit 11 of FIG. Is replaced with a 30-frame detection circuit.

It is a block diagram of a pull-down detection circuit for 24 frames of the present embodiment. It is explanatory drawing for the sensitivity reference value setting of a present Example. It is a flowchart of a sensitivity reference value setting process.

Explanation of symbols

10: 24 frame determination circuit, 11: 24 frame detection circuit, 12: Counter, 13: Comparator 20: Sensitivity standard value setting circuit

Claims (3)

  1.   A pull-down determination circuit that activates a pull-down determination signal when the input 60-frame interlace signal is a 24-frame source or 30-frame source video signal, and a total time that the pull-down determination signal is active within a predetermined past time from the present time And a sensitivity reference value setting circuit for setting a sensitivity reference value of the pull-down determination circuit.
  2. The pull-down detection circuit according to claim 1.
    The sensitivity reference value setting circuit sets the sensitivity reference value so that the determination sensitivity of the pull-down determination circuit is high when the total time when the determination signal is active is large, and when the total time is small, the sensitivity reference value setting circuit sets the sensitivity reference value. A pull-down detection circuit, wherein the sensitivity reference value is set so that the determination sensitivity becomes low.
  3. The pull-down detection circuit according to claim 1 or 2,
    The sensitivity reference value setting circuit adds the total time by one unit time when the total time is less than the predetermined time when the current pull-down determination signal is active, and the total time is other than 0 when the total time is inactive. In this case, the sensitivity reference value is set in accordance with the total time by subtracting one unit time.
JP2004196514A 2004-07-02 2004-07-02 Pull-down detection circuit Withdrawn JP2006020119A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004196514A JP2006020119A (en) 2004-07-02 2004-07-02 Pull-down detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004196514A JP2006020119A (en) 2004-07-02 2004-07-02 Pull-down detection circuit

Publications (1)

Publication Number Publication Date
JP2006020119A true JP2006020119A (en) 2006-01-19

Family

ID=35793930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004196514A Withdrawn JP2006020119A (en) 2004-07-02 2004-07-02 Pull-down detection circuit

Country Status (1)

Country Link
JP (1) JP2006020119A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7728908B2 (en) 2008-06-27 2010-06-01 Kabushiki Kaisha Toshiba Pull-down signal detecting apparatus, pull-down signal detecting method, and interlace-progressive converter
JP2012100181A (en) * 2010-11-05 2012-05-24 Hitachi Consumer Electronics Co Ltd Image output device, image output method, receiver, and reception method
US8203650B2 (en) 2006-10-31 2012-06-19 Kabushiki Kaisha Toshiba Pull-down signal detecting apparatus, pull-down signal detecting method, and video-signal converting apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8203650B2 (en) 2006-10-31 2012-06-19 Kabushiki Kaisha Toshiba Pull-down signal detecting apparatus, pull-down signal detecting method, and video-signal converting apparatus
US7728908B2 (en) 2008-06-27 2010-06-01 Kabushiki Kaisha Toshiba Pull-down signal detecting apparatus, pull-down signal detecting method, and interlace-progressive converter
JP2012100181A (en) * 2010-11-05 2012-05-24 Hitachi Consumer Electronics Co Ltd Image output device, image output method, receiver, and reception method

Similar Documents

Publication Publication Date Title
KR100563866B1 (en) Apparatus and method for deinterlace of video signal
US7265791B2 (en) Method and apparatus for de-interlacing video signal
EP0757482B1 (en) An edge-based interlaced to progressive video conversion system
US7095445B2 (en) Method of detecting motion in an interlaced video sequence based on logical operation on linearly scaled motion information and motion detection apparatus
US7079159B2 (en) Motion estimation apparatus, method, and machine-readable medium capable of detecting scrolling text and graphic data
JP2693721B2 (en) Interlaced / progressive scanning conversion method and a video signal processing apparatus to which it has a double smoothing function
EP1158792B1 (en) Filter for deinterlacing a video signal
US6396543B1 (en) Deinterlacing apparatus of digital image data
EP0830018A2 (en) Method and system for motion detection in a video image
US5784115A (en) System and method for motion compensated de-interlacing of video frames
US6795123B2 (en) Interpolation apparatus, and video signal processing apparatus including the same
EP0790736B1 (en) Edge-oriented intra-field/inter-field interpolation filter for improved quality video appliances
US20060023119A1 (en) Apparatus and method of motion-compensation adaptive deinterlacing
JP2004064788A (en) Deinterlacing apparatus and method
EP0549471A1 (en) Motion detection and estimation apparatus and method thereof
JP4513819B2 (en) Video conversion device, video display device, and video conversion method
EP1353509B1 (en) Stillness judging device and scanning line interpolating device having it
US7202907B2 (en) 2:2 and 3:2 pull-down detection techniques
KR940009087B1 (en) Motion detection for video including that obtained from film
US6985187B2 (en) Motion-adaptive interpolation apparatus and method thereof
US20070222895A1 (en) Subtitle detection apparatus, subtitle detection method and pull-down signal detection apparatus
EP1592250A1 (en) Film-mode detection in video sequences
US4768092A (en) Image signal conversion device
US7075581B1 (en) Interlaced-to-progressive scan conversion based on film source detection
US8279303B2 (en) Imaging apparatus and flicker detection method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070619

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080527

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090622

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090714

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20090714