JP2006018591A - Memory card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory card capable of preventing the decline of a processing speed for write by a small capacity unit even when the flash memory of a large capacity is used. <P>SOLUTION: The memory card is provided with a large capacity flash memory for which a write data unit is large, a small capacity flash memory for which the write data unit is small, and a controller for controlling the large capacity flash memory and the small capacity flash memory. At the time of writing data less than the page size of the large capacity flash memory, the data are written to the small capacity flash memory. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory card, and more particularly to a memory card having a rewritable flash memory.

  Recently, the use of a storage device mainly in the form of a card using a rewritable nonvolatile memory is spreading as an external storage device for storing data used in electronic devices such as computers.

  A typical non-volatile memory that is a storage means in this memory card is a flash memory. Data held in the flash memory is managed in units of blocks, and data in the flash memory is erased in units of blocks. Each block is composed of a plurality of pages. This page is the minimum unit for reading and writing data to the flash memory. (In general, erasing the flash memory indicates a process for setting all bits to “1”, and writing indicates a process for setting the designated bit to “0”.) Therefore, the target area for writing data requested by the host is If it is a part of the page, in order to prevent the data that does not need to be rewritten from being involved in the rewriting process, the data of the page is read once, the corresponding part is replaced with the write data, and the data after the replacement It is necessary to perform a roll-in evacuation process in which the is written on the page. Similarly, when the target area for reading data requested from the host is a part of the page, the data of the page is read, and the data of the corresponding part is selected from the read data and sent to the host.

  Each page has a redundant portion separately from the data, and the redundant portion holds information relating to the logical address assigned to the page and a data correction code. Here, each page is assigned a unique physical address in the flash memory, and the controller can control processing by designating the physical address when sending a command to the flash memory.

  When data is accessed from the host to the memory card, the host handles data with a data size called a sector. Further, when data from the host is held on the flash memory, it is managed in units of logical blocks in accordance with the size of the physical block that is the management unit of the flash memory. This logical block is generally composed of a plurality of sectors. A logical address which is a logical order is added to each sector, and the host controls data processing by designating the logical address to the memory card.

  FIG. 9 is a diagram illustrating a correspondence relationship between a logical address and a physical address in a data management method implemented in a general memory card.

  The logical block written to the memory card is managed in one-to-one correspondence with the physical block in the flash memory (however, there is no corresponding physical block for the unwritten logical block). ). A plurality of logical blocks (here, M) are combined to form a logical segment, and physical blocks (here, N) are combined to form a physical segment. Here, a certain logical segment is assigned to one physical segment, and logical data constituting the logical segment is held in an area managed by a specific physical segment (because a physical block includes a bad block, Generally M <N). Therefore, correspondence information (hereinafter referred to as logical-physical conversion information) between logical blocks and physical blocks held in the flash memory is managed in units of physical segments.

FIG. 10 is a block diagram showing a conventional memory card.
As shown in FIG. 10, the memory card 104 includes a flash memory 102 and a controller 103 that controls the flash memory 102. The flash memory 102 includes a management area 1021 that holds logical-physical conversion information and an area 1022 that holds data assigned to a logical address. Reference numeral 101 denotes a host device that performs data access to the memory card 104.

  As an example of data processing in the conventional memory card configured as described above, a processing procedure when data is written from the host device 101 will be described below.

FIG. 11 is a flowchart of a writing process in a conventional memory card.
First, the host device 101 issues a write command to the controller 103 (S11-1). Receiving the write command from the host device 101, the controller 103 issues a write command to the data area 1022 of the flash memory 102 (S11-2). The end of the writing process of the flash memory 102 is determined (S11-3). If the writing process is ended, it is determined whether the written data size is smaller than the page size unit of the flash memory 102 (S11-4).

  If it is determined in S11-4 that the size is smaller than the page size unit, the evacuation and save processing is performed so that the data size written to the flash memory 102 becomes the page size unit (S11-5). The logical-physical conversion information is written in the management area 1021 held (S11-6). If it is determined in S11-4 that it is larger than the page size unit, the writing in S11-6 is performed without performing the winding and saving process in S11-5.

  Thereafter, it is determined whether or not the writing process of the flash memory 102 has been completed (S11-7). When the process is completed, a signal indicating the completion of data writing is sent to the host device 101 (S11-8).

As described above, the conventional memory card has one flash memory or a plurality of flash memories of the same type, and each flash memory has a data area, a logical address viewed from the host, and a physical address in the flash memory. It has an area for holding logical-physical conversion information that associates addresses (for example, see Patent Document 1).
JP 2001-142774 A

  In recent years, the capacity of flash memories used for memory cards has been increasing, and with this increase in capacity, the block size as an erasing unit and the page size as a writing unit tend to increase.

  If the page size is large, there is a problem that the processing speed of the memory card decreases because it is necessary to perform a roll-in save process when writing at a page size or smaller.

  Even when the data portion and the logical / physical conversion information portion are written separately to the flash memory, the flash memory write processing time increases as the page size increases. There is a problem in that the overhead of the memory card increases and the processing speed of the memory card itself decreases.

  The present invention has been made to solve the above-described conventional problems, and can prevent a decrease in processing speed for writing in a small capacity unit even when a large capacity flash memory is used. The purpose is to provide a card.

  A memory card according to claim 1 of the present invention is a large-capacity flash memory having a large write data unit, a small-capacity flash memory having a small write data unit, a controller for controlling the large-capacity flash memory and the small-capacity flash memory; Is provided.

  The memory card according to claim 2 of the present invention is the memory card according to claim 1, wherein the small-capacity flash memory is a logical-physical conversion related to data in the large-capacity flash memory and data in the small-capacity flash memory. It has a management area for holding information.

  A memory card according to a third aspect of the present invention is the memory card according to the first aspect, wherein the small-capacity flash memory has a data area for holding only FAT data.

  A memory card according to a fourth aspect of the present invention is the memory card according to the first aspect, wherein the controller transfers a head sector of data sent from a host to the large-capacity flash memory and the small-capacity flash memory. In the case where only one sector is transferred from the host, the small capacity flash memory is written, and when data is continuously sent from the host, the large capacity flash memory is written. is there.

  A memory card according to a fifth aspect of the present invention is the memory card according to the fourth aspect, wherein a data bus from the controller to the large-capacity flash memory and the small-capacity flash memory is shared. .

  A memory card according to claim 1 of the present invention is a large-capacity flash memory having a large write data unit, a small-capacity flash memory having a small write data unit, a controller for controlling the large-capacity flash memory and the small-capacity flash memory; Since the small-capacity flash memory is used when writing data smaller than the page size of the large-capacity flash memory, the processing speed for writing in small-capacity units can be improved.

  The memory card according to claim 2 of the present invention is the memory card according to claim 1, wherein the small-capacity flash memory is a logical-physical conversion related to data in the large-capacity flash memory and data in the small-capacity flash memory. It is assumed that it has a management area to hold information, and because the logical-physical conversion information data smaller than the page size of the large-capacity flash memory is written to the small-capacity flash memory, the writing time of the logical-physical conversion information data is shortened, There is an effect that the effective speed can be improved.

  A memory card according to a third aspect of the present invention is the memory card according to the first aspect, wherein the small-capacity flash memory has a data area that holds only FAT data, and a small capacity for rewriting the FAT area. Since the evacuation process is not performed using the flash memory, the effective speed can be improved.

  A memory card according to a fourth aspect of the present invention is the memory card according to the first aspect, wherein the controller transfers a head sector of data sent from a host to the large-capacity flash memory and the small-capacity flash memory. In the case where only one sector is transferred from the host, the small-capacity flash memory is written, and when data is continuously sent from the host, the large-capacity flash memory is written. This has the effect of shortening the writing time per sector and improving the effective speed.

  The memory card according to claim 5 of the present invention is the memory card according to claim 4, wherein a data bus from the controller to the large-capacity flash memory and the small-capacity flash memory is shared. The effective speed can be improved without increasing the number of connection terminals.

(Embodiment 1)
FIG. 1 is a block diagram showing a memory card according to Embodiment 1 of the present invention.
As shown in FIG. 1, the memory card 14 includes a large-capacity flash memory 12, a small-capacity flash memory 15, and a controller 13 that controls the large-capacity flash memory 12 and the small-capacity flash memory 15. The large-capacity flash memory 12 includes a management area 121 that holds logical-physical conversion information and a data area 122 that holds data assigned to logical addresses. The small-capacity flash memory 15 holds logical-physical conversion information. Management area 151 and area 152 that holds data assigned to the logical address. Reference numeral 11 denotes a host device that performs data access to the memory card 14.

  The large-capacity flash memory 12 has a write processing time of about 600 us for a page size of 2 Kbytes, and the small-capacity flash memory 15 has a write processing time of about 200 us for a page size of 512 bytes. 13 controls to write 512-byte data to the small-capacity flash memory 15 when the data is written from the host device 11.

  Since the memory card of the first embodiment uses a small-capacity flash memory for rewriting data in 512-byte units, the processing speed for writing in small-capacity units can be improved. .

(Embodiment 2)
FIG. 2 is a block diagram showing a memory card according to Embodiment 2 of the present invention.
As shown in FIG. 2, the memory card 24 includes a large-capacity flash memory 22, a small-capacity flash memory 25, and a controller 23 that controls the large-capacity flash memory 22 and the small-capacity flash memory 25. The large-capacity flash memory 22 includes a data area 222 that stores data assigned to a logical address, and the small-capacity flash memory 25 includes a management area 251 that stores logical-physical conversion information. Reference numeral 21 denotes a host device that performs data access to the memory card 24.

  The large-capacity flash memory 22 has a write processing time of about 600 us for a page size of 2 Kbytes, and the small-capacity flash memory 25 has a write processing time of about 200 us for a page size of 512 bytes. Is controlled so that data whose write data size is variable is written to the data area 222 of the large-capacity flash memory 22 and logical-physical conversion data whose one-write data size is 2 Kbytes or less is written to the management area 251 of the small-capacity flash memory 25. To do.

  As an example of data processing in the memory card according to the second embodiment configured as described above, a processing procedure when data is written from the host device 21 will be described.

  FIG. 3 is a flowchart for explaining a memory card write process according to the second embodiment of the present invention.

  First, the host device 21 issues a write command to the controller 23 (S3-1). Receiving the write command from the host device 21, the controller 23 issues a write command to the data area 222 of the large-capacity flash memory 22 (S3-2). The end of the writing process of the large-capacity flash memory 22 is determined (S3-3), and if the writing process is ended, it is determined whether the written data size is smaller than the page size unit of the large-capacity flash memory 22 (S3). -4).

  If it is determined in S3-4 that the data size is smaller than the page size unit, the evacuation process is performed so that the data size written to the large-capacity flash memory 22 becomes the page size unit of the large-capacity flash memory 22 (S3-5). Thereafter, the logical / physical conversion information is written in the management area 251 holding the logical / physical conversion information in the small-capacity flash memory 25 (S3-6). If it is determined in S3-4 that it is larger than the page size unit, the writing in S3-6 is performed without performing the evacuation saving process in S3-5.

Thereafter, the end of the writing process of the small-capacity flash memory 25 is determined (S3-7), and when the process is completed, a signal of data writing completion is sent to the host device 21 (S3-8).
In such a memory card according to the second embodiment, the logical-physical conversion information data having a page size smaller than that of the large-capacity flash memory is written to the small-capacity flash memory, so the writing time of the logical-physical conversion information data is shortened. In addition, the effective speed can be improved.

(Embodiment 3)
FIG. 4 is a block diagram showing a memory card according to Embodiment 3 of the present invention.
As shown in FIG. 4, the memory card 44 includes a large-capacity flash memory 42, a small-capacity flash memory 45, and a controller 43 that controls the large-capacity flash memory 42 and the small-capacity flash memory 45. The large-capacity flash memory 42 includes a data area 421 that stores data other than FAT (File Allocation Tables). The small-capacity flash memory 45 includes a management area 451 that stores logical-physical conversion information and FAT data. The data area 452 is held. Reference numeral 41 denotes a host device that performs data access to the memory card 44.

  The large-capacity flash memory 42 has a write processing time of about 600 us for a page size of 2 Kbytes, and the small-capacity flash memory 45 has a write processing time of about 200 us for a page size of 512 bytes. The data whose write data size changes at one time is written in the data area 421 of the large-capacity flash memory 42, and the FAT area whose write data size is 512 bytes at one time is written in the data area 452 of the small-capacity flash memory 45. Control.

  As an example of data processing in the memory card according to the third embodiment configured as described above, a processing procedure at the time of writing data from the host device 41 will be described.

  FIG. 5 is a flowchart for explaining a memory card write process according to the third embodiment of the present invention.

  First, the host device 41 issues a write command to the controller 43 (S5-1). The controller 43 that has received the write command from the host device 41 determines whether or not the write from the host device 41 is for the FAT area (S5-2).

  If it is determined in S5-2 that the writing from the host device 41 is not for the FAT area, a write command is issued for the data from the host device 41 to the data area 422 of the large-capacity flash memory 42 (S5). -3). The end of the writing process of the large-capacity flash memory 42 is determined (S5-4), and if the writing process is ended, it is determined whether or not the written data size is smaller than the page size unit of the large-capacity flash memory 42 (S5). -5).

  If it is determined in S5-5 that the size is smaller than the page size unit, the wrap-around save process is performed so that the size of data written to the large-capacity flash memory 42 becomes the page size unit of the large-capacity flash memory 42 (S5-6). Thereafter, the logical / physical conversion information is written in the management area 451 that holds the logical / physical conversion information in the small-capacity flash memory 45 (S5-9). If it is determined in S5-5 that it is larger than the page size unit, the writing in S5-6 is performed without performing the wrap-around saving process in S5-6.

  If it is determined in S5-2 that the write from the host device 41 is for the FAT area, a write command for the data from the host device 41 is issued to the data area 452 of the small-capacity flash memory 45. (S5-7). Thereafter, the end of the writing process of the small-capacity flash memory 45 is determined (S5-8), and when the writing process ends, the writing of S5-9 is performed. Here, since the page size of the small-capacity flash memory 45 is 512 Bytes, no evacuation process occurs.

  Thereafter, the end of the writing process of the small-capacity flash memory 45 is determined (S5-10). When the process is completed, a signal indicating the completion of data writing is sent to the host device 41 (S5-11).

  In such a memory card according to the third embodiment, the effective speed can be improved since the small area flash memory is not used for the FAT area rewriting process and the retraction process is not performed.

(Embodiment 4)
FIG. 6 is a block diagram showing a memory card according to Embodiment 4 of the present invention.
As shown in FIG. 6, the memory card 64 includes a large-capacity flash memory 62, a small-capacity flash memory 65, and a large-capacity flash memory 62 and a controller 63 that controls the small-capacity flash memory 65. The large-capacity flash memory 62 includes a data area 621 that holds data, and the small-capacity flash memory 65 includes a management area 651 that stores logical-physical conversion information and a data area 652 that stores data. Has been. Reference numeral 61 denotes a host device that performs data access to the memory card 64.

  The large-capacity flash memory 62 has a write processing time of about 600 us for a page size of 2 Kbytes, and the small-capacity flash memory 65 has a write processing time of about 200 us for a page size of 512 bytes. The data sent from the host device 61 in units of one sector is written to the data area 652 of the small-capacity flash memory 65, and the data continuously sent from the host apparatus 61 is written to the data area 622 of the large-capacity flash memory 62. Control.

As an example of data processing in the memory card according to the fourth embodiment configured as described above, a processing procedure when data is written from the host device 61 will be described.
FIG. 7 is a flowchart for explaining a memory card write process according to the fourth embodiment of the present invention.

  First, the host device 61 issues a write command to the controller 63 (S7-1). Receiving the write command from the host device 61, the controller 63 transfers the data from the host device 61 to both the data area 621 of the large-capacity flash memory 62 and the data area 652 of the small-capacity flash memory 65 (S7). -2).

  Thereafter, it is determined whether or not writing from the host device 61 is only one sector (S7-3). When two or more sectors of data are sent from the host device 61, a write command for data from the host device 61 is issued to the data area 622 of the large-capacity flash memory 62 (S7-4). The transfer data to the capacity flash memory 62 is canceled (S7-5). The end of the writing process of the large-capacity flash memory 62 is determined (S7-6), and if the writing process is ended, it is determined whether or not the written data size is smaller than the page size unit of the large-capacity flash memory 62 (S7). -7).

  If it is determined in S7-7 that the size is smaller than the page size unit, the wrap-around save process is performed so that the data size written to the large-capacity flash memory 62 becomes the page size unit of the large-capacity flash memory 62 (S7-8). Thereafter, the logical / physical conversion information is written into the management area 651 that holds the logical / physical conversion information of the small-capacity flash memory 65 (S7-12). If it is determined in S7-7 that it is larger than the page size unit, the writing in S7-12 is performed without performing the evacuation process in S7-8.

  If it is determined in S7-3 that the write from the host device 61 is only one sector, a write command for the data from the host device 61 is issued to the data area 652 of the small-capacity flash memory 65. (S7-9), the transfer data is canceled for the large-capacity flash memory 62 (S7-10). Thereafter, the end of the writing process of the small-capacity flash memory 65 is determined (S7-11), and when the writing process ends, the writing of S7-12 is performed. Here, since the page size of the small-capacity flash memory 65 is 512 Bytes, no wrap-around saving process occurs.

  Thereafter, the end of the writing process of the small-capacity flash memory 65 is determined (S7-13), and when the process is completed, a signal of data writing completion is sent to the host device 61 (S7-14).

  In such a memory card of the fourth embodiment, the effective speed can be improved because the small-capacity flash memory is not used for the one-sector write process from the host and the evacuation process is not performed.

(Embodiment 5)
FIG. 8 is a block diagram showing a memory card according to the fifth embodiment of the present invention.
As shown in FIG. 8, the memory card 84 includes a large-capacity flash memory 82, a small-capacity flash memory 85, and a controller 83 that controls the large-capacity flash memory 82 and the small-capacity flash memory 85. Here, the large-capacity flash memory 82 and the small-capacity flash memory 85 are controlled from the controller 83 by the same BUS. The large-capacity flash memory 82 includes a data area 821 that holds data, and the small-capacity flash memory 85 includes a management area 851 that stores logical-physical conversion information and a data area 852 that stores data. Has been. Reference numeral 81 denotes a host device that performs data access to the memory card 84.

  The large-capacity flash memory 82 has a write processing time of about 600 us for a page size of 2 Kbytes, and the small-capacity flash memory 85 has a write processing time of about 200 us for a page size of 512 bytes. The data sent from the host device 81 in units of one sector is written in the data area 852 of the small-capacity flash memory 85, and the data continuously sent from the host device 81 is written in the data area 821 of the large-capacity flash memory 82. Control.

  Such a memory card of the fifth embodiment can obtain an effective speed equivalent to that of the memory card of the fourth embodiment without increasing the number of connection terminals of the controller.

  Since the memory card according to the present invention can prevent a decrease in processing speed for writing in a small capacity unit even when a large capacity flash memory is used, a large capacity and high speed image recording using the memory card is possible. Useful for systems that perform processing.

It is a block diagram which shows the memory card by Embodiment 1 of this invention. It is a block diagram which shows the memory card by Embodiment 2 of this invention. It is a flowchart for demonstrating the write-in process of the memory card by Embodiment 2 of this invention. It is a block diagram which shows the memory card by Embodiment 3 of this invention. It is a flowchart for demonstrating the write-in process of the memory card by Embodiment 3 of this invention. It is a block diagram which shows the memory card by Embodiment 4 of this invention. It is a flowchart for demonstrating the write-in process of the memory card by Embodiment 4 of this invention. It is a block diagram which shows the memory card by Embodiment 5 of this invention. It is a figure which shows the correspondence of the logical address and physical address in the data management method currently implemented with the general memory card. It is a block diagram which shows the conventional memory card. It is a flowchart of the write-in process in the conventional memory card.

Explanation of symbols

11, 21, 41, 61, 81, 101 Host device 12, 22, 42, 62, 82 Large-capacity flash memory 13, 23, 43, 63, 83, 103 Controller 14, 24, 44, 64, 84, 104 Memory Card 15, 25, 45, 65, 85 Small-capacity flash memory 121, 151, 251, 451, 651, 851, 1021 Management area 122, 152, 222, 421, 452, 621, 652, 821, 852, 1022 Data area 102 flash memory

Claims (5)

A large-capacity flash memory with a large write data unit,
A small-capacity flash memory with a small write data unit,
A controller for controlling the large-capacity flash memory and the small-capacity flash memory,
A memory card characterized by that. The memory card according to claim 1,
The small-capacity flash memory is
A management area for holding logical-physical conversion information related to the data in the large-capacity flash memory and the data in the small-capacity flash memory;
A memory card characterized by that. The memory card according to claim 1,
The small-capacity flash memory is
It has a data area that holds only FAT (File Allocation Tables) data.
A memory card characterized by that. The memory card according to claim 1,
The controller is
The first sector of the data sent from the host is transferred to the large-capacity flash memory and the small-capacity flash memory. If the transfer is only one sector from the host, the data is written to the small-capacity flash memory. If data is sent continuously, write to the large-capacity flash memory.
A memory card characterized by that. The memory card according to claim 4, wherein
Sharing a data bus from the controller to the large-capacity flash memory and the small-capacity flash memory;
A memory card characterized by that.

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