JP2006005741A - Limiter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a limiter circuit which has a small circuit scale and high clip accuracy and does not need a capacitor with large capacitance. <P>SOLUTION: When, for example, +2V is applied to a control terminal 30 as clip voltage, the voltage of +2V is applied to the source of a FET 28 and to a minus input port of an operational amplifier 31, and the operational amplifier 31 outputs voltage of -2V to apply the voltage of -2V to the source of a FET 23. In this state, when an input signal at an input terminal 21 is within the range from -2V to +2V, both FETs 25 and 26 are turned off to prevent a circuit from affecting the input signal. When voltage of the input signal is equal to and greater than +2V, source voltage of the FET 26 becomes higher than gate voltage to turn on the FET 26, clipping the input signal at +2V. In addition, when voltage of the input signal is not greater than -2V, the source voltage of the FET 25 becomes lower than the gate voltage to turn on the FET 25, clipping the input signal at -2V. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a limiter circuit suitable for use in an input section of a digital amplifier.

  As is well known, in a digital amplifier or the like, the maximum output is limited by the power supply voltage. Therefore, when an excessive input signal is input, the output is saturated. For this reason, the digital amplifier is preferably provided with a limiter circuit for limiting the output level. Of course, a circuit for controlling the power supply voltage may be provided as the limiter circuit, but the circuit for controlling the power supply voltage has a problem that the circuit configuration becomes large.

Therefore, the inventor of this application has considered a limiter circuit that uses an operational amplifier and clips an input signal below a certain level. 6 and 7 are circuit diagrams showing the structure of a limiter circuit using this operational amplifier. In FIG. 6, reference numeral 1 is an input terminal of a digital amplifier, 2 is an N-channel FET (field effect transistor), 3 is a P-channel FET, 4 to 6 are operational amplifiers, 7 and 8 are resistors, and 9 is a control to which a clip voltage is applied. Terminal. In FIG. 7, 10 is a P-channel FET, 11 is an N-channel FET, and other components 1, 4 to
9 is the same as FIG.

In such a configuration, for example, when a 3V clip voltage is applied to the control terminal 9, when the signal at the input terminal 1 is -3V to + 3V, the FETs 2, 3 (10, 11) are turned off, and this limiter circuit operates. However, when the signal at the input terminal 1 exceeds + 3V, the FET 3 (11) is turned on and the input signal is clipped to + 3V. Similarly, when the input signal becomes -3V or less, FET2 (10) is turned on and the input signal is clipped to -3V.
Limiter circuits using diodes or transistors are also known, but these limiter circuits have a drawback that the accuracy of clipping is poor compared to the circuit described above using an operational amplifier.
JP-A-1-109810 Patent Brother 3162889

  The above-described limiter circuit using an operational amplifier has high accuracy and a relatively small circuit configuration, but still has the following problems. That is, FIG. 8 is a diagram illustrating an example of the internal configuration of the operational amplifier. An operational amplifier generally has a high gain (80 or more). Therefore, in order to form a feedback loop, capacitors having a considerably large capacity of, for example, 100 pF are required as the phase compensation capacitors C1 and C2 shown in the figure. However, when such a large-capacitance capacitor is formed in an IC (integrated circuit), a large area is occupied by the capacitor, which is extremely undesirable.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a limiter circuit that has a small circuit scale, a high clipping accuracy, and does not require a large-capacitance capacitor.

  The present invention has been made to solve the above problems, and the invention according to claim 1 is a limiter circuit that clips an input signal applied to an input terminal at a constant voltage by a control voltage input from the outside. A control element connected between a power supply terminal and the input terminal; and a control circuit that always turns off the control element and controls the control element to be on when the input signal exceeds the constant voltage. This is a limiter circuit.

According to a second aspect of the present invention, in a limiter circuit that clips an input signal applied to an input terminal at a constant voltage by a control voltage input from the outside, the power supply terminals are connected in series, and an interconnection point is connected to the input terminal. The connected first and second control elements and the first control element are normally turned off, and the first control element is controlled to be turned on when the input signal exceeds the first control voltage. A first control circuit and a second control circuit that always turns off the second control element and controls the second control element to an on state when the input signal becomes equal to or lower than a second control voltage. And a limiter circuit.
According to a third aspect of the present invention, in the limiter circuit according to the second aspect, the second control voltage is a voltage obtained by inverting the first control voltage.

  According to a fourth aspect of the present invention, in a limiter circuit that clips an input signal applied to an input terminal at a voltage level applied to the control terminal, the power supply terminals are connected in series, and an interconnection point is connected to the input terminal. First and second transistors; a third transistor that forms a current mirror circuit together with the first transistor; and first and second constant current circuits inserted between the third transistor and a power supply terminal; A fourth transistor constituting a current mirror circuit together with the second transistor, third and fourth constant current circuits inserted between the fourth transistor and a power supply terminal, and an inverting circuit for inverting the voltage of the control terminal The voltage of the control terminal is applied to the connection point of the third transistor and the first constant current circuit, and the output voltage of the inverting circuit is A limiter circuit, characterized in that added to the connection point of the fourth transistor and the third constant current circuit.

According to a fifth aspect of the present invention, there is provided a limiter circuit that clips an input signal applied to an input terminal at a constant voltage by a control voltage input from the outside, and first and second transistors connected in series between power supply terminals; A third transistor constituting a current mirror circuit together with the first transistor, first and second constant current circuits inserted between the third transistor and a power supply terminal, and a current mirror circuit together with the second transistor. A fourth transistor to be configured, and third and fourth constant current circuits inserted between the fourth transistor and a power supply terminal, and a fifth transistor connected in series between the power supply terminals and controlled by the first transistor. And a sixth transistor controlled by the second transistor, the first control voltage being the third transistor A second control voltage is applied to the connection point of the fourth transistor and the third constant current circuit, and the input terminal is connected to the fifth transistor and the connection point of the transistor and the first constant current circuit; A limiter circuit connected to an interconnection point of a sixth transistor.
According to a sixth aspect of the present invention, in the limiter circuit according to the fifth aspect, the second control voltage is a voltage obtained by inverting the first control voltage.

  According to the present invention, there is an advantage that the circuit scale is small, the clipping accuracy is high, and a capacitor having a large capacity is not required.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of a limiter circuit according to the first embodiment of the present invention. In this figure, 21 is an input terminal of the digital amplifier. 22 is a 10 μA constant current circuit, 23 is an N-channel FET, 24 is a 10 μA constant current circuit, one end of the constant current circuit 22 is connected to the + 5V power supply, and the other end is connected to the drain and gate of the FET 23. Are connected to a -5V power source through a constant current circuit 24. An N channel FET 25 has a drain connected to the + 5V power source, a gate connected to the gate of the FET 23, and a source connected to the input terminal 21. The FETs 23 and 25 described above constitute a current mirror circuit.

  26 is a P-channel FET, the source is connected to the input terminal 21, the base (substrate) is connected to the + 5V power supply, the gate is connected to the gate and drain of the P-channel FET 28, and the drain is connected to the -5V power supply. ing. The source of the FET 28 is connected to the control terminal 30 and connected to the + 5V power source via the 10 μA constant current circuit 27, the base is connected to the +5 V power source, and the drain is connected to the −5 V power source via the 10 μA constant current street 29. It is connected. The FETs 26 and 28 described above constitute a current mirror circuit. Reference numeral 31 denotes an operational amplifier, the + input terminal of which is grounded, the − input terminal is connected to the output terminal via a resistor 32, and is connected to the control terminal 30 via a resistor 33, and the output terminal is connected to the FET 23 and a constant current. The connection point of the circuit 24 is connected. Here, the values of the resistors 32 and 33 are the same. This inverts the voltage applied to the control terminal 30 and is not necessary when a control voltage (lower limit side) is applied to the connection point between the FETs 23 and 24.

  In such a configuration, it is assumed that, for example, +2 V is applied to the control terminal 30 as a clip voltage. This voltage + 2V is applied to the source of the FET 28 and also to the negative input terminal of the operational amplifier 31 via the resistor 33. As a result, a voltage of −2 V is output from the operational amplifier 31 and applied to the source of the FET 23. In this state, when the input signal of the input terminal 21 is in the range of −2V to + 2V, both the FETs 25 and 26 are turned off, and the clip circuit does not affect the input signal.

  Next, when the input signal becomes + 2V or more, the FET 28 and the FET 26 constitute a current mirror circuit, and the source of the FET 26 works to be + 2V. That is, the source voltage of the FET 26 becomes higher than the gate voltage (threshold voltage Vt), and the FET 26 is turned on. As a result, the input signal is clipped at + 2V. When the input signal becomes −2V or lower, the source voltage of the FET 25 becomes lower than the gate voltage, the FET 25 is turned on, and the input signal is clipped at −2V.

In the first embodiment described above, the circuit configuration is simple, the operation speed is fast, and the input signal can be accurately clipped at the clipping voltage. Further, since the gain is relatively small, a phase compensation circuit is unnecessary, and there is no need to provide a phase compensation capacitor. Even when the Vt (threshold voltage) characteristics of the FETs 26 and 28 (or 23 and 25) vary, the relative variation of the FETs 26 and 28 (or 23 and 25) only becomes a problem. Variation does not matter. As a result, if FETs 26 and 28 (or 23 and 25) having the same characteristics are prepared, highly accurate clip characteristics can be obtained.
However, in the above circuit, the current flowing through the FETs 25 and 26 is 10 μA at the maximum, and as a result, as shown in FIG. This poor clip is usually not a problem, but the following problems occur depending on the state of use. That is, the amount of the portion beyond the broken line in FIG. 3 cannot be controlled. For this reason, if the amount exceeding the broken line is different between the + side and the − side, an offset occurs. This offset has a problem of applying an extra load to a subsequent speaker or the like.

Thus, a second embodiment of the present invention that solves such a problem will be described.
FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention. In this figure, portions corresponding to the respective portions in FIG. In this figure, reference numeral 41 denotes a 10 μA constant current circuit, which is inserted between the drain of the FET 25 and the + 5V power source. Reference numeral 42 denotes a P-channel FET, the source of which is connected to the + 5V power supply, the gate of which is connected to the drain of the FET 25, and the drain of which is connected to the input terminal 21. Reference numeral 43 denotes an N-channel FET, the drain of which is connected to the input terminal 21, the gate of which is connected to the drain of the FET 26, and the source of which is connected to a -5V power source. Reference numeral 44 denotes a constant current circuit of 10 μA, which is inserted between the drain of the FET 26 and the −5V power source.

  In such a configuration, when, for example, +2 V is applied to the control terminal 30 as a clip voltage, +2 V is applied to the source of the FET 28, and −2 V is applied to the source of the FET 23 by the operational amplifier 31. In this state, when the input signal of the input terminal 21 is in the range of −2V to + 2V, both the FETs 25 and 26 are turned off, and hence the FETs 42 and 43 are also turned off, and the clip circuit has an influence on the input signal. Absent.

  Next, when the input signal becomes +2 V or more, the source voltage of the FET 26 becomes higher than the gate voltage, and the FET 26 is turned on. As a result, the gate of the FET 43 becomes higher than the source, the FET 43 is turned on, and the input signal is clipped at + 2V. When the input signal becomes −2 V or less, the source voltage of the FET 25 becomes lower than the gate voltage, and the FET 25 is turned on. As a result, the gate of the FET 42 becomes a lower level than the source, the FET 42 is turned on, and the input signal is clipped at −2V.

  As described above, according to the second embodiment, a large current can be caused to flow by the FET 42 or 43 at the time of clipping. As a result, as shown in FIG. Can be clipped linearly.

  4 and 5 are diagrams showing the effects of the second embodiment, in which the horizontal axis represents time and the vertical axis represents voltage. A curve L1 shown in FIG. 4 shows a voltage obtained at the input terminal 21 when a sine wave having a peak-peak of 11V is applied to the input terminal 21 via a resistor and 5V is applied to the control terminal 30 as a clip voltage. Also, L1a to L1d are the same input signals, and indicate voltages obtained at the input terminal 21 when the clip voltage is 4V, 3V, 2V, and 1V. In FIG. 4, a curve L2 is obtained at the input terminal 21 when a sine wave having a peak-peak of 24V is applied to the input terminal 21 via a resistor, and 3V is applied to the control terminal 30 as a clip voltage. The voltage is shown.

  In FIG. 5, a curve L3 is obtained at the input terminal 21 when a sine wave having an effective value of 2.3 V is applied to the input terminal 21 via a resistor, and 3 V is applied to the control terminal 30 as a clip voltage. In addition, L3a to L3f have the same input signal as the curve L3, and the input terminal 21 when the clip voltage is 2.5V, 2V, 1.5V, 1V, 0.5V, and 0V. Shows the voltage obtained. As is clear from these figures, according to the second embodiment, the input signal is clipped accurately and in a state of good linearity with no sluggish state by the clipping voltage applied to the control terminal 30. Can do.

  The present invention is used in digital amplifiers and other various fields.

1 is a circuit diagram showing a configuration of a limiter circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the limiter circuit by 2nd Embodiment of this invention. It is a wave form diagram for demonstrating the characteristic of 1st, 2nd embodiment. It is a wave form diagram for demonstrating the effect of 2nd Embodiment. It is a wave form diagram for demonstrating the effect of 2nd Embodiment. It is a circuit diagram which shows the structural example of the limiter circuit which uses an operational amplifier. It is a circuit diagram which shows the other structural example of the limiter circuit using an operational amplifier. It is a circuit diagram which shows an example of an internal structure of an operational amplifier.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 ... Input terminal 22, 24, 27, 29, 41, 44 ... Constant current circuit 23, 25, 43 ... N channel FET, 26, 28, 42 ... P channel FET, 30 ... Control terminal, 31 ... Operational amplifier.

Claims (6)

In the limiter circuit that clips the input signal applied to the input terminal at a constant voltage by the control voltage input from the outside,
A control element connected between a power supply terminal and the input terminal;
A control circuit that always turns off the control element and controls the control element to be on when the input signal exceeds the constant voltage;
A limiter circuit comprising: In the limiter circuit that clips the input signal applied to the input terminal at a constant voltage by the control voltage input from the outside,
First and second control elements connected in series between power supply terminals and having an interconnection point connected to the input terminal;
A first control circuit that always turns off the first control element and controls the first control element to be in an on state when the input signal exceeds a first control voltage;
A second control circuit that always turns off the second control element and controls the second control element to be in an on state when the input signal becomes equal to or lower than a second control voltage;
A limiter circuit comprising:   The limiter circuit according to claim 2, wherein the second control voltage is a voltage obtained by inverting the first control voltage. In the limiter circuit that clips the input signal applied to the input terminal at the level of the voltage applied to the control terminal,
First and second transistors connected in series between power supply terminals and having an interconnection point connected to the input terminal;
A third transistor constituting a current mirror circuit together with the first transistor, and first and second constant current circuits inserted between the third transistor and a power supply terminal;
A fourth transistor constituting a current mirror circuit together with the second transistor, and third and fourth constant current circuits inserted between the fourth transistor and a power supply terminal;
An inverting circuit for inverting the voltage of the control terminal;
The voltage of the control terminal is applied to the connection point of the third transistor and the first constant current circuit, and the output voltage of the inverting circuit is applied to the fourth transistor and the third constant current circuit. A limiter circuit characterized by being added to a connection point. In the limiter circuit that clips the input signal applied to the input terminal at a constant voltage by the control voltage input from the outside,
First and second transistors connected in series between power supply terminals;
A third transistor constituting a current mirror circuit together with the first transistor, and first and second constant current circuits inserted between the third transistor and a power supply terminal;
A fourth transistor constituting a current mirror circuit together with the second transistor, and third and fourth constant current circuits inserted between the fourth transistor and a power supply terminal;
A fifth transistor connected in series between the power supply terminals and controlled by the first transistor and a sixth transistor controlled by the second transistor;
A first control voltage is applied to a connection point of the third transistor and the first constant current circuit, and a second control voltage is applied to the connection of the fourth transistor and the third constant current circuit. In addition to the point, the input terminal is connected to the interconnection point of the fifth transistor and the sixth transistor.   The limiter circuit according to claim 5, wherein the second control voltage is a voltage obtained by inverting the first control voltage.

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