JP2006005379A - Multilayer ceramic circuit board with built-in capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer ceramic circuit board with built-in capacitor and its manufacturing method, capable of stably forming a capacitor area inside the multilayer ceramic circuit board and realizing high density interconnection without imposing restriction on internal interconnection patterns. <P>SOLUTION: A predetermined circuit including internal interconnection patterns 2 and via hole conductors 3 is arranged in a laminate board 1 composed by laminating a plurality of ceramic layers 1a to 1e, and capacitors 6b and 6d, in each of which a dielectric ceramic layer 62 is sandwiched by a pair of capacitor electrode patterns 61 and 63, are connected to the circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer ceramic circuit board with a built-in capacitor, in which a capacitor region composed of a pair of capacitive electrode patterns and a dielectric ceramic member sandwiched between the capacitor electrode patterns is arranged on a part of the multilayer board.

  Conventionally, a laminated ceramic circuit board is a laminate board in which a green sheet filled with a conductor serving as a via-hole conductor and having a conductor film serving as an internal wiring pattern formed on the surface is laminated according to the laminated structure and fired. A surface wiring pattern or the like was formed on the surface of the laminated substrate as necessary.

  As a structure in which such a multilayer ceramic circuit board has other functions besides wiring for forming a predetermined circuit, conventionally, a thick film resistor film or a thick film is mainly formed on the surface of the multilayer board. Capacitors were formed. For example, since a thick film resistor film generally has a structure in which a resistor film is disposed between two surface wiring patterns, it can be relatively easily formed on the surface of a multilayer substrate. On the other hand, a thick film capacitor has a structure in which a dielectric layer is interposed between a pair of capacitive electrode patterns. Therefore, in order to obtain a predetermined capacitance characteristic, it is largely defined by the facing area of the pair of capacitive electrode patterns. This has been a major obstacle to increasing the density of surface wiring patterns.

  For this reason, it is very effective to form a capacitor for deriving a predetermined capacity characteristic inside the multilayer substrate in order to increase the density of the wiring pattern of the entire multilayer ceramic circuit substrate.

  As a structure in which the capacitor region is formed inside the multilayer substrate as described above, for example, referring to the chip-shaped multilayer ceramic capacitor structure, at least both of the ceramic green sheets serving as the ceramic layers of the multilayer substrate are laminated. A laminated substrate is formed by interposing a dielectric ceramic green sheet having a predetermined dielectric constant so that a capacitive electrode pattern is disposed on the main surface side.

  In the above-described multilayer ceramic circuit board with a built-in capacitor, a dielectric ceramic green sheet having a predetermined dielectric constant is interposed on the entire surface between ceramic layers made of a plurality of ceramic green sheets.

  In particular, in a region where a pair of capacitive electrodes is not formed, the ceramic green sheet serving as the ceramic layer and the dielectric ceramic green sheet serving as the dielectric ceramic layer are in contact with each other. Peeling phenomenon occurs due to the difference in shrinkage behavior.

  Further, since the capacitance characteristic is defined by the thickness of the dielectric ceramic layer, it is necessary to use a dielectric green sheet having a predetermined thickness. Normally, the thickness of this dielectric ceramic green sheet is thinner than that of the ceramic green sheet, and the insulation characteristics are different between the two. For example, an internal wiring pattern is formed on both main surfaces of the dielectric ceramic layer. May not be possible, and it may cause a major obstacle to increasing the density of internal wiring patterns.

  In order to solve the above-mentioned problems, the present invention can fundamentally change the method for manufacturing a capacitor-embedded multilayer ceramic circuit board, and can stably form a capacitor region inside the multilayer ceramic circuit board. Moreover, the present invention provides a multilayer ceramic circuit board with a built-in capacitor capable of high-density wiring without restricting internal wiring patterns and a method for manufacturing the same.

  In the present invention, a predetermined circuit composed of an internal wiring pattern and a via-hole conductor is disposed in a multilayer substrate formed by laminating a plurality of ceramic layers, and a pair of dielectric ceramic layers connected to the circuit is provided. Capacitors sandwiched by capacitive electrode patterns are arranged.

  In the present invention, a predetermined circuit composed of an internal wiring pattern and a via-hole conductor is disposed in a multilayer substrate formed by laminating a plurality of ceramic layers, and a pair of dielectric ceramic layers connected to the circuit is provided. Capacitors sandwiched between the capacitor electrode patterns are arranged inside, so that the capacitor area does not become an obstacle to the formation of internal wiring patterns between ceramic layers. At the same time, the degree of freedom in designing the wiring pattern on the surface side is improved, and the high density can be maintained.

  Hereinafter, a capacitor built-in type multilayer ceramic circuit board of the present invention and a manufacturing method thereof will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a built-in multilayer ceramic circuit board according to the present invention.

  In FIG. 1, reference numeral 10 denotes a built-in multilayer ceramic circuit board, which is formed on a multilayer substrate 1 including a wiring pattern 2, a via-hole conductor 3, and capacitor regions 6 b and 6 d inside, and a main surface of the multilayer substrate 1. It is composed of surface wiring patterns 4, 5 and thick film resistor films, protective films, and various electronic components that are mounted and formed as necessary. The multilayer substrate 1 is formed by laminating ceramic layers 1a to 1e to form an internal wiring pattern 2 formed between the ceramic layers 1a to 1e, between the internal wiring patterns 2, and between the internal wiring pattern 2 and the surface wiring patterns 4 and 5. It consists of via-hole conductors 3 formed between them. Furthermore, capacitor regions 6b and 6d connected to the internal wiring pattern 2 and the via-hole conductor 3 are disposed in the ceramic layers 1b and 1d.

  The ceramic layers 1a to 1e are made of a glass-ceramic material that can be fired at a relatively low temperature of, for example, about 850 to 1050 ° C., and have a thickness of about 100 to 300 μm in consideration of insulating characteristics.

  The internal wiring pattern 2 and the via-hole conductor 3 are made of a conductor such as Ag (Ag simple substance, Ag alloy such as Ag-Pd) or Cu (Cu simple substance, Cu alloy), and the thickness of the internal wiring pattern 2 is about 8 to 15 μm. The diameter of the via-hole conductor can be set to an arbitrary value. For example, the diameter is 80 to 250 μm.

  Further, a part of the ceramic layers 1b and 1d is arranged so as to be dotted with capacitor regions 6b and 6d composed of one capacitor electrode pattern 61, a dielectric ceramic layer 62, and the other capacitor electrode pattern 63. ing.

  The capacitive electrode patterns 61 and 63 are made of the same material as the internal wiring pattern 2 and are formed with substantially the same thickness.

  The dielectric ceramic layer 62 has a predetermined dielectric constant different from that of the ceramic layers 1a to 1e. For example, the dielectric ceramic layer 62 is made of a ceramic such as Pb4 Fe2 Nb2 O12 and a low melting point glass material.

  The opposing areas of the capacitive electrode patterns 61 and 63 and the thickness of the dielectric ceramic layer 62 are set to predetermined values according to the capacitance characteristics. For example, the thickness of the dielectric ceramic layer 62 is, for example, about 20 μm to 100 μm, and is the same as or thinner than the thickness of the ceramic layers 1b and 1d.

  A predetermined circuit wiring having a capacitance component is formed in the multilayer substrate 1 by the internal wiring pattern 2 between the ceramic layers 1a to 1e, the via-hole conductor 3, and the capacitor regions 6b and 6d.

  The surface wiring patterns 4 and 5 are made of a conductor such as Ag-based (Ag simple substance, Ag-Pd or other Ag alloy), or Cu-based (Cu simple substance, Cu alloy).

  A thick film resistor film or a protective film is deposited on the surface wiring patterns 4 and 5 of the multilayer substrate 1, and various electronic components such as a chip capacitor, a chip resistor, a transistor, and an IC are soldered. It is mounted and bonded by wire bonding fine wires.

  Here, the characteristic feature of the present invention is that the ceramic layers 1a to 1e are laminated, and a necessary circuit is provided inside the multilayer substrate 1 in which a predetermined circuit is constituted by the internal wiring pattern 2 and the via-hole conductor 3. The capacitor regions 6b and 6d are disposed only in the region. In the figure, capacitor regions 6b and 6d are partially formed in the ceramic layers 1b and 1d.

  Thereby, also in the ceramic layers 1b and 1d including the capacitor regions 6b and 6d, the internal wiring pattern 2 can be formed without hindrance on both main surfaces of the ceramic layers 1b and 1d, and the via holes through the thickness of the ceramic layers 1b and 1d can be formed. The conductor 3 can be formed. That is, the design freedom of the internal wiring pattern 2 and the via-hole conductor 3 can be maintained, and the high-density wiring can be maintained.

  In addition, the capacitor regions 6b and 6d can be formed in a ceramic layer required according to the wiring circuit at a place where the internal wiring pattern 2 can be most efficiently connected, and can be provided inside the multilayer substrate 1. Therefore, the capacitors formed on the surface of the conventional substrate can be eliminated, so that the surface wiring patterns 4 and 5 can be formed with a high density, and the capacitors 6b and 6d are arranged close to the internal wiring pattern 2. be able to. Therefore, high density of the entire multilayer ceramic circuit board is achieved.

  Next, the manufacturing method of the ceramic circuit board with a built-in capacitor according to the present invention will be described. FIG. 2 is a process flow chart, and FIGS. 3A to 3H are schematic views of main processes in the process flow chart of FIG.

  The manufacturing process of the capacitor built-in type multilayer ceramic circuit board 1 includes a preparation process before stacking, a stacking process for forming the stacked body substrate, a peeling process for peeling the stacked body substrate from the support substrate, a firing process, a surface treatment process, and the like. Become.

  In particular, in the laminating process, there are two processes: an insulating film to be the ceramic layers 1a to 1e, a conductor film to be the internal wiring pattern 2, a process to form a conductor to be a via-hole conductor, and a capacitor area forming process. Divided.

  As shown in FIG. 3A, the pre-stacking preparation step prepares a support substrate 15 for forming a multilayer substrate, and also forms a ceramic slip material and dielectric ceramic for forming the ceramic layers 1a to 1e. Conductive pastes for forming the dielectric ceramic slip material for forming the layer 62, the internal wiring pattern 2, the via-hole conductor 3, the capacitive electrode patterns 61 and 63, and the surface wiring patterns 4 and 5 are respectively formed.

  [Support Substrate] The support substrate 15 is a base for forming a laminate substrate as shown in FIG. 3A, and is made of, for example, a substrate of ceramic, glass, heat-resistant resin or the like. If necessary, a support substrate smoothing layer may be formed on the surface of the support substrate 15. The support substrate 15 is stripped in the step (i) of FIG.

  As the support substrate 15, a single-plate or multilayer ceramic circuit substrate on which a predetermined wiring pattern is formed may be used. In this case, the peeling process which is the step (i) is omitted.

  [Ceramic Slip Material] The ceramic slip material is for forming the ceramic layers 1a to 1e, and is processed with a firing temperature of about 850 to 1000 ° C., ceramic powder, glass frit, photocurable monomer, binder A solvent or the like is selected and formed by homogeneous kneading.

  Examples of the ceramic powder include insulating ceramic materials such as cristobalite, quartz, corundum (α-alumina), mullite, cordierite and the like, and the average particle size thereof is 0.5 to 6.0 μm, preferably 1.5 to 4.0 μm. Use pulverized one. Two or more ceramic materials may be mixed and used.

  The glass frit may be any one that precipitates crystals of cordierite, mullite, anorthite, serdian, spinel, garnite, willemite, dolomite, petalite and their substituted derivatives and spinel structure by firing, for example, , B2 O3, SiO2, Al2 O3, ZnO, and a glass frit containing an alkaline earth oxide.

  It is important that such a glass frit has a wide vitrification range and a yield point of around 600 to 800 ° C. The average particle size of the glass frit is 1.0 to 6.0 μm, preferably 1.5 to 3.5 μm.

  Regarding the constituent ratio of the ceramic material and the glass frit, the ceramic material is 10 to 60 wt%, preferably 30 to 50 wt%, and the glass frit is 90 to 40 wt%, preferably 70 to 50 wt%.

  The photocurable monomer is excellent in thermal decomposability so that it can be burned off at a relatively low temperature and in a short baking process, and needs to be photopolymerized by selective exposure treatment. That is, a monomer having a secondary or tertiary carbon capable of forming a free radical by exposure treatment and capable of chain growth addition polymerization is preferable. For example, an alkyl acrylate such as butyl acrylate having at least one polymerizable ethylene group And the corresponding alkyl methacrylates are effective. In addition, polyethylene glycol diacrylates such as tetraethylene glycol diacrylate and methacrylates corresponding to them can be used.

  The binder has a good thermal decomposability like the photocurable monomer and is determined in consideration of the viscosity of the slip. For example, an ethylenically unsaturated compound having a carboxyl group or an alcoholic hydroxyl group such as an acrylic acid or methacrylic acid polymer is preferable. In addition, the ratio of the photocurable monomer and the binder is added to about 1 to 3: 5.

  As the solvent, an organic solvent or an aqueous solvent can be used. In the case of an aqueous solvent, the photocurable monomer and binder must be water-soluble, and a hydrophilic functional group such as a carboxyl group is added to the monomer and binder. The addition amount is 2 to 300, preferably 5 to 100 in terms of acid value.

  The above-mentioned ceramic slip material must be completely pyrolyzed in the process of firing the laminate substrate as described above for the photo-curable monomer and binder, particularly at 600 ° C. or less, preferably at 500 ° C. or less. It is important to select the material to be decomposed.

  Moreover, you may add a sensitizer, a photoinitiating system material, etc. to a ceramic slip material as needed. For example, examples of the photoinitiating material include benzophenones and acyloin ester compounds.

  [Dielectric Ceramic Slip Material] The dielectric ceramic slip material is for forming the dielectric ceramic layer 62 in the capacitor regions 6b and 6d, and is processed at a firing temperature of about 850 to 1000 ° C. Powder, glass frit, photocurable monomer, binder, solvent and the like are selected and formed by homogeneous kneading.

  As the dielectric ceramic powder, for example, Pb4 Fe2 Nb2 O12 can be exemplified, and an average particle size of 0.5 to 6.0 [mu] m, preferably 1.5 to 4.0 [mu] m is used. In addition, since it is simultaneously fired with the insulating films 10a to 1e, it is desirable that the glass frit, the photocurable monomer, the binder, the solvent, and the like are the same as those described above. The constituent ratio of the above-mentioned dielectric ceramic material and glass frit is determined in consideration of the dielectric constant of the dielectric ceramic layer 62. For example, the glass frit may be omitted.

  [Conductive paste] The conductive paste for forming the internal wiring pattern 2, the via-hole conductor 3, the capacitive electrode patterns 61 and 63, and the surface wiring pattern 4 is Ag-based (Ag alone, Ag alloy such as Ag-Pd). , Cu-based (Cu simple substance, Cu alloy) and other conductive material powders, for example, silver-based powder, low melting point glass component, binder, and solvent kneaded are used, and photocurable monomer is added if necessary can do.

  By conducting screen printing and drying of this conductive paste, a conductor film to be the internal wiring pattern 2, the capacitive electrode patterns 61 and 63 and the surface wiring pattern 4 is formed, and the through hole to be the via-hole conductor 3 is filled with the conductor. .

  [Lamination Step] Now, a laminate substrate is formed on the support substrate 15 using various ceramic slip materials and conductive paste.

  A laminated body in which the internal wiring pattern 2 is arranged between the insulating films 10a to 10e to be the ceramic layers 1a to 1e and the conductor 31 to be the via-hole conductor 3 is formed in the thickness of the insulating films 10a to 10e is shown in FIG. It is formed by sequentially repeating steps (e) to (e).

  Also, the conductor films 610 and 630 that become the pair of capacitive electrode patterns 61 and 63 that become the capacitor regions 6b and 6d and the dielectric film 620 that becomes the dielectric ceramic layer 62 are formed in the steps (b) to (e). It is formed by steps (f) to (h) in FIG.

  First, as in the process of FIG. 2B, the insulating film 10e to be the ceramic layer 1e is formed on the support substrate 15 (see FIG. 3A).

  The formation of the insulating film 10e includes a ceramic slip material coating process and a drying process. Specifically, the above-mentioned ceramic slip material is applied to the entire surface of the support substrate 15 to a predetermined thickness, for example, 100 μm, and further dried.

  Here, as a method for applying the ceramic slip material, a doctor blade method (knife coating method), a roll coating method, a printing method, or the like is used, whereby an insulating film 10e having a uniform application surface is formed on the support substrate 15. Will be. For example, in the doctor blade method, the thickness can be arbitrarily set by appropriately setting the height of the blade.

  As a drying method, a batch type drying furnace or an in-line type drying furnace is used, and the drying condition is desirably 120 ° C. or lower. Moreover, since rapid drying may cause cracks on the surface, it is important to avoid rapid heating.

  Next, as in the step (c) of FIG. 2, a through hole 30 penetrating the insulating film 10e is formed corresponding to the position of the ceramic layer 1e serving as the via hole conductor 3 (see FIG. 3 (b)). . This consists of selective exposure processing, development processing, and cleaning / drying processing. In the selective exposure process, a photo target having a pattern that conceals only the region to be the through hole 30 is placed close to or placed on the insulating film 10e, and exposure light (low pressure, high pressure, ultra high pressure mercury lamp system 10 to 10). 20 mW / cm @ 2) is irradiated for about 5 to 30 seconds. As a result, the exposed portion is photocured.

  In the development process, a developing solvent such as organic chlorocene, 1,1,1-trichloroethane, or an alkaline solvent is sprayed onto the insulating film 10e subjected to the selective exposure process by, for example, a spray development method or a paddle development method. , Contact or develop. Thereby, only the part which is not irradiated with exposure light is selectively removed.

  Thereafter, washing and drying are performed as necessary.

  Through the selective exposure process / development process, the through hole 30 of the via hole conductor 3 is formed. Therefore, the shape of the through hole 30, that is, the via hole conductor 3, may be arbitrarily changed depending on the pattern of the photo target. It becomes easy. Accordingly, it is possible to easily increase the shape of the via-hole conductor 3 connected to a wiring pattern through which a relatively large current flows, such as a supply wiring or a ground potential wiring, and the via-hole conductor 3 is not displaced and the via-hole conductor 3 is not displaced. 3 conduction reliability is greatly improved.

  Next, as in the step (d) of FIG. 2, a conductor 31 to be the via-hole conductor 3 is formed in the through hole 30 formed in the insulating film 10e. The conductor 31 which becomes the via-hole conductor 3 is a conductor for connecting the internal wiring pattern 2 and the surface wiring pattern 5.

  Specifically, a conductive paste is printed on the through hole 30 of the insulating film 10e to fill the through hole 30 with the conductor 31 to be the via-hole conductor 3, and a drying process is performed.

  Next, a conductor film 21 to be the internal wiring pattern 2 is formed along the flow line (1) in FIG. 2. In the multilayer ceramic circuit board with a built-in capacitor shown in FIG. 1, the conductor film 21 is formed on the ceramic layer 1e. Since it is necessary to form the capacitor region, the conductor film 21 to be the internal wiring pattern 2 is formed along the flow line (1) in FIG. 2, and at the same time along the flow line (2) in FIG. Then, the conductor film 610 to be the capacitor electrode pattern 61 is formed, and the process proceeds to the capacitor region forming step.

  In practice, the process of forming the conductor film 21 to be the internal wiring pattern 2 and the process of forming the conductor film 610 of the capacitor electrode pattern 61 are the same when forming the conductor 31 to be the via-hole conductor 3 in the process of FIG. The conductive paste may be formed by printing or drying.

  That is, a conductive paste is printed in a predetermined shape on the insulating film 10 e and dried to form the conductor film 21 that becomes the internal wiring pattern 2 and the conductor film 610 that becomes the capacitive electrode pattern 61.

  Next, as shown in the process of FIG. 2G, a dielectric film 620 to be the dielectric ceramic layer 62 in the capacitor region 6d is formed. This comprises a dielectric ceramic slip material coating process, a drying process, a selective exposure process, a developing process, and a cleaning / drying process.

  That is, as shown in FIG. 3D, the dielectric ceramic slip material is treated with the above-mentioned dielectric ceramic slip material in a wide area on the insulating film 10e including the conductor film 610 to be the capacitive electrode pattern 61. Application is performed to a thickness, for example, 20 μm. Thus, a dielectric coating film 620 'having a predetermined shape is formed by selective exposure / development processing. For example, in the doctor blade method, the thickness of the coating film 620 ′ can be arbitrarily set by appropriately setting the height of the blade.

  Next, a drying process is performed under the above-described drying conditions.

  In the next selective exposure process, as shown in FIG. 3E, a photo target 64 that finally exposes a portion to become the dielectric ceramic layer 62 is disposed on the dielectric coating film 620 ′. Exposure light is irradiated under the above-described exposure conditions. As a result, the portion that will eventually become the dielectric ceramic layer 62 is photocured.

  As shown in FIG. 3F, the next development process is to remove the dielectric coating film 620 'portion that has not been photocured by the exposure process, and is performed under the development conditions described above. As a result, the dielectric coating film 620 ′ existing outside the capacitor region 6 d is removed, and a dielectric film 620 having a predetermined pattern is formed.

  By this selective exposure / development processing, the insulating coating film 620 'is patterned into a predetermined shape with high accuracy, and the dielectric film 620 is completed. The insulating film 10e and the conductor film 21 that becomes the internal wiring pattern 2 appear from the removed portion, but the insulating film 10e has already been photocured and the conductor film 21 is not affected by the developer. Since the internal wiring pattern 2 is not adversely affected, the dielectric film 620 can be stably formed in a predetermined shape.

  Thereafter, washing and drying are performed.

  Next, as shown in the process of FIG. 2H, a conductor film 630 that becomes the capacitive electrode pattern 63 is formed (see FIG. 3G).

  This is formed on the dielectric film 620 by screen printing of a conductive paste, and then dried.

  2 (f) to 2 (h), a structure that becomes the capacitor region 6d on the insulating film 10e, that is, a conductor film 620 that becomes the capacitor electrode pattern 61, and a dielectric material are formed on the insulating film 10e. The dielectric film 620 to be the ceramic layer 62 and the conductor film 630 to be the capacitive electrode pattern 63 can be formed independently at predetermined locations.

  In this capacitor region forming step, the thickness of the dielectric film 620 can be set, and furthermore, the opposing areas of the conductor films 610 and 630 that become the capacitor electrode patterns 61 and 63 can be arbitrarily set, so that the capacitance characteristics are stable. This is the capacitor area.

  Next, the steps (b) to (d) in FIG. 2 are performed, and the capacitor film 6d formed on the insulating film 10e, the conductor film 21 to be the internal wiring pattern 2 formed on the insulating film 10e, and the insulating film 10e are formed. An insulating film 10 d is formed so as to cover, the through hole 30 that becomes the via hole conductor 3 reaching the conductor film 630 that becomes the previously formed conductor film 21 and the capacitive electrode pattern 63 is formed, and the conductor that becomes the via hole conductor 3 is formed. It forms (refer FIG.3 (h)).

  Here, since the ceramic slip material is applied to the insulating film 10d so as to cover the conductor film 21 and the capacitor region 6d which become the internal wiring pattern 2 of the insulating film 10e, the capacitor region 6d is provided at a necessary portion of the insulating film 10d. In addition, the surface of the insulating film 10d becomes a uniform surface. Therefore, various treatments formed on the insulating film 10d can be stably formed.

  In addition, from the through hole 30 formed by the selective exposure / development processing of the insulating film 10d, the conductor film 21 to be the already formed internal wiring pattern 2 and the conductor film 630 to be the capacitive electrode pattern 63 are exposed. However, since the conductor films 21 and 630 are not affected by the developer, the via-hole conductor 3 can be stably connected via the conductor 31.

  In addition, an insulating film 10d is formed on and around the capacitor region 6d, and the insulating film 10d is formed in the same manner as a normal insulating film, for example, 10e, regardless of the presence or absence of the capacitor region 6d. The conductor film 21 to be the internal wiring pattern 2 and the conductor 31 to be the via-hole conductor 3 can be formed.

  Next, in FIG. 2, along the flow line (1), the conductor film 21 to be the internal wiring pattern 2 is formed on the insulating film 10d in the step (e).

  Similarly, the steps (b) to (d) of FIG. 2 are repeated to form an insulating film 10c (not shown) on the conductor film 21 to be the internal wiring pattern 2 of the insulating film 10d. A through-hole 30 is formed, and the through-hole 30 is filled with a conductor 31 that becomes the via-hole conductor 3.

  Next, as shown in the step (e) along the flow lines (1) and (2) in FIG. 2, a conductor film 21 to be the internal wiring pattern 2 is formed on the insulating film 10c, and ( The capacitor electrode pattern 61 and the conductor film 610 in the capacitor region 6b shown in step f) are formed.

  Thereafter, as shown in steps (g) to (h) of FIG. 2, a dielectric film 620 to be the dielectric film 62 in the capacitor region 6 b is formed, and a conductor film 630 to be the capacitive electrode pattern 63 is formed.

  Next, the steps (b) to (d) in FIG. 2 are repeated to cover the conductor film 21 to be the internal wiring pattern 2 formed in the insulating film 10c and the capacitor region 6b formed on the insulating film 10c. The insulating film 10b (not shown) is formed, and the through hole 30 to be the via-hole conductor 3 reaching the conductor film 21 and the conductor film 630 to be the capacitive electrode pattern 63 is formed, and the conductor to be the via-hole conductor 3 2 are further repeated to form the insulating film 10a (not shown) and the conductor 31 that becomes the via-hole conductor 3 penetrating the insulating film 10a.

  Although the through-hole 30 and the subsequent holes formed in the insulating film 10d are not shown in FIG. 3, the formation of the insulating film including the internal wiring pattern 2 and the conductor 2 is shown in FIGS. 3 (a) to 3 (c). As shown in FIG. 3, the capacitor region is formed as shown in FIGS. 3 (c) to 3 (g). 3A to 3G, the support substrate 15 is illustrated. The support substrate 15 indicates an insulating film portion formed before the process.

  [Peeling Step] Next, along the flow line (3) in FIG. 2, the peeling step of the support substrate 15 shown in FIG. 2 (j) is performed.

  In the peeling step, the laminate composed of the insulating films 10 a to 10 e including the capacitor regions 6 b and 6 d, the internal wiring pattern 21, and the conductor 31 that becomes the via-hole conductor 3 is separated from the support substrate 15.

  Specifically, in order to peel the support substrate 15 and the laminate, for example, the support substrate 15 is curved, or the cutter blade is slid on a flat surface at the peeling interface. When a resin member that causes a foaming reaction at 120 ° C. (drying temperature) or higher is added to the smooth substrate layer formed at the interface between the support substrate 15 and the laminate, heat treatment facilitates peeling. It doesn't matter. In addition, a sheet that dissolves with an organic solvent may be interposed in an interface portion between the support substrate 15 and the substrate smoothing layer, and may be immersed in the organic solvent. When using a sheet that dissolves with an organic solvent, it is important to use a ceramic slip material, a binder for the conductive paste, an aqueous system for the photocurable monomer, and pure water as the solvent.

  [Surface Wiring Pattern Forming Step] Next, a conductor film to be the surface wiring patterns 4 and 5 is formed on the surface of the laminate, which is the step (j) of FIG. This is formed by printing a conductive paste and further drying.

  [Baking Step] Next, as a step (k) in FIG. 2, the laminated substrate including the conductor film to be the surface wiring patterns 4 and 5 is subjected to a baking treatment. The firing process includes a binder removal process and a sintering process.

  The binder removal treatment includes insulating films 10a to 10e, conductor film 21 to be the internal wiring pattern 2, conductor 31 to be the via-hole conductor 3, conductor film to be the surface wiring patterns 4 and 5, capacitive electrode patterns 610 and 630, dielectric film This is for burning off organic components contained in 620, and is performed, for example, in a temperature range of 600 ° C. or lower. In the sintering process, the glass components of the insulating films 10a to 10e and the dielectric film 620 are crystallized and uniformly dispersed at the grain boundaries of the ceramic powder to give the laminate substrate 1 a certain strength, and at the same time, Conductive material of conductor film 21 to be wiring pattern 2, conductor 31 to be via-hole conductor 3, conductor film to be surface wiring patterns 4 and 5, conductive films 610 and 630 to be capacitive electrode patterns 61 and 63, for example, silver-based powder The grains are grown to reduce the resistance, and are integrated with the ceramic layers 1a to 1e and the dielectric ceramic layer 62. This is done in the temperature region where the peak temperature reaches 850-1050 ° C.

  The firing atmosphere varies depending on the material of the conductive paste and the like. As described above, in the case of an Ag-based conductor, the firing atmosphere is performed in an air (oxidizing) atmosphere or a neutral atmosphere, and in the case of a Cu-based conductor, a reducing atmosphere or medium is performed. Performed in a sex atmosphere.

  [Surface Treatment Step] Next, as a step (l) in FIG. 2, surface treatment is performed.

  In the surface treatment, a thick film resistive film or a protective film is baked on the main surface of the multilayer substrate 1 to mount various electronic components.

  As described above, the multilayer ceramic circuit board with a built-in capacitor according to the present invention is such that the multilayer substrate portion having the internal wiring pattern 2 is coated and dried with a ceramic slip material having a photocurable monomer, and the coated insulating film Then, selective exposure / development processing is performed to repeatedly form the conductor 31 to be the via-hole conductor 3 and the conductor film 21 to be the internal wiring pattern 2 by the conductive paste.

  The capacitor regions 6b and 6d are formed in the same process as the multilayer substrate, that is, the formation of the capacitor electrode pattern, the application / drying of the ceramic slip material as the dielectric film, and the selective process. It can be formed by patterning by exposure / development processing and formation of a capacitive electrode pattern. Thereby, it can form easily, without a manufacturing process becoming complicated.

  The capacitor electrode patterns 61 and 63 in the capacitor regions 6b and 6d are shaped by conductive paste printing, and the dielectric ceramic layer 62 is shaped by selective exposure and development of the dielectric film 620. Since the thickness of the dielectric ceramic layer 62 can be reliably and accurately formed by controlling the coating thickness of the dielectric ceramic slip material when forming the dielectric film 620, stable capacitance characteristics are derived. be able to.

  In addition, the capacitor electrode patterns 61 and 63 in the capacitor region can be formed independently in necessary places in consideration of the wiring of the internal circuit, and the predetermined internal wiring pattern 2 is an extension of the internal wiring pattern 2. In addition, it can be easily connected via the via-hole conductor 3.

  In the capacitor region, both main surfaces of the dielectric ceramic layer 62 are substantially in contact with the capacitor electrode patterns 61 and 63 and not in contact with the ceramic layers 1a to 1e, and the capacitor region 6b, Since the insulating film 10a to 10e and the dielectric film 620 are different in sintering behavior in the baking process, warping and peeling phenomenon can be effectively suppressed because the insulating film 10a to 10e and the dielectric film 620 are formed only in necessary portions inside 6d.

  In the above embodiment, the thickness of the dielectric ceramic layer in the capacitor region is sufficiently smaller than the thickness of the ceramic layers 1b and 1d where the capacitor regions 6b and 6d are disposed. In the forming step, the conductive film 630 that becomes the capacitive electrode pattern 63 on the upper side of the stacking step is performed as an independent step. For example, the thickness of the dielectric ceramic layer 62 is substantially the same as the ceramic layers 1b and 1d. If it is thick, the formation process of the conductor film 630 to be the capacitive electrode pattern 63 can be simultaneously formed in the formation process of the conductor film 21 to be the internal wiring pattern 2 formed on the insulating films 10b and 10d.

  In the above-described embodiment, the support substrate is used. However, for example, if a single plate or a multilayer ceramic circuit substrate on which a wiring pattern is already formed is used, the peeling step which is the step (i) in FIG. 2 is omitted. be able to.

  The step of forming a conductor film to be a surface wiring pattern that can be performed in FIG. 2J may be performed for each main surface before and after the peeling step that is the step in FIG. Further, it may be performed after performing a baking process that can be performed in FIG. In addition, the conductor film to be the wiring pattern on the one main surface side of the laminate substrate can be formed before the step of forming the insulating film 10e in FIG. 2A, and before the laminate is fired. You may load the division process process of forming a division | segmentation groove | channel and carrying out a division process along a division | segmentation groove | channel after baking. In other words, each of the processes (i) to (l) shown in FIG.

  In addition, the conductor film 21 to be the internal wiring pattern 2 and the conductor films 610 and 630 to be the capacitive electrode patterns 61 and 63 are formed by a conductive paste printing process / drying process. It is possible to add a curable monomer, apply it to the entire surface where the conductor films 21, 610, and 630 are formed, dry it, and form a predetermined pattern by selective exposure processing and development processing.

  In the above-described embodiment, the capacitor-embedded multilayer ceramic circuit board that can be fired at a low temperature has been described. However, for example, a capacitor-embedded multilayer ceramic circuit board that is fired at 1300 to 1600 ° C. may be used. In this case, a material that can be baked at 1300 to 1600 ° C. is selected.

  For example, a ceramic mainly composed of alumina is used as the material for the ceramic layers 1a to 1e, and the conductive materials for the internal wiring pattern 2, the via-hole conductor 3, and the capacitive electrode patterns 61 and 63 are MO, W, Aa−. A refractory metal material such as Pd is used, and the dielectric ceramic layer 62 is made of a dielectric ceramic material mainly composed of BaTiO3 and TiO2, respectively. Further, the binder is removed from a photocuring monomer, an organic binder, a solvent, or the like. The processing temperature is set to be higher corresponding to the sintering temperature, and the firing atmosphere is set to, for example, a forming gas in which hydrogen and nitrogen are mixed.

  According to the multilayer ceramic circuit board with a built-in capacitor according to the present invention, the capacitor region composed of a pair of capacitive electrode patterns and a dielectric ceramic layer sandwiched between the capacitor electrode patterns is formed at predetermined positions on the multilayer substrate. . Further, a ceramic layer is disposed around the capacitor region, and an internal wiring pattern and a via-hole conductor are also formed around the capacitor region. As a result, the capacitor area does not become an obstacle to the formation of internal wiring patterns between ceramic layers, the degree of freedom in designing the internal wiring patterns and the high density can be maintained, and at the same time, the freedom to design the wiring patterns on the surface side. The degree of improvement is improved, and high density can be maintained.

  Further, the capacitor region can be formed at a position where the connection is most efficient on the circuit wiring, and the high density of the internal wiring pattern can also be achieved.

  This is because the ceramic layer forms an insulating film by applying and drying a ceramic slip material containing a photocurable monomer, and further, a through-hole serving as a via-hole conductor is formed by selective exposure / development treatment. This is because the predetermined internal wiring pattern and / or the via-hole conductor are formed by printing a conductive paste. In addition, since the capacitive electrode pattern is present at the interface between the ceramic layer and the dielectric ceramic layer, the contact between the main surfaces of both layers is substantially eliminated, and no peeling or the like occurs during the manufacturing process.

  In addition, since the capacitor regions are individually formed, the thickness of the dielectric ceramic layer and the opposing area of the capacitor electrode pattern can be set according to the capacitance characteristics, so that the capacitance characteristics of the capacitor can be accurately formed.

  According to a first aspect of the present invention, a predetermined circuit comprising an internal wiring pattern and a via-hole conductor is disposed in a multilayer substrate formed by laminating a plurality of ceramic layers, and a pair of dielectric ceramic layers are connected to the circuit. The capacitor built-in type multilayer ceramic circuit board is formed by interposing capacitors sandwiched by the capacitor electrode patterns.

  A second invention is a method of manufacturing a multilayer ceramic circuit board with a built-in capacitor according to the first invention, wherein (1) a ceramic slip material having a photo-curable monomer is applied on a support substrate and dried by a ceramic treatment. A step of forming an insulating film to be a layer, (2) a step of forming a through hole in the insulating film by subjecting the insulating film to selective exposure processing and development processing, and (3) on the insulating film and in the through hole In addition, each step (1) of printing, filling, and drying a conductive paste to form a conductor film serving as an internal wiring pattern on the insulating film and forming a conductor serving as a via-hole conductor in the through hole (1) ) To (3) are sequentially repeated to form a conductor film and a via-hole conductor serving as an internal wiring pattern to be a predetermined circuit in an unfired laminated substrate, and the above (1) to (3) During the process, 4) a step of forming a conductor film to be one capacitor electrode pattern, (5) a step of forming a dielectric film to be the dielectric ceramic layer, and (6) a step of forming a conductor film to be the other capacitor electrode pattern. Each of the steps (4) to (5) is appropriately performed, the capacitor substrate is formed by forming the capacitor substrate in the unsintered stacked substrate so as to be interspersed with the capacitor region, and firing the stacked substrate. It is a manufacturing method of a multilayer ceramic circuit board.

  In each of the above steps, the step (3) and the step (4) can be performed in the same step. Further, the dielectric film to be a dielectric ceramic layer is formed by forming a dielectric coating film to be a dielectric ceramic layer by applying and drying a dielectric ceramic slip material having a photocurable monomer. It is desirable to form a dielectric film having a predetermined shape corresponding to the capacitor region by selective exposure processing / development processing, and then form a conductor film serving as a capacitor electrode pattern on the dielectric film. Moreover, when the thickness of a dielectric ceramic layer and the thickness of a ceramic layer are the same, the process of (3) and the process of (6) can also be performed by the same process.

  According to the multilayer ceramic circuit board with a built-in capacitor according to the first aspect of the present invention, capacitors each including a dielectric ceramic layer and a capacitor electrode pattern sandwiching the dielectric ceramic layer are scattered in the multilayer substrate. Will be provided with a ceramic layer.

  Accordingly, the capacitor can be formed only at a necessary location inside the multilayer ceramic circuit board, and high-density mounting on the substrate surface on which the conventional capacitor is disposed can be realized. In addition, the internal wiring pattern that contacts the ceramic layer around the capacitor can be formed regardless of the presence of the capacitor, the degree of freedom in designing the internal wiring pattern can be maintained, and the density can be increased.

  According to the second invention, even if the capacitor region formed by the steps (4) to (6) exists on the insulating film formed in the previous step, the insulating film covers the capacitor region. Thus, it forms by application | coating and drying of the ceramic slip material which has a photocurable monomer.

  Therefore, it is possible to cover the capacitor region with the insulating film, whereby the action of the first invention can be derived.

  Further, the structure of the capacitor is such that the dielectric film serving as the dielectric ceramic layer is sandwiched between the conductor films serving as two capacitive electrode patterns, and there is no planar contact between the dielectric film and the insulating film, Further, since the capacitor regions are scattered, no peeling or the like occurs during the manufacturing process.

  In addition, since the capacitor regions are individually formed, the thickness of the dielectric ceramic layer and the opposing area of the capacitor electrode pattern can be arbitrarily set according to the capacitance characteristics, so that the capacitance characteristics of the capacitor can be formed with high accuracy.

1 is a cross-sectional view of a multilayer ceramic substrate with a built-in capacitor according to the present invention. It is process drawing for demonstrating manufacture of the multilayer ceramic substrate with a built-in capacitor | condenser of this invention. (A)-(h) is the schematic in the main processes of manufacture of the capacitor | condenser multilayer ceramic substrate of this invention, respectively.

Explanation of symbols

10... Capacitor built-in type multilayer ceramic circuit board 1... Laminated body substrates 1 a to 1 e... Ceramic layers 10 a to 10 e. Wiring pattern 21... Conductor film 3 serving as an internal wiring pattern... Via hole conductor 31... Conductor 6 b and 6 d serving as a via hole conductor. ..Capacitance electrode patterns 610, 630... Conductor film 62 to be a capacitance electrode pattern... Dielectric ceramic layer 620.

Claims (1)

A predetermined circuit composed of an internal wiring pattern and a via-hole conductor is disposed in a multilayer substrate formed by laminating a plurality of ceramic layers, and the dielectric ceramic layer connected to the circuit is formed by a pair of capacitive electrode patterns. A multilayer ceramic circuit board with a built-in capacitor, in which the sandwiched capacitor is placed.

Images