JP2005275276A - Display device and display device control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of reducing luminance unevenness while suppressing an increase in power consumption. <P>SOLUTION: In the display device 10, a non-complementary driving transistor 18 drives an OLED 16 on the basis of a luminance signal. The driving transistor 18 corrects its operation timing by itself. A correcting transistor 24 performs ON/OFF control over the self-correction. A holding capacitor 26 holds a corrected luminance signal. The driving transistor 18 uses a temporarily supplied luminance signal to generate the luminance signal corrected based upon the operation threshold of the driving transistor 18 to thereby correct its operation by itself. The voltage of the luminance signal is gradually increased or decreased from a 1st ramp signal RP1 to control power supply to the OLED 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device, and more particularly to a technology of a display device using an organic EL.

  An organic electroluminescence (hereinafter referred to as “organic EL”) display device has attracted attention as a new flat display device. The organic EL display device is expected to take over the currently widely used liquid crystal display devices, and is in the midst of intense development competition for practical use and mass production.

  There are roughly two types of driving methods for organic EL display devices: an analog driving method and a digital driving method. The analog drive method is a method in which a current having a magnitude corresponding to the data voltage is supplied to each organic EL element, and the organic EL element is lit at a luminance corresponding to the data voltage. Various digital driving methods have been proposed. For example, the time gray scale method supplies each organic EL element with a pulse current having a duty ratio corresponding to the data voltage and lights it for a period corresponding to the data voltage. In other words, this is a method of expressing multiple gradations (see, for example, Patent Document 1).

Among the time gray scale methods, in the subfield driving method, one field (frame) period, which is a display cycle of one screen, is divided into a plurality of subfield (frame) periods, and lighting on / off in each subfield period is controlled. Thus, the organic EL element is turned on for a period according to the data voltage. At this time, the same current is supplied to the organic EL element, and the organic EL element emits light with the same luminance, but gradation is expressed by the length of the lighting time. The light emission period of each subfield has a length of 2 to the power of n (n = 0, 1, 2,..., N−1), for example, 1, 2, 4, 8, 16, 32, 64. , 128 is used to express 256 gradations by turning on and off the light emission period.
JP 2003-5709 A

  In the device described in Patent Document 1, a through current flows through the inverter circuit from the luminance signal writing period to the light emission period. This through current has a non-negligible magnitude compared to the drive current flowing through the organic EL element, and causes an increase in power consumption.

  The present invention has been made under the above-described background, and an object of the present invention is to provide a display device that can reduce luminance unevenness while suppressing an increase in power consumption.

  In order to solve the above problems, a display device according to an aspect of the present invention includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels drives a current-driven optical element, a non-complementary driving circuit that self-corrects the driving operation of the optical element based on a luminance signal, and controls on / off of the self-correction. A correction circuit; and a holding circuit that holds a luminance signal used for driving. The drive circuit generates a luminance signal corrected based on a predetermined signal that is temporarily passed and an operation threshold value of the drive circuit, and drives the optical element based on the corrected luminance signal to perform the driving operation. Self correct.

  Here, an organic light emitting diode can be assumed as the optical element, but the present invention is not limited to this. A MOS (Metal Oxide Semiconductor) transistor or a thin film transistor (TFT) can be assumed as the drive circuit and the correction circuit, but the present invention is not limited to this. The “operation threshold value of the driving circuit” may be an operation threshold voltage of the transistor. The “non-complementary drive circuit” is intended to exclude a drive circuit of a type in which a through current flows, such as an inverter. Therefore, while this “non-complementary drive circuit” performs self-correction, a signal used for correction is used. The signal line is not connected to the ground potential as it is, and no through current flows. The holding circuit may include a capacitor.

  According to this aspect, the self-correction is performed by the non-complementary drive circuit based on the characteristics of the drive circuit, so that no through current is generated during the correction period. Therefore, it is possible to drive the optical element without being affected by variations in characteristics of the drive circuit while preventing an increase in power consumption, and to avoid uneven brightness of the display device.

  Each of the plurality of pixels may further include a circuit that controls driving of the optical element by the driving circuit by gradually decreasing or gradually increasing the voltage of the held luminance signal. The drive circuit may self-correct the operation timing of the drive circuit. With each configuration including these non-complementary driving circuits, it is possible to realize a time gray scale display device that avoids uneven luminance due to variations in characteristics of the driving circuits while preventing an increase in power consumption.

  The drive circuit may perform self-correction using a luminance signal before correction that is temporarily passed as a predetermined signal. Each of the plurality of pixels may further include a power supply circuit that cuts off the drive circuit from the power supply line during self-correction. As a result, it is possible to correct the variation in characteristics of the drive circuit without using the current supplied from the power supply line, and to avoid uneven brightness.

  Another embodiment of the present invention is also a display device. This apparatus includes a plurality of pixels arranged in a matrix. Each of the plurality of pixels is connected to a current-driven optical element, a driving circuit that drives the optical element based on a luminance signal, and self-corrects the driving operation, and the driving circuit. A power supply circuit for controlling the power supply to the optical element via the drive circuit, a writing circuit connected to the drive circuit for controlling the input of the luminance signal to the pixel, and driving the signal flowing through the drive circuit for self-correction A correction circuit that connects or cuts off a path to be input to the circuit, a holding capacitor that holds a signal input to the driving circuit, and an optical by the driving circuit by gradually decreasing or gradually increasing the voltage of the signal held through the holding capacitor A circuit for controlling driving of the element; and a reset circuit for connecting or blocking a path of a driving current to the optical element. The driving circuit generates a luminance signal corrected based on the luminance signal temporarily passed through the writing circuit and the operation threshold value of the driving circuit, and drives the optical element based on the corrected luminance signal. The power supply circuit cuts off the power supply to the optical element through the drive circuit during the self-correction, and the reset circuit drives the drive current to the optical element during the self-correction. Block the route.

  A MOS transistor and a thin film transistor can be assumed as the driving circuit, the power supply circuit, the writing circuit, the correction circuit, and the reset circuit, respectively, but the present invention is not limited to this.

  According to this aspect, the driving circuit self-corrects the luminance signal based on the characteristics of the driving circuit, and avoids luminance unevenness due to characteristic variations of the driving circuit. In the case of this configuration, since no through current is generated during the correction period, an increase in power consumption can be prevented.

  Yet another embodiment of the present invention is a display device control method. In this method, a predetermined signal is passed through a non-complementary driving circuit that drives a current-driven optical element, and a luminance signal is corrected by correcting the predetermined signal flowing through the driving circuit with an operating threshold value of the driving circuit. Generating and maintaining the corrected luminance signal in the driving circuit, blocking a predetermined signal flow to the driving circuit, and increasing or decreasing the voltage of the held luminance signal. Supplying a drive current to the optical element.

  According to this aspect, the self-correction is performed by the non-complementary drive circuit based on the characteristics of the drive circuit, so that no through current is generated during the correction period. Therefore, it is possible to drive the optical element without being affected by variations in characteristics of the drive circuit while preventing an increase in power consumption, and to avoid uneven brightness of the display device.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, it is possible to improve luminance unevenness while suppressing power consumption in a display device.

(Example 1)
FIG. 1 illustrates a basic configuration of pixels included in the display device according to the first embodiment. In the display device 10, the first pixel 12 includes an organic light emitting diode (hereinafter, “organic light emitting diode” is referred to as “OLED”) 16, a reset transistor 14, a driving transistor 18, a writing transistor 20, a power supply transistor 22, a correction. A transistor 24 and a storage capacitor 26 are included. The OLED 16 is a current-driven optical element, and emits light with an intensity corresponding to the current value when a drive current flows. However, in this embodiment, the value of the drive current is almost constant, and the gradation is expressed by the difference in the length of the light emission period for each pixel.

  Drive transistor 18 and power supply transistor 22 are each a p-channel MOS transistor. Each of the reset transistor 14, the write transistor 20, and the correction transistor 24 is an n-channel MOS transistor. The drive transistor 18 functions as a drive circuit that drives the light emission of the OLED 16. The reset transistor 14 functions as a reset circuit that switches between interruption and connection of the signal path of the current that drives the OLED 16.

  The write transistor 20 has a drain electrode connected to the first data signal line DL 1, and a source electrode connected to the drain electrode of the power supply transistor 22 and the source electrode of the drive transistor 18. The gate electrode of the write transistor 20 is connected to the first selection signal line SL1. The power supply transistor 22 has a source electrode connected to the first power supply line VDD1 and a gate electrode connected to the first selection signal line SL1. The drain electrode of the drive transistor 18 is connected to the source electrode of the correction transistor 24 and the drain electrode of the reset transistor 14. The drain electrode of the correction transistor 24 is connected to the gate electrode of the driving transistor 18 and one end of the storage capacitor 26. The other end of the storage capacitor 26 is connected to the first ramp signal line RP1. The gate electrode of the correction transistor 24 is connected to the first selection signal line SL1. The reset transistor 14 has a source electrode connected to the anode of the OLED 16 and a gate electrode connected to the first reset line RS1. The holding capacitor 26 holds a luminance signal set in the gate electrode of the driving transistor 18.

  FIG. 2 shows an arrangement relationship of a plurality of pixels included in the display device. In the display device 10, a plurality of pixels are arranged in a matrix. For example, a plurality of pixels such as the first pixel 12 and the second pixel 30 are arranged in the horizontal direction in the first row, and a plurality of pixels such as the third pixel 32 and the fourth pixel 34 are arranged in the horizontal direction in the second row. Is done. The first pixel 12 is connected to the first selection signal line SL1, the first data signal line DL1, the first power supply line VDD1, the first reset line RS1, and the first ramp signal line RP1. The second pixel 30 is connected to the first selection signal line SL1, the second data signal line DL2, the second power supply line VDD2, the first reset line RS1, and the first ramp signal line RP1. The third pixel 32 is connected to the second selection signal line SL2, the first data signal line DL1, the first power supply line VDD1, the second reset line RS2, and the second ramp signal line RP2. The fourth pixel 34 is connected to the second selection signal line SL2, the second data signal line DL2, the second power supply line VDD2, the second reset line RS2, and the second ramp signal line RP2. Each pixel including the second pixel 30, the third pixel 32, and the fourth pixel 34 includes the same configuration as the first pixel 12.

  FIG. 3 is a time chart showing the relationship of the state change of each signal input to the first pixel 12. As shown in the figure, one horizontal line selection period is divided into two, and each pixel is controlled with the first half being a luminance signal writing period and the second half being a light emission period. In the writing period, when the selection signal input from the first selection signal line SL1 becomes high, the writing transistor 20 and the correction transistor 24 are turned on, and the power supply transistor 22 is turned off. At this time, the reset signal input from the first reset line RS1 is high, and the reset transistor 14 is turned on. Therefore, since the node 28 is connected to the OLED 16, the potential of the node 28 is lowered and reset. When the reset signal goes low and the reset transistor 14 is turned off, the reset period of the node 28 ends.

  At the end of the reset period, since the potential of the node 28 is sufficiently lower than the potential of the luminance signal input from the first data signal line DL1, the driving transistor 18 is turned on. The luminance signal flowing through the driving transistor 18 is input to the node 28 and written to the gate electrode of the driving transistor 18. The driving transistor 18 is turned off when the node 28 becomes a potential lower than the voltage Vdata of the luminance signal by the threshold voltage Vtp of the driving transistor 18. That is, the value of Vdata−Vtp is set in the node 28. Even when the first selection signal line SL1 becomes low and the writing transistor 20 and the correction transistor 24 are turned off, the value of the node 28 is held by the holding capacitor 26.

  When the first selection signal line SL1 becomes low, the power supply transistor 22 is turned on. When the first reset line RS1 becomes high, the reset transistor 14 is also turned on. At this time, the power supply voltage supplied from the first power supply line VDD1 is set lower than the low level voltage of the luminance signal input from the first data signal line DL1, and the potential of the node 28 is Vdata−Vtp. Therefore, the drive transistor 18 remains off. Therefore, no current flows through the driving transistor 18, and the OLED 16 remains in a non-light emitting state.

  During the light emission period, a ramp signal is input to the storage capacitor 26 from the first ramp signal line RP1. The potential of the ramp signal is fixed at a high level during the writing period, and gradually decreases from the high level when the light emission period starts. Therefore, the potential of the node 28 also gradually decreases from Vdata−Vtp due to coupling with the storage capacitor 26. Each pixel included in the display device 10 is controlled in the process as described above.

  Among the plurality of pixels included in the display device 10, a current flows through the driving transistor 18 of the pixel in order from the pixel in which the potential of the node 28 has reached a value smaller than the power supply potential by Vtp, and the OLED 16 emits light. Since the potential of the ramp signal returns to the high level that is the initial value immediately before the end of the light emission period, the potential of the node 28 also returns to the initial value Vdata-Vtp, and the OLEDs 16 of all the pixels included in the display device 10 are in the non-light emitting state. become. In this way, multi-gradation display is realized by modulating the lighting time of each pixel based on the voltage of the luminance signal.

  As described above, Vdata−Vtp, which is a value obtained by correcting the voltage of the luminance signal with the threshold voltage of the drive transistor 18, is written to the gate electrode of the drive transistor 18, and light emission is started by the ramp signal with reference to the potential Timing is determined. In this case, since the OLED 16 can emit light without depending on the threshold voltage of the driving transistor 18, display variation does not occur between pixels. Further, since the driving transistor 18 is in an off state during the writing period, no current flows through the OLED 16 during this period. In particular, since the driving transistor 18 is a non-complementary driving circuit, no through current flows and the power consumption of the entire display device 10 can be reduced.

(Example 2)
The display device according to the present embodiment is different from the display device according to the first embodiment in the configuration or arrangement of each transistor included therein. Further, the configuration of the signal lines and the polarity of some of the signal lines are different from those in the first embodiment. Hereinafter, the description will focus on the differences, and the description of the common points will be omitted as appropriate.

  FIG. 4 illustrates a basic configuration of pixels included in the display device according to the second embodiment. In the display device 10, the first pixel 12 includes an OLED 16, a reset transistor 14, a drive transistor 18, a write transistor 20, a power supply transistor 22, a correction transistor 24, and a storage capacitor 26. However, it differs from the first embodiment in which the write transistor 20 is an n-channel MOS transistor in that the write transistor 20 is a p-channel MOS transistor. Further, the power supply transistor 22 is an n-channel MOS transistor, and is different from the first embodiment in which the power supply transistor 22 is a p-channel MOS transistor. Further, the second embodiment is different from the first embodiment in that the gate electrode of the correction transistor 24 is connected to the correction signal line CR1.

  The write transistor 20 has a source electrode connected to the first data signal line DL 1, and a drain electrode connected to the source electrode of the power supply transistor 22 and the source electrode of the drive transistor 18. The gate electrode of the write transistor 20 is connected to the first selection signal line SL1. The power supply transistor 22 has a drain electrode connected to the first power supply line VDD1 and a gate electrode connected to the first selection signal line SL1. The drain electrode of the drive transistor 18 is connected to the source electrode of the correction transistor 24 and the drain electrode of the reset transistor 14. The drain electrode of the correction transistor 24 is connected to the gate electrode of the driving transistor 18 and one end of the storage capacitor 26. The other end of the storage capacitor 26 is connected to the first ramp signal line RP1. The gate electrode of the correction transistor 24 is connected to the correction signal line CR1. The reset transistor 14 has a source electrode connected to the anode of the OLED 16 and a gate electrode connected to the first reset line RS1. The holding capacitor 26 holds a luminance signal set in the gate electrode of the driving transistor 18.

  Also in this embodiment, one horizontal line selection period is divided into two, and each pixel is controlled with the first half being a luminance signal writing period and the second half being a light emission period. Here, since the write transistor 20 is a p-channel MOS transistor and the power supply transistor 22 is an n-channel MOS transistor, the polarity of the selection signal of the first selection signal line SL1 is obtained by inverting the selection signal in the first embodiment. It becomes a shape. Further, since the correction transistor 24 is controlled by the correction signal of the correction signal line CR1, in the writing period, the correction signal becomes high when the selection signal is low, the writing transistor 20 and the correction transistor 24 are turned on, and the power supply Supply transistor 22 is turned off. Conversely, when the selection signal goes high and the correction signal goes low, the write transistor 20 and the correction transistor 24 are turned off and the power supply transistor 22 is turned on. The voltage change of other signals and the operation of each transistor are the same as in the first embodiment.

  Also with the above configuration, since the value Vdata−Vtp obtained by correcting the voltage of the luminance signal with the threshold voltage of the drive transistor 18 is written to the gate electrode of the drive transistor 18, it depends on the threshold voltage of the drive transistor 18. Without causing the OLED 16 to emit light, and display variation does not occur between pixels. During the writing period, the driving transistor 18 is turned off, and no current flows through the OLED 16, and no through current flows through the driving transistor 18, so that the power consumption of the entire display device 10 can be reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are also within the scope of the present invention. . Hereinafter, modifications will be described.

  In each embodiment, the driving transistor 18 is operated by gradually decreasing the ramp signal input from the first ramp signal line RP1. In the modification, the first ramp signal line RP1 may be gradually increased. In this case, a low level ramp signal is once input to each pixel, and each driving transistor 18 is operated to cause the OLED 16 to emit light, and then the voltage of the ramp signal is gradually increased. Among the plurality of pixels, the drive transistor 18 of the pixel is turned off sequentially from the pixel in which the potential of the node 28 has reached a value smaller than the power supply potential by Vtp, and the OLED 16 is turned off. In this way, multi-gradation display is realized by modulating the lighting time of each pixel.

  In each embodiment, the configuration in which both the write transistor 20 and the power supply transistor 22 are connected to the first selection signal line SL1 and controlled by the same selection signal has been described. In the modification, the write transistor 20 and the power supply transistor 22 may be connected to separate signal lines and controlled by separate signals. In addition to controlling each transistor with a separate signal, all the transistors may be configured with p-channel MOS transistors.

3 is a diagram illustrating a basic configuration of a pixel included in a display device in Example 1. FIG. It is a figure which shows the arrangement | positioning relationship of the some pixel contained in a display apparatus. It is a time chart which shows the relationship of the state change of each signal inputted into the 1st pixel. 6 is a diagram illustrating a basic configuration of a pixel included in a display device in Example 2. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Display apparatus, 12 1st pixel, 14 Reset transistor, 16 OLED, 18 Drive transistor, 20 Write transistor, 22 Power supply transistor, 24 Correction transistor, 26 Retention capacity, 28 Node, 30 2nd pixel, 32 3rd pixel , 34 fourth pixel.

Claims (6)

A plurality of pixels arranged in a matrix,
Each of the plurality of pixels is
A current-driven optical element;
A non-complementary drive circuit that drives the optical element based on a luminance signal and that self-corrects the drive operation;
A correction circuit for controlling on / off of the self-correction;
A holding circuit for holding a luminance signal used for the driving,
The driving circuit generates a luminance signal corrected based on a predetermined signal that is temporarily passed and an operation threshold value of the driving circuit, and drives the optical element based on the corrected luminance signal. A display device characterized by self-correcting a driving operation. Each of the plurality of pixels further includes a circuit that controls driving of the optical element by the driving circuit by gradually decreasing or gradually increasing the voltage of the held luminance signal,
The display device according to claim 1, wherein the drive circuit self-corrects the operation timing of the drive circuit.   The display device according to claim 1, wherein the driving circuit performs self-correction using a luminance signal before correction that is temporarily passed as the predetermined signal.   4. The display device according to claim 1, wherein each of the plurality of pixels further includes a power supply circuit that cuts off the drive circuit from a power supply line during the self-correction. 5. A plurality of pixels arranged in a matrix,
Each of the plurality of pixels is
A current-driven optical element;
A driving circuit for driving the optical element based on a luminance signal and self-correcting the driving operation;
A power supply circuit that is connected to the drive circuit and controls power supply to the optical element via the drive circuit;
A writing circuit connected to the driving circuit and controlling input of the luminance signal to the pixel;
A correction circuit for connecting or blocking a path for inputting a signal flowing through the drive circuit to the drive circuit for the self-correction;
A holding capacitor for holding a signal input to the driving circuit;
A circuit for controlling driving of the optical element by the driving circuit by gradually decreasing or gradually increasing the voltage of the held signal through the holding capacitor;
A reset circuit for connecting or blocking a path of a driving current to the optical element;
Including
The driving circuit generates a luminance signal corrected based on a luminance signal temporarily passed through the writing circuit and an operation threshold value of the driving circuit, and the optical circuit based on the corrected luminance signal By self-correcting the driving operation by driving the element,
The power supply circuit shuts off power supply to the optical element via the drive circuit during the self-correction,
The display device, wherein the reset circuit blocks a path of a drive current to the optical element during the self-correction. Passing a predetermined signal through a non-complementary drive circuit that drives a current-driven optical element;
Correcting the predetermined signal flowing through the drive circuit with an operating threshold value of the drive circuit to generate a luminance signal;
Setting and holding the corrected luminance signal in the drive circuit;
Blocking the flow of the predetermined signal to the drive circuit;
Supplying a driving current to the optical element by increasing or decreasing the voltage of the held luminance signal;
A display device control method comprising:

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