JP2005259960A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide techniques capable of reducing man-hour, unit cost, TAT, device operators and the like, by performing efficiently wafer rearrangement after wafer rear-face grinding in the manufacturing process of a semiconductor integrated circuit device. <P>SOLUTION: It is made possible to perform a wafer rearrangement process and a marking process with one device by executing the steps as follows: a probe inspection (P inspection) is conducted about each wafer (Step S602) after finishing the previous process (Step S600); the rear face of the wafer is ground (BG) (Step S604) using a marking apparatus, the lot number and wafer number which are printed in the wafer surface are read; marking of the lot number and the wafer number is carried out to the wafer rear face; and by using the marking apparatus on the basis of the read wafer number, each wafer in the wafer cassette is rearranged in order of the probe inspection (Step S605). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to rearrangement of semiconductor wafers in a manufacturing process of a semiconductor integrated circuit device.

  For example, as a technique studied by the present inventor, the following techniques can be cited regarding rearrangement of semiconductor wafers (hereinafter simply referred to as “wafers”) in the manufacturing process of a semiconductor integrated circuit device.

  While the handler sequentially takes out the wafers from the cassette of the loader unit, reads the wafer number of the wafers by the print reading unit, carries the wafer to be inspected into the inspection unit, performs the inspection, and performs the inspection In addition, the wafer numbers that are not to be inspected are sequentially read by the print reading unit, and the wafers stored in the cassette are rearranged so that the wafer numbers are in a predetermined order. A wafer processing apparatus capable of reducing the overall processing time required for inspection processing (see, for example, Patent Document 1).

The wafers divided into lots are taken out one by one into the thickness measuring machine, and the thickness information is stored in the thickness information storage unit together with information on the wafers using bar code marks, and all measurements are completed. Until the original state is reproduced with the temporary cassette until the wafer is stored in the batch cassette by the handling robot, the wafer is automatically classified into thicknesses, and the process can be unmanned. A wafer thickness classification device that can be used (see, for example, Patent Document 2).
JP 2002-33369 A (page 4-5, FIGS. 1 and 3) JP-A-6-260546 (page 8, FIG. 2)

  By the way, as a result of examination of the technique of the method for manufacturing a semiconductor integrated circuit device as described above, the following has been clarified.

  In order to facilitate analysis of causes when problems occur in the semiconductor integrated circuit device market, that is, to improve traceability, it is necessary to introduce a laser marking device that uses a laser to mark characters and other symbols on the backside of the wafer It has become. However, a laser marking process is added, and the number of processes increases by one, which increases man-hours and unit prices, increases TAT (Turn Around Time), and increases the number of equipment operators.

  FIG. 15 shows an example of steps before and after the laser marking step studied by the inventor as a premise of the present invention. In the manufacturing process of the semiconductor integrated circuit device, after the previous step (step S600), bumps (BUMP) are formed (step S601), probe inspection (P inspection) is performed (step S602), and wafer inspection (W inspection) is performed. (Step S603), back grinding (BG) is performed (step S604), and the wafer is rearranged by the wafer rearrangement apparatus (step S605a). In the case of chip shipment, after the wafer rearrangement in step S605a, laser marking is performed on the back surface of the wafer (step S605b), dicing, jig filling, etc. are performed (step S606), and chips are shipped (step S607). In the case of wafer shipment, the wafer is shipped after the wafer rearrangement in step S605a (step S608).

  In the back grinding (BG) process in step S604, since a plurality of wafers are processed simultaneously by one apparatus, the order of the wafers in the wafer cassette may be changed if a manual operation is added when a trouble occurs in the processing apparatus. There is. In the P inspection data (probe inspection result), the first data corresponds to the first wafer cassette and is arranged in the following order. Therefore, if the wafer arrangement order in the cassette is changed, the P inspection data and the wafer are changed. Will not be able to respond. Therefore, after the back surface grinding process, it is necessary to restore the wafer arrangement order in the wafer cassette using the wafer rearrangement apparatus.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a technique capable of efficiently performing wafer rearrangement after wafer back grinding in the manufacturing process of a semiconductor integrated circuit device and reducing man-hours / unit price, TAT, equipment operator, and the like. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a probe inspection is performed on each wafer after the wafer processing step, the back surface of the wafer is ground, and the surface of the wafer is printed using a marking device. The lot number and the wafer number are read, the lot number and the wafer number are marked on the back surface of the wafer, and the probe inspection is performed on each wafer in a wafer cassette using the marking device based on the read wafer number. By rearranging in order, the wafer rearrangement step and the marking step can be performed by one apparatus.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Wafer rearrangement and laser marking on the backside of the wafer can be performed with the same apparatus.

  (2) Since the wafer rearrangement step and the laser marking step can be performed with one apparatus, it is possible to reduce one step.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a process flow diagram showing a manufacturing process in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows each process in the method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. It is a figure which shows the processing base of.

  First, an example of the manufacturing process in the present embodiment will be described with reference to FIG. In the manufacturing process of the semiconductor integrated circuit device according to the present embodiment, after the previous process (step S600), bumps (BUMP) are formed (step S601), probe inspection (P inspection) is performed (step S602), and wafer inspection is performed. (W inspection) is performed (step S603), back surface grinding (BG) is performed (step S604), and laser marking and wafer rearrangement are performed on the wafer rear surface by a laser marking device with a wafer rearrangement function (step S605). ). In the case of chip shipment, dicing and jig packing are performed after the rear surface laser marking and wafer rearrangement in step S605 (step S606), and the chip is shipped (step S607). In the case of wafer shipment, the wafer is shipped after the wafer rearrangement in step S605 (step S608).

  In the pre-process (wafer processing process) of step S600, processes such as lithography, impurity introduction, diffusion, oxidation, and etching are performed to form a circuit element pattern on the wafer surface.

  In the bump forming step in step S601, a protruding electrode (bump) is formed on the pad with gold (Au) or the like.

  In the probe inspection process in step S602, a needle (probe) is applied to the electrode to test the electrical characteristics. The probe inspection is performed by sequentially taking out the wafers in the respective slots in the wafer cassette in the order of the slots. The slot number in the wafer cassette corresponds to the wafer number. The P test data (probe test results) is stored in the order of probe tests. That is, they are stored in order of wafer number and slot number.

  In the wafer inspection process in step S603, an appearance inspection of the wafer is performed.

  In the wafer back grinding process in step S604, the wafer surface is protected with a resin tape material, vacuum-adsorbed on a stage, the wafer back surface is ground with a diamond grindstone, and the protective tape is peeled off and the wafer is cleaned. Since wafer backside grinding processes a plurality of wafers simultaneously, the order of the wafers in the wafer cassette may be changed due to an apparatus trouble or the like. Therefore, it is necessary to rearrange the wafers in the wafer cassette later in the order of the wafer numbers.

  In the back surface laser marking and wafer rearrangement process in step S605, the lot number and wafer number information printed on the wafer surface is read by a laser marking device with a wafer rearrangement function, and the lot number is printed on the rear surface of the wafer. Information such as wafer number, chip address, bump base, and manufacturing date is marked for each chip. Further, the wafers in the cassette are rearranged using the free time. The wafers are rearranged in the order of the read wafer numbers in order to be able to correspond to the P inspection data.

  In the dicing and jig packing process in step S606, the wafer is divided (cut) into chips, and non-defective chips are selected and placed on a shipping pallet. At that time, the wafers are stored in a shipping pallet in the order of the wafer numbers and shipped.

  Next, referring to FIG. 2, an example of the processing base of each process in the present embodiment will be described. Each processing step shown in FIG. 1 is not performed at one business site, that is, one site, but is performed at a plurality of processing sites according to the production status. The processing base may be a different factory within the same company, or a subcontractor's other factory. For example, as shown in FIG. 2, the pre-process is performed at the base of the pre-process department a, the pre-process department b, the pre-process department c, and the pre-process department d. Wafers processed in the pre-process department a12, the pre-process department b13, and the pre-process department c14 are accepted in the accept department a16, and are distributed to the bump department a17, bump department b18, bump department c19, bump department d20, and bump department e21. And bumps are formed. The wafer processed in the pre-process department d15 is accepted in the bump department e21 to form bumps. The wafer on which the bumps are formed is received by the receiving department b22 and sent to the P inspection department a23, the P inspection department b24, the P inspection department c25, the P inspection department d26, and the P inspection department e27 for probe inspection. . Further, the wafer on which the bump is formed in the bump section e21 is sent to the P inspection section f28, and the probe inspection is performed. Wafers subjected to probe inspection in the P inspection department a23, P inspection department b24, P inspection department c25, P inspection department d26 and P inspection department e27 are subjected to back grinding in the BG department a29 and probe inspection in the P inspection department f28. The wafer subjected to is subjected to back grinding at the BG department b30. The wafer subjected to the back grinding in the BG department a29 is accepted in the receiving department c31 and is delivered to the post-process department a33, the post-process department b34, the post-process department c35, and the post-process department d36. The wafer subjected to back grinding in the BG department b30 is accepted in the acceptance department d32 and delivered to the post-process department a33, the post-process department b34, the post-process department c35, and the post-process department d36. In the post-process department a33, the post-process department b34, the post-process department c35, and the post-process department d36, back surface laser marking, wafer rearrangement, dicing, and jig filling are performed. Shipment inspection is carried out in the shipment inspection department a37 and shipped. The chips divided from the wafers in the post-process department b34, the post-process department c35, and the post-process department d36 are shipped and inspected in the shipping inspection department b38. In the subsequent process, the wafer is divided into chips.

  FIG. 3 is a cross-sectional view showing a mounting example of a semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. The semiconductor integrated circuit device according to the present embodiment is an LCD driver, for example, and includes an LSI chip 39, bumps 40, leads 41, a substrate 42, a tape 43, a resin 44, and the like, and the bumps 40 are formed on the LSI chip 39. The bump 40 and the lead 41 on the substrate 42 are connected, and the LSI chip 39 is fixed by a tape 43 and sealed by a resin 44. The LSI chip 39 divided and shipped from the wafer in a subsequent process is mounted at the receiving destination of the LSI chip 39.

  FIG. 4 is a view showing the back surface of the LSI chip laser-marked by the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. As shown in FIG. 4, the manufacturing date, lot number, bump base, wafer number, in-wafer chip address, and the like are marked on the back surface of the LSI chip 39 by a laser marking device with a wafer rearrangement function, which will be described later. The bump base indicates a base where the bump is formed. The chip address indicates the coordinates of each chip in the wafer. The wafer number corresponds to the slot number in the wafer cassette.

  FIG. 5 is a diagram showing the surface of a wafer to be processed in the method for manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention. As shown in FIG. 5, a plurality of LSI chips 39 are formed on the surface of the wafer 45, and in the vicinity of the orientation flat on the outer periphery of the wafer 45, the product type name, lot number, wafer number and the like are printed. A laser marking apparatus with a wafer rearrangement function, which will be described later, reads these lot numbers and wafer numbers, and performs laser marking and wafer rearrangement on the back surface of the wafer 45 based on them.

  FIG. 6 is a block diagram showing a configuration of a laser marking device with a wafer rearrangement function in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 7 shows a configuration of the laser marking device with a wafer rearrangement function. FIG. As shown in FIGS. 6 and 7, the laser marking device 4 with a wafer rearrangement function according to the present embodiment includes a semiconductor wafer transfer unit 1a, an image reading recognition unit 5, a laser mark unit 8, a standby wafer cassette (second The semiconductor wafer transfer unit 1a, the image reading recognition unit 5 and the laser mark unit 8 are electrically connected to the control unit 6 and controlled by the control unit 6.

  FIG. 7 is a view of the laser marking device 4 with a wafer rearrangement function as viewed from above. As shown in FIG. 7, the semiconductor wafer transfer unit 1a includes a transfer arm 1, a wafer cassette stage 10, a standby wafer cassette 9, and the like. The transfer arm 1 is located near the center of the laser marking device 4 with a wafer rearrangement function. Has been placed.

  The controller 6 controls each function in the laser marking device 4 with a wafer rearrangement function. The semiconductor wafer transfer unit 1 a is configured to transfer a wafer by the transfer arm 1 among the laser mark unit 8, the image reading recognition unit 5, the wafer cassette stage 10, and the standby wafer cassette 9. The image reading / recognizing unit 5 reads a lot number, a wafer number, and the like printed on the wafer surface by image recognition. In addition, alignment of the wafer orientation flat and notch is also performed. For example, an OCR (Optical Character Reader) is used as the image recognition means. The laser mark unit 8 prints the manufacturing date, lot number, wafer number, bump base, chip address, etc. on the back surface of the wafer with a laser for each chip. The wafer cassette stage 10 is for placing a wafer cassette (first wafer cassette) 2 containing wafers. Although the number of wafer cassette stages 10 is one in FIG. 7, the number is not limited to this, and a plurality of wafer cassette stages 10 may be provided. If there are a plurality of wafer cassette stages 10, a plurality of wafer cassettes 2 can be processed simultaneously. The standby wafer cassette 9 is a wafer cassette that temporarily waits for wafer rearrangement, and is used as a buffer. The host 7 is a host computer that exchanges processing data such as recipes and performs overall control with the laser marking device 4 with a wafer rearrangement function via the control unit 6.

  FIG. 8 is a flowchart showing an operation flow of the laser marking apparatus with a wafer rearrangement function of FIG. With reference to FIG. 8, an example of a method for manufacturing a semiconductor integrated circuit device according to the present embodiment will be described using a laser marking device 4 with a wafer rearrangement function.

  First, the operator sets the wafer cassette 2 containing the wafer on the wafer cassette stage 10 of the laser marking device 4 with a wafer rearrangement function.

  When the operator gives an instruction to start construction, the transfer arm 1 removes one wafer from the wafer cassette 2 on the wafer cassette stage 10 and loads the wafer onto the image reading recognition unit 5 (step S100).

  The image reading and recognition unit 5 recognizes the lot number and wafer number printed on the wafer surface. Also, alignment of the orientation flat (notch) is executed (step S101).

  The laser marking device 4 with a wafer rearrangement function makes an inquiry to the host 7 using the lot number recognized as an image as a key, and calls a recipe corresponding to the lot number. When the inquiry cannot be made, or when the laser marking device 4 with the wafer rearrangement function is in the manual mode, the operator inputs a recipe (step S102).

  The wafer is moved from the image reading recognition unit 5 to the laser mark unit 8 by the transfer arm 1 (step S103).

  The laser mark unit 8 performs marking on the back surface of the wafer according to a recipe instruction (step S104).

  After the marking, the wafer is moved from the laser mark unit 8 to the wafer cassette 2 by the transfer arm 1 and unloaded (collected and stored) in the same wafer cassette slot as the wafer number read by image recognition (step S105). . At this time, in step S106, it is confirmed whether or not there is a wafer in the same wafer cassette slot as the wafer number. If there is no wafer, that is, if the slot is empty (Yes), unloading is performed as it is (step S107). ). If there is another wafer in the slot (No), the wafer is temporarily loaded (stored) in the standby wafer cassette 9 (step S108).

  In step S109, it is confirmed whether or not all the wafers in the wafer cassette 2 have been started. If all the wafers have not been started (No), steps S100 to S109 are repeated.

  If all the wafers in the wafer cassette 2 have been started (Yes), the process proceeds to step S110 to check whether all the loaded wafers are unloaded in the wafer cassette 2. If all the wafers loaded from the wafer cassette 2 have been unloaded (Yes), the construction is finished as it is.

  When all the wafers loaded from the wafer cassette 2 have not been unloaded to the wafer cassette 2 (No), all the wafers temporarily waiting in the standby wafer cassette 9 are unloaded into the same slot as the wafer number ( Step S111), the construction is finished.

  Therefore, according to the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, after the completion of all the wafers, the wafer is unloaded into the same slot as the wafer number of the wafer temporarily waiting in the standby wafer cassette 9. By loading, wafers can be rearranged with the same apparatus, and one process can be reduced.

  FIG. 9 is a flowchart showing another operation flow of the laser marking apparatus with a wafer rearrangement function of FIG. With reference to FIG. 9, another example of the semiconductor integrated circuit device manufacturing method according to the present embodiment will be described using a laser marking device 4 with a wafer rearrangement function.

  In FIG. 9, steps S200 to S204 are the same as steps S100 to S104 of the embodiment shown in FIG.

  While marking on the back surface of the wafer in step S204, the waiting time is used to transfer another wafer in the next slot in the wafer cassette 2 from the wafer cassette 2 to the image reading / recognition unit by the transfer arm 1. 5 is loaded (step S205).

  When the marking in step S204 is completed, the marking-completed wafer is moved from the laser mark portion 8 to the wafer cassette 2 by the transfer arm 1 and unloaded to the same wafer cassette slot as the wafer number read by image recognition (step S204). Step S206). At this time, in step S207, it is confirmed whether or not there is a wafer in the same wafer cassette slot as the wafer number. If the slot is empty (Yes), the wafer cassette slot having the same number as the wafer number is unloaded. Load (step S208). If there is another wafer in the slot (No), the wafer is temporarily loaded into the standby wafer cassette 9 (step S209).

In step S210, it is checked whether or not all the wafers in the wafer cassette 2 have been started. If all the wafers have been started (Yes), the start of the process is finished as it is.
If all the wafers have not been started, the process proceeds to step S211, where it is confirmed whether the empty slot number of the wafer cassette 2 is the same as the wafer number temporarily waiting in the standby wafer cassette 9 or not ( No) goes to step S201. When the empty slot number of the wafer cassette 2 is the same as the wafer number temporarily waiting in the standby wafer cassette 9 (Yes), a wafer having the same wafer number as the empty slot number of the wafer cassette 2 is waited by the transfer arm 1. The wafer cassette 9 moves to the wafer cassette 2, unloads the wafer into the empty slot in the wafer cassette 2 (step S212), and proceeds to step S201.

  Therefore, according to the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, when the same slot in the wafer cassette 2 as the wafer number of the wafer temporarily waiting in the standby wafer cassette 9 is vacated, By unloading, the wafer can be rearranged with the same apparatus, and the number of steps can be reduced.

  FIG. 10 is a plan view showing another configuration of the laser marking apparatus with a wafer rearrangement function. A laser marking device 4a with a wafer rearrangement function shown in FIG. 10 replaces the standby wafer cassette 9 of the laser marking device 4 with a wafer rearrangement function shown in FIG. 7 and an unloading wafer cassette stage 11 and a wafer cassette. A (second wafer cassette) 3 is provided. The loading wafer cassette stage 10 is a place where a wafer cassette (first wafer cassette) 2 containing a wafer to be started is placed. The unloading wafer cassette stage 11 is a place where a wafer cassette 3 into which a completed wafer is placed is placed. The number of loading wafer cassette stages 10 and the number of unloading wafer cassette stages 11 are one each in FIG. 10, but the present invention is not limited to this, and a plurality of them may be provided. If there are a plurality of wafer cassette stages, a plurality of wafer cassettes can be processed simultaneously.

  FIG. 11 is a flowchart showing an operation flow of the laser marking device 4a with a wafer rearrangement function of FIG. With reference to FIG. 11, an example of a method for manufacturing a semiconductor integrated circuit device according to the present embodiment will be described using a laser marking device 4a with a wafer rearrangement function.

  First, the operator sets the wafer cassette 2 containing the wafer before the start of loading on the loading wafer cassette stage 10 and the unloading empty wafer cassette 3 on the unloading wafer cassette stage 11 (step S300).

  When the operator gives an instruction to start construction, the transfer arm 1 removes one wafer from the wafer cassette 2 on the wafer cassette stage 10 and loads the wafer onto the image reading recognition unit 5 (step S301).

  The image reading and recognition unit 5 recognizes the lot number and wafer number printed on the wafer surface. Also, alignment of the orientation flat (notch) is executed (step S302).

  The laser marking device 4a with a wafer rearrangement function makes an inquiry to the host 7 using the image-recognized lot number as a key and calls a recipe corresponding to the lot number. When the inquiry cannot be made, or when the laser marking device 4a with wafer rearrangement function is in the manual mode, the operator inputs a recipe (step S303).

  The wafer is moved from the image reading recognition unit 5 to the laser mark unit 8 by the transfer arm 1 (step S304).

  The laser mark unit 8 performs marking on the back surface of the wafer by a recipe instruction (step S305).

  While marking on the back surface of the wafer in step S305, the waiting time is used to transfer another wafer in the next slot in the wafer cassette 2 from the wafer cassette 2 to the image reading recognition unit by the transfer arm 1. 5 is loaded (step S306).

  When the marking in step S305 is completed, the marking-completed wafer is moved from the laser mark unit 8 to the wafer cassette 3 on the unloading wafer cassette stage 11 by the transfer arm 1, and is the same as the wafer number read by image recognition. The slot is unloaded (step S307).

  In step S308, it is confirmed whether or not all the wafers in the wafer cassette 2 have been started. If all the wafers have not been started (No), steps S302 to S308 are repeated. If all wafers have been processed, the process is finished.

  Therefore, according to the semiconductor integrated circuit device manufacturing method of the present embodiment, all the wafers in wafer cassette 2 on loading wafer cassette stage 10 are transferred to wafer cassette 3 on unloading wafer cassette stage 11. At this time, since the wafers are rearranged in the order of the wafer numbers, the wafers can be rearranged by the same apparatus, and one process can be reduced.

  FIG. 12 is a plan view showing another configuration of the laser marking apparatus with a wafer rearrangement function. The laser marking device 4b with a wafer rearrangement function shown in FIG. 12 is obtained by eliminating the standby wafer cassette 9 of the laser marking device 4 with a wafer rearrangement function shown in FIG. The number of wafer cassette stages 10 is one in FIG. 12, but the present invention is not limited to this, and a plurality of wafer cassette stages 10 may be provided. If there are a plurality of wafer cassette stages, a plurality of wafer cassettes can be processed simultaneously.

  FIG. 13 is a flowchart showing an operation flow of the laser marking device 4b with the wafer rearrangement function of FIG. With reference to FIG. 13, an example of a method for manufacturing a semiconductor integrated circuit device according to the present embodiment will be described using a laser marking device 4b with a wafer rearrangement function.

  First, the operator sets the wafer cassette 2 containing a wafer on the wafer cassette stage 10 of the laser marking device 4b with a wafer rearrangement function.

  When the operator gives an instruction to start construction, the transfer arm 1 extracts one wafer from the wafer cassette 2 on the wafer cassette stage 10 and loads the wafer onto the image reading recognition unit 5 (step S400).

  The image reading and recognition unit 5 recognizes the lot number and wafer number printed on the wafer surface. Also, alignment of the orientation flat (notch) is executed (step S401).

  The laser marking device 4b with a wafer rearrangement function makes an inquiry to the host 7 using the image-recognized lot number as a key and calls a recipe corresponding to the lot number. When the inquiry cannot be made, or when the laser marking device 4b with wafer rearrangement function is in the manual mode, the operator inputs a recipe (step S402).

  The wafer is moved from the image reading recognition unit 5 to the laser mark unit 8 by the transfer arm 1 (step S403).

  The laser mark unit 8 performs marking on the back surface of the wafer by a recipe instruction (step S404).

  While marking is performed on the back surface of the wafer in step S404, when the waiting time is used, the wafer number of the wafer being marked (wafer number read by image recognition) and the slot number of the load source (wafer cassette 2) are the same. In the wafer cassette 2, the next wafer to be processed (other wafers in the next slot) is extracted from the wafer cassette 2 in order and loaded onto the image reading recognition unit 5 by the transfer arm 1. If the wafer number of the wafer being marked is different from the slot number of the load source, the wafer in the same slot number as the wafer number of the wafer being marked is extracted from the wafer cassette 2 and loaded into the image reading / recognition unit 5 by the transfer arm ( Step S405).

  When the marking in step S404 is completed, the marking-completed wafer is moved from the laser mark unit 8 to the wafer cassette 2 by the transfer arm 1 and unloaded to the same wafer cassette slot as the wafer number read by image recognition (step S404). Step S406).

  In step S407, it is checked whether or not all the wafers in the wafer cassette 2 have been started. If all the wafers have not been started (No), steps S400 to S407 are repeated. If all the wafers have been started (Yes), the start of the process is finished as it is.

  Therefore, according to the method of manufacturing a semiconductor integrated circuit device according to the present embodiment, if another wafer exists in the same slot as the wafer number of the wafer being marked, the wafer is extracted as the next process wafer. By leaving the slot open, the wafer after marking can be unloaded in the same slot as the wafer number, so the wafer can be rearranged with the same equipment, and one process can be reduced. Become.

  FIG. 14 is a flowchart showing another operation flow of the laser marking device 4b with the wafer rearrangement function of FIG. Referring to FIG. 14, another example of the method for manufacturing the semiconductor integrated circuit device according to the present embodiment will be described using a laser marking device 4b with a wafer rearrangement function.

  In FIG. 14, steps S500 to S504 are the same as steps S400 to S404 of the embodiment shown in FIG.

  While marking is performed on the back surface of the wafer in step S504, the next processing wafer (other wafers in the next slot) in the wafer cassette 2 is transferred to the wafer cassette 2 by the transfer arm 1 using the waiting time. To the image reading recognition unit 5 (step S505).

  If there is a wafer that has been started and the slot number is different from the wafer number, and there is no wafer in the slot with the same number as the wafer number, the processed wafer is taken out by the transfer arm 1, The slot number is the same as the wafer number (step S506).

  After completion of the marking in step S504, unloading is performed from the laser mark unit 8 to the same wafer cassette slot as the wafer number in the wafer cassette 2 by the transfer arm 1. If there is already a wafer in the same wafer cassette slot as the wafer number, unloading is performed in the empty slot of the load source (step S507).

  In step S508, it is confirmed whether or not all the wafers in the wafer cassette 2 have been started. If all the wafers have not been started (No), steps S501 to S508 are repeated. If all the wafers have been started (Yes), the start of the process is finished as it is.

  Therefore, according to the manufacturing method of the semiconductor integrated circuit device of the present embodiment, the wafers can be rearranged by rearranging the completed wafers in the wafer cassette 2 using the waiting time during marking. This is possible with the same apparatus, and one process can be reduced.

  The time required for laser marking is about 2 minutes per wafer, and the time required for wafer loading and unloading is about 70 seconds including alignment of the orientation flat (notch). Since the second and subsequent wafers can be transferred while performing the laser marking, the substantial transfer time is shortened. Therefore, other wafers can be rearranged using the standby time during laser marking. During wafer processing, one wafer is placed on the laser mark unit 8 and one wafer is placed on the image reading / recognition unit 5, so that two wafers are extracted from the wafer cassette 2 on the wafer cassette stage 10. Will be.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the LCD driver has been described as the semiconductor integrated circuit device. However, the present invention is not limited to this, and the present invention can also be applied to other semiconductor integrated circuit devices.

  Moreover, in the said embodiment, although the laser marking apparatus was demonstrated as a marking apparatus, it is not limited to this, It can apply also to the other marking apparatus which uses ink etc.

  As described above, the invention disclosed in the present application can be applied to a production line of a semiconductor integrated circuit device.

It is a process flow figure showing a manufacturing process in a manufacturing method of a semiconductor integrated circuit device which is one embodiment of the present invention. It is a figure which shows the processing base of each process in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is sectional drawing which shows the example of mounting of the semiconductor integrated circuit device manufactured by the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a figure which shows the back surface of the LSI chip | tip laser-marked by the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a figure which shows the surface of the wafer processed in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a block diagram which shows the structure of the laser marking apparatus with a wafer rearrangement function in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a top view which shows the structure of the laser marking apparatus with a wafer rearrangement function in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a flowchart which shows the operation | movement flow of the laser marking apparatus with a wafer rearrangement function of FIG. It is a flowchart which shows the other operation | movement flow of the laser marking apparatus with a wafer rearrangement function of FIG. It is a top view which shows the other structure of the laser marking apparatus with a wafer rearrangement function in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a flowchart which shows the operation | movement flow of the laser marking apparatus with a wafer rearrangement function of FIG. It is a top view which shows the other structure of the laser marking apparatus with a wafer rearrangement function in the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a flowchart which shows the operation | movement flow of the laser marking apparatus with a wafer rearrangement function of FIG. It is a flowchart which shows the other operation | movement flow of the laser marking apparatus with a wafer rearrangement function of FIG. It is a figure which shows an example of the process before and behind the laser marking process examined as a premise of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transfer arm 1a Semiconductor wafer transfer part 2 Wafer cassette (1st wafer cassette)
3 Wafer cassette (second wafer cassette)
4, 4a, 4b Laser marking device with wafer rearrangement function 5 Image reading recognition unit 6 Control unit 7 Host 8 Laser mark unit 9 Standby wafer cassette (second wafer cassette)
10, 11 Wafer cassette stage 12 Pre-processing section a
13 Pre-processing department b
14 Pre-processing department c
15 Previous process department d
16 Accepting department a
17 Bump category a
18 Bump category b
19 Bump category c
20 Bump category d
21 Bump category e
22 Accepting department b
23P inspection department a
24P inspection department b
25P inspection department c
26P inspection department d
27P inspection department e
28 P Inspection Department f
29 BG category a
30 BG category b
31 Accepting department c
32 Accepting department d
33 Post-processing department a
34 Post-process department b
35 Post-processing department c
36 Post-processing department d
37 Shipping Inspection Department a
38 Shipping Inspection Department b
39 LSI chip 40 Bump 41 Lead 42 Substrate 43 Tape 44 Resin 45 Wafer

Claims (7)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of performing probe inspection on each wafer after the wafer processing step;
(B) grinding the back surface of the wafer;
(C) using a marking device, reading a lot number and a wafer number printed on the wafer surface, and marking the lot number and the wafer number on the back surface of the wafer;
(D) A step of rearranging the wafers in a wafer cassette in the order of the probe inspection using the marking device based on the wafer number read in the step (c). The method for manufacturing a semiconductor integrated circuit device according to claim 1 further includes the following steps:
(E) A step of dividing the wafer into chips. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Said step (d) comprises the following substeps:
(D1) A step of taking out the first wafer from the first slot in the first wafer cassette for reading the number in the step (c);
(D2) After marking the first wafer in the step (c), if there is a second wafer in the second slot in the first wafer cassette corresponding to the wafer number of the first wafer, Temporarily storing the first wafer in a two-wafer cassette;
(D3) After marking in the step (c) for all the wafers in the first wafer cassette, the first wafer temporarily stored in the second wafer cassette is transferred to the first wafer cassette. Storing in the second slot in the wafer cassette; The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Said step (d) comprises the following substeps:
(D1) A step of taking out the first wafer from the first slot in the first wafer cassette for reading the number in the step (c);
(D2) After marking the first wafer in the step (c), if there is a second wafer in the second slot in the first wafer cassette corresponding to the wafer number of the first wafer, Temporarily storing the first wafer in a two-wafer cassette;
(D3) The first wafer is temporarily stored in the second wafer cassette when the second wafer is taken out from the second slot in the first wafer cassette and the second slot is empty. Is stored in the second slot in the first wafer cassette. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Said step (d) comprises the following substeps:
(D1) A step of taking out the first wafer from the first slot in the first wafer cassette for reading the number in the step (c);
(D2) A step of storing the first wafer in a second slot in a second wafer cassette corresponding to the wafer number of the first wafer after marking in the step (c) for the first wafer. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Said step (d) comprises the following substeps:
(D1) taking out the first wafer from the first slot in the wafer cassette for reading the number in the step (c);
(D2) a step of taking out the second wafer from the second slot in the wafer cassette corresponding to the wafer number of the first wafer as a wafer to be started next;
(D3) A step of storing the first wafer in the second slot in the wafer cassette after marking the step (c) on the first wafer. The method of manufacturing a semiconductor integrated circuit device according to claim 1,
Said step (d) comprises the following substeps:
(D1) taking out the first wafer from the first slot in the wafer cassette for reading the number in the step (c);
(D2) While marking the first wafer in the step (c), a third corresponding to the wafer number of the second wafer that has been started and stored in the second slot in the wafer cassette. If the slot is vacant, the step of removing the second wafer from the second slot and storing it in the third slot;
(D3) After marking the first wafer in the step (c), if the fourth slot in the wafer cassette corresponding to the first wafer is empty, the first wafer is moved to the fourth slot. And storing the first wafer in the first slot when the fourth slot is not empty.

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