JP2005251993A - Chip-type electronic component - Google Patents

Chip-type electronic component Download PDF

Info

Publication number
JP2005251993A
JP2005251993A JP2004060602A JP2004060602A JP2005251993A JP 2005251993 A JP2005251993 A JP 2005251993A JP 2004060602 A JP2004060602 A JP 2004060602A JP 2004060602 A JP2004060602 A JP 2004060602A JP 2005251993 A JP2005251993 A JP 2005251993A
Authority
JP
Japan
Prior art keywords
electrodes
chip
internal electrodes
electronic component
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004060602A
Other languages
Japanese (ja)
Other versions
JP4111340B2 (en
Inventor
Goro Takeuchi
吾郎 武内
Hiroyuki Sato
弘幸 佐藤
Keisuke Akagi
啓介 赤城
Original Assignee
Tdk Corp
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp, Tdk株式会社 filed Critical Tdk Corp
Priority to JP2004060602A priority Critical patent/JP4111340B2/en
Publication of JP2005251993A publication Critical patent/JP2005251993A/en
Application granted granted Critical
Publication of JP4111340B2 publication Critical patent/JP4111340B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide the chip-type electronic component of the structure that extending of plating in the electroplating of terminal electrode can be prevented, without forming an insulator layer on the surface of a single material formed of a ceramics semiconductor. <P>SOLUTION: The surface roughness Ra of the single material 1 and the radius R of an inscribed circle of the angled portion 6, between the side surface of the single material and upper and lower surfaces satisfy the relations 0.1 μm ≤Ra≤0.5 μm and R≥0.03×W (where W is the width of single material 1) or of 0.1 μm ≤Ra≤0.6 μm and R≥0.05×W or 0.1 μm ≤Ra≤2.0 μm and R ≥ 0.10×W. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、NTCサーミスタ、PTCサーミスタあるいはバリスタのように、素体が半導体セラミックスからなるチップ型電子部品に関する。   The present invention relates to a chip-type electronic component whose element body is made of semiconductor ceramics, such as an NTC thermistor, a PTC thermistor, or a varistor.

サーミスタやバリスタは、シート積層法や、チップ状に切り出したセラミック素体の両端に端子電極を付けることによって構成される。前記シート積層法による場合は、セラミックグリーンシート上に電極ペーストを印刷、乾燥し、これを上下の保護用のグリーンシートと共に積層した後、切断してチップとし、これを焼成し、チップの両端に端子電極を付けて製造される。バリスタも同様の方法によって製造される。   The thermistor and varistor are configured by a sheet lamination method or by attaching terminal electrodes to both ends of a ceramic body cut out in a chip shape. In the case of the sheet laminating method, the electrode paste is printed on the ceramic green sheet, dried, laminated with the upper and lower protective green sheets, then cut into chips, and this is fired at both ends of the chip. Manufactured with terminal electrodes. Varistors are also manufactured by a similar method.

また、前記サーミスタやバリスタは、プリント基板に表面実装するために、端子電極は、銀ペースト等を焼付けした焼付電極上に半田食われを防止するためのニッケル等を電気めっきにより形成し、その上に半田付けを容易にするための錫あるいは錫−鉛等を電気めっきにより形成する。   The thermistor and varistor are surface-mounted on a printed circuit board, and the terminal electrode is formed by electroplating nickel or the like for preventing solder erosion on a baked electrode baked with silver paste or the like. Then, tin or tin-lead or the like for easy soldering is formed by electroplating.

このようなニッケルや錫等の電気めっきはバレルめっきにより行なわれるが、直方体状に形成されたセラミックス素体が半導体でなるため、図4に示すように、素体20の両端に設けられた端子電極21、22より、相手側端子電極22、21に向けて、素体側面と上下面との間の角部24に沿って、電気めっきによる金属膜が形成されるめっき伸び23が生じる。   Such electroplating of nickel, tin, or the like is performed by barrel plating, but since the ceramic body formed in a rectangular parallelepiped shape is a semiconductor, terminals provided at both ends of the body 20 as shown in FIG. From the electrodes 21, 22 toward the mating terminal electrodes 22, 21, a plating elongation 23 is formed along which a metal film is formed by electroplating along the corner portion 24 between the element side surface and the upper and lower surfaces.

このようなめっき伸び23はつぎのような理由により起こる。すなわち、バレルめっきは、めっき液により外部と電気的に導通可能な回転円筒体内に複数の負極棒を設けると共に、導電性を有する球体でなるメディアを、焼付電極を設けた多数のチップと共に前記回転円筒体内に入れ、この回転円筒体をめっき液に浸漬し、回転円筒体の外部にめっき液に浸漬して設けた正極と前記負極棒との間に通電することにより、前記チップの焼付電極上に負極棒より直接に通電するか、あるいはメディアを介して通電させて電気めっきを行なうものである。   Such plating elongation 23 occurs for the following reason. That is, in barrel plating, a plurality of negative poles are provided in a rotating cylinder that can be electrically connected to the outside by a plating solution, and a medium composed of conductive spheres is rotated with a plurality of chips provided with baking electrodes. The chip is placed in a cylindrical body, immersed in a plating solution, and energized between a positive electrode provided outside the rotating cylinder and immersed in a plating solution, and the negative electrode rod. The electroplating is carried out by applying current directly to the negative electrode from the negative electrode or through a medium.

このようなバレルめっきを行なう場合、回転円筒体の回転に伴い、流動状態にあるチップの角部24は、チップの上下面や側面に比較して正極に近くなるタイミングが多くなり(すなわち電界集中が起こり)、かつ、セラミックス素体1が半導体であるため、微小電流が流れるため、前記角部24に沿って端子電極21、22側からめっき伸び23が生じるのである。このめっき伸び23が生じると、外観が不良となり、極端な場合には端子電極21、22間が短絡するショート不良を生じる。   When such barrel plating is performed, as the rotating cylinder rotates, the corner 24 of the chip in the fluidized state is more likely to be closer to the positive electrode than the upper and lower surfaces and side surfaces of the chip (that is, electric field concentration). In addition, since the ceramic body 1 is a semiconductor, a minute current flows, so that the plating elongation 23 occurs from the terminal electrodes 21 and 22 side along the corner portion 24. When this plating elongation 23 occurs, the appearance becomes poor, and in an extreme case, a short circuit failure occurs in which the terminal electrodes 21 and 22 are short-circuited.

前記めっき伸び23を防止するため、従来は、セラミックス素体20の表面をガラス等の絶縁体層により覆い、これにより電気めっき時に素体20の表面が電流が流れることを防止している(例えば特許文献1参照。)。   In order to prevent the plating elongation 23, conventionally, the surface of the ceramic body 20 is covered with an insulating layer such as glass, thereby preventing current from flowing through the surface of the body 20 during electroplating (for example, (See Patent Document 1).

特開2003−151805公報(図1、段落0012)JP2003-151805 (FIG. 1, paragraph 0012)

前述のように、従来はセラミックス素体を絶縁体層によって覆うことによりめっき伸び23を防止しているが、しかし絶縁体層の形成の工程を付加する必要があるために工数が増え、コストアップにつながる等の問題点がある。   As mentioned above, the plating elongation 23 is conventionally prevented by covering the ceramic body with an insulator layer. However, since it is necessary to add a process of forming the insulator layer, man-hours increase and cost increases. There is a problem that leads to.

本発明は、上記問題点に鑑み、セラミックス半導体でなる素体表面に絶縁体層を形成することなく、電気めっきの際の角部に沿うめっき伸びを防止することができる構造のチップ型電子部品を提供することを目的とする。   In view of the above problems, the present invention provides a chip-type electronic component having a structure capable of preventing plating elongation along corners during electroplating without forming an insulator layer on the surface of a ceramic semiconductor body. The purpose is to provide.

(1)本発明のチップ型電子部品は、直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦0.5μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.03×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とする。
(1) The chip-type electronic component of the present invention has a plurality of internal electrodes opposed to each other inside a semiconductor ceramic body having a rectangular parallelepiped shape, and one or more internal electrodes are drawn out to one end of the element body. The remaining internal electrodes are drawn to the other end of the element body, and terminal electrodes connected to the internal electrodes drawn to the respective end parts at both ends of the element body, A chip-type electronic component having a baked electrode baked on and a plated electrode formed by electroplating on the baked electrode,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 0.5 μm,
When the width of the element body is W and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.03 × W,
The element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.

(2)また、本発明のチップ型電子部品は、直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦0.6μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.05×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とする。
(2) Further, the chip-type electronic component of the present invention has a plurality of internal electrodes opposed to each other inside a semiconductor ceramic body having a rectangular parallelepiped shape, and one or more internal electrodes are arranged at one end of the element body. The remaining internal electrodes are drawn out to the other end of the element body, and have terminal electrodes connected to the internal electrodes drawn out at the respective ends at both ends of the element body. A chip-type electronic component having a baked electrode baked on an element body and a plated electrode formed by electroplating on the baked electrode,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 0.6 μm,
When the width of the element body is W, and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.05 × W,
The element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.

(3)また、本発明のチップ型電子部品は、直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦2.0μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.10×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とする。
(3) Moreover, the chip-type electronic component of the present invention has a plurality of internal electrodes facing each other inside a semiconductor ceramic body having a rectangular parallelepiped shape, and one or more internal electrodes are arranged at one end of the element body. The remaining internal electrodes are drawn out to the other end of the element body, and have terminal electrodes connected to the internal electrodes drawn out at the respective ends at both ends of the element body. A chip-type electronic component having a baked electrode baked on an element body and a plated electrode formed by electroplating on the baked electrode,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 2.0 μm,
When the width of the element body is W and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.10 × W,
The element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.

本発明においては、表面粗さRaおよび角部の内接円の半径Rを前記のように設定することにより、電界集中が良好に抑制され、前記めっき伸びを防止することができる。   In the present invention, by setting the surface roughness Ra and the radius R of the inscribed circle at the corners as described above, the electric field concentration can be satisfactorily suppressed and the plating elongation can be prevented.

図1は本発明によるチップ型電子部品の一実施の形態を示す斜視図、図2はその縦断面図、図3は図2のE−E断面図である。1は負の温度抵抗特性(NTC特性)を有する直方体状をなすセラミックス素体であり、この素体1は、例えばMn、Ni、Fe、Co、Cu、Zr等の化合物によって構成される半導体である。2、3は素体1に内蔵した内部電極であり、銀、銀-パラジウムあるいはパラジウム等からなるものである。   1 is a perspective view showing an embodiment of a chip-type electronic component according to the present invention, FIG. 2 is a longitudinal sectional view thereof, and FIG. 3 is a sectional view taken along line EE of FIG. Reference numeral 1 denotes a ceramic body having a rectangular parallelepiped shape having negative temperature resistance characteristics (NTC characteristics). This element body 1 is a semiconductor composed of a compound such as Mn, Ni, Fe, Co, Cu, or Zr. is there. Reference numerals 2 and 3 denote internal electrodes built in the element body 1, which are made of silver, silver-palladium or palladium.

4、5はそれぞれ素体1の両端に引き出された前記内部電極2、3に接続されるように設けた端子電極である。6は素体1の側面と上下面との間の角部である。なお、本発明において、上下面とは内部電極2、3と平行面をなす面を意味し、側面とは内部電極2、3に垂直な面を意味するもので、図示の上面や側面がプリント基板への実装面であってもよい。この実施の形態では一方の内部電極2を2枚、他方の内部電極3を1枚としているが、それぞれ1枚ずつあるいは複数枚ずつ設けてもよい。   Reference numerals 4 and 5 denote terminal electrodes provided so as to be connected to the internal electrodes 2 and 3 drawn to both ends of the element body 1, respectively. Reference numeral 6 denotes a corner between the side surface of the element body 1 and the upper and lower surfaces. In the present invention, the upper and lower surfaces mean a surface parallel to the internal electrodes 2 and 3, and the side surface means a surface perpendicular to the internal electrodes 2 and 3. It may be a mounting surface on a substrate. In this embodiment, one internal electrode 2 is two and the other internal electrode 3 is one, but one or a plurality of each may be provided.

前記端子電極4、5は、焼付電極7と、その上に形成され、焼付電極7が半田と合金を作って侵食される(食われる)ことを防止する第1のめっき層8と、半田付け用の第2のめっき層9とからなる。前記素体1は、端子電極4、5で覆われた部分以外の部分は外部に露出している。   The terminal electrodes 4, 5 are formed on the baked electrode 7, a first plating layer 8 that prevents the baked electrode 7 from being eroded (corroded) by forming an alloy with the solder, and soldering. And a second plating layer 9 for use. In the element body 1, portions other than the portions covered with the terminal electrodes 4 and 5 are exposed to the outside.

前記素体1は、例えばシート積層法により製造される。すなわち前記素体を構成する元素の割合が所定の比になるように、前記元素の化合物を所定の割合で混合し、湿式混合等により均一に混合する。その後乾燥させて解砕した後、仮焼成し、仮焼成粉をボールミルで湿式粉砕する。その粉砕したものを乾燥して粉砕粉に有機バインダ、有機溶剤、有機可塑剤等を加えてボールミルにより混合、粉砕してスラリー化する。このスラリーをドクターブレード法やスクリーン印刷法等の手段によってシート化し、そのシートを乾燥させてセラミックグリーンシートを得る。   The element body 1 is manufactured by, for example, a sheet lamination method. That is, the compound of the element is mixed at a predetermined ratio so that the ratio of the elements constituting the element body becomes a predetermined ratio, and is uniformly mixed by wet mixing or the like. Thereafter, the powder is dried and crushed, and then calcined, and the calcined powder is wet pulverized with a ball mill. The pulverized product is dried, an organic binder, an organic solvent, an organic plasticizer, and the like are added to the pulverized powder, mixed and pulverized by a ball mill to form a slurry. This slurry is formed into a sheet by means such as a doctor blade method or a screen printing method, and the sheet is dried to obtain a ceramic green sheet.

次に内部電極2、3を構成する電極ペーストを、印刷法等の手段によってグリーンシートの上に所定のパターンで塗布することにより形成する。また、素体1の上下面を形成するための電極を持たないグリーンシートを準備する。これらのグリーンシートを重ね合わせ、圧力を加えて圧着し、乾燥工程等の必要な工程を経た後、内部電極2、3の各一端が端面から露出するように切断し、グリーンチップを得る。そしてこのグリーンチップを加熱することにより脱バインダ処理を行ない、その後焼成して焼成体を得る。   Next, an electrode paste constituting the internal electrodes 2 and 3 is formed by applying a predetermined pattern on the green sheet by means such as a printing method. Further, a green sheet having no electrodes for forming the upper and lower surfaces of the element body 1 is prepared. These green sheets are superposed, pressure is applied and pressure-bonded, and after passing through necessary steps such as a drying step, the internal electrodes 2 and 3 are cut so that one end of each of the internal electrodes 2 and 3 is exposed from the end face, thereby obtaining a green chip. The green chip is heated to remove the binder, and then fired to obtain a fired body.

このようにして得た焼成体でなる端子電極4、5を付ける前のチップを、遠心バレルに入れ、素体1の側面と上下面との間の角部6に丸みを持たせるための比較的粒径の大きな(粒径が0.1mm〜1.0mm)のセラミックボール等からなる大径研磨剤と、素体1の表面を平滑化するための比較液粒径の小さな(粒径が0.1〜2.0μm)の砥石粉末のような小径研磨剤と水とを入れ、バレルを回転させて面取りと研磨を行なう。   Comparison for placing the chip before attaching the terminal electrodes 4 and 5 made of the fired body in this way into a centrifuge barrel and rounding the corner 6 between the side surface and the upper and lower surfaces of the element body 1 A large-diameter abrasive comprising ceramic balls having a large target particle size (particle size of 0.1 mm to 1.0 mm) and a comparative liquid particle size for smoothing the surface of the element body 1 (particle size is A small-diameter abrasive such as 0.1 to 2.0 [mu] m grinding stone powder and water are put in, and the barrel is rotated to perform chamfering and polishing.

ここで、バレルによる面取り、研磨時間の調整、大小の研磨剤の径および量を調整して、素体1の表面粗さRaが0.1μm≦Ra≦0.5μmとなるようにすると同時に、前記角部6の内接円の半径Rが素体1の幅W(図1参照)に対し、R≧0.03×Wとなるように研磨する。また、別の態様として、0.1μm≦Ra≦0.6μmでかつR≧0.05×Wかあるいは0.1μm≦Ra≦2.0μmでかつR≧0.10×Wとする。   Here, the chamfering by the barrel, the adjustment of the polishing time, the diameter and the amount of the large and small abrasives are adjusted so that the surface roughness Ra of the element body 1 is 0.1 μm ≦ Ra ≦ 0.5 μm, Polishing is performed so that the radius R of the inscribed circle of the corner 6 is R ≧ 0.03 × W with respect to the width W of the element body 1 (see FIG. 1). As another aspect, 0.1 μm ≦ Ra ≦ 0.6 μm and R ≧ 0.05 × W, or 0.1 μm ≦ Ra ≦ 2.0 μm and R ≧ 0.10 × W.

このようにして得られた個々の素体の両端部に対して、銀等の貴金属を主成分とする電極ペーストを塗布して乾燥した後、焼付けして焼付電極7を形成する。そして個々の素子に対し、焼付電極7上に、半田食われ防止用のニッケルからなる第1のめっき層8を電気めっきにより形成し、その上に半田付け用の錫または錫−鉛等からなる第2のめっき層9を電気めっきにより形成する。   An electrode paste mainly composed of a noble metal such as silver is applied to both end portions of the individual element bodies thus obtained, dried, and then baked to form a baked electrode 7. Then, for each element, a first plating layer 8 made of nickel for preventing solder erosion is formed on the baking electrode 7 by electroplating, and it is made of soldering tin or tin-lead or the like thereon. The second plating layer 9 is formed by electroplating.

なお第1のめっき層8は0.5μm以上の厚みに形成することが半田食われを防止する意味で好ましく、また、5.0μm以下の厚みに形成することが、不必要に厚く形成することを防ぐ意味で好ましい。また、第2のめっき層9は半田付け性を確保する意味において2.0μm以上の厚みに形成することが好ましく、また、10.0μm以下の厚みに形成することが、不必要に厚く形成することを防ぐ意味で好ましい。   The first plating layer 8 is preferably formed to a thickness of 0.5 μm or more in order to prevent solder erosion, and it is necessary to form the first plating layer 8 to a thickness of 5.0 μm or less unnecessarily thickly. It is preferable in the meaning which prevents. The second plating layer 9 is preferably formed to a thickness of 2.0 μm or more in order to ensure solderability, and it is formed to be unnecessarily thick to a thickness of 10.0 μm or less. It is preferable in the meaning which prevents this.

酸化マンガン(Mn3O4):52.85mol%、酸化コバルト(Co3O4):31.04mol%、酸化鉄(Fe2O3):13.42mol%、酸化ジルコニウム(ZrO2):2.69mol%を混合し、湿式混合によって均一に混合した。その後乾燥させて解砕した後、1000℃で2時間仮焼成し、仮焼成粉をボールミルで16時間湿式粉砕した。その後乾燥させて解砕し、解砕した粉砕粉に有機バインダ、有機溶剤、有機可塑剤を加えてボールミルで20時間混合、粉砕してスラリー化した。 Manganese oxide (Mn 3 O 4 ): 52.85 mol%, cobalt oxide (Co 3 O 4 ): 31.04 mol%, iron oxide (Fe 2 O 3 ): 13.42 mol%, zirconium oxide (ZrO 2 ): 2 69 mol% was mixed and mixed uniformly by wet mixing. After drying and pulverizing, the calcined powder was calcined at 1000 ° C. for 2 hours, and the calcined powder was wet pulverized with a ball mill for 16 hours. After drying and pulverizing, an organic binder, an organic solvent, and an organic plasticizer were added to the pulverized pulverized powder, and the mixture was pulverized for 20 hours by a ball mill to form a slurry.

このスラリーをドクターブレード法によってシート化し、乾燥してグリーンシートを得た。このグリーンシートに対し、パラジウムを主体とした電極ペーストを印刷法により塗布、乾燥して内部電極2、3を形成した。   This slurry was formed into a sheet by a doctor blade method and dried to obtain a green sheet. An electrode paste mainly composed of palladium was applied to the green sheet by a printing method and dried to form internal electrodes 2 and 3.

このように内部電極2、3を形成したグリーンシートと、内部電極を形成していない上下面形成用のグリーンシートとを重ね合わせて圧着し、乾燥等の必要な工程を経て所定の寸法に切断し、グリーン状態の素体(チップ)1を得た。この場合、最終素子のサイズとしてはサイズA=(長さ1.6mm)×(幅0.8mm)×(高さ0.8mm)、同様にサイズB=1.0mm×0.5mm×0.5mm、サイズC=0.6mm×0.3mm×0.3mm、サイズD=0.4mm×0.2mm×0.2mmの4種のサイズのものを試作した。   In this way, the green sheet on which the internal electrodes 2 and 3 are formed and the green sheet for forming the upper and lower surfaces on which the internal electrode is not formed are overlapped and pressure-bonded, and cut into a predetermined size through a necessary process such as drying. As a result, a green body 1 (chip) 1 was obtained. In this case, the size of the final element is size A = (length 1.6 mm) × (width 0.8 mm) × (height 0.8 mm), and similarly size B = 1.0 mm × 0.5 mm × 0. Four types of sizes of 5 mm, size C = 0.6 mm × 0.3 mm × 0.3 mm, and size D = 0.4 mm × 0.2 mm × 0.2 mm were made as prototypes.

この素体1を400℃で2時間加熱して脱バインダを行ない、その後、1250℃で2時間、大気中で焼成して焼成体を得た。   The element body 1 was heated at 400 ° C. for 2 hours to remove the binder, and then fired at 1250 ° C. for 2 hours in the air to obtain a fired body.

このようにして得た焼結体チップを遠心バレルに入れ、直径が0.1mm〜1.0mmのジルコニアボールからなる面取り用大径研磨剤と、直径が0.1μm〜2.0μmのアルミナからなる砥石粉末としての小径研磨剤とを水に入れ、これらを回転させて研磨し、面取りした。   The sintered body chip thus obtained is placed in a centrifuge barrel, and is made of a chamfering large-diameter abrasive made of zirconia balls having a diameter of 0.1 mm to 1.0 mm, and alumina having a diameter of 0.1 μm to 2.0 μm. A small-diameter abrasive as a whetstone powder was put in water, and these were rotated and polished to be chamfered.

このとき、バレル時間の調整および大径研磨剤であるジルコニアボール、アルミナでなる小径研磨剤のそれぞれの径を前記範囲で調整すると共に、研磨前の表面粗さRaが4.0μmであった素体1に対し、これらの大径研磨剤、小径研磨剤の混合比および溶剤(水)に対する研磨剤の含有率をそれぞれ調整して研磨することにより、表面粗さRaを0.05μm、0.1μm、0.3μm、0.5μm、0.6μm、1.0μm、2.0μmに変化させた。また、各表面粗さRaについて、角部6の内接円10の半径Rが幅Wの0%、3%、5%、10%、20%、30%となるようにした。   At this time, the barrel time was adjusted, and the diameters of the large-diameter zirconia balls and the small-diameter abrasive made of alumina were adjusted within the above ranges, and the surface roughness Ra before polishing was 4.0 μm. The body 1 is polished by adjusting the mixing ratio of these large-diameter abrasives, small-diameter abrasives and the content of the abrasive with respect to the solvent (water), respectively, so that the surface roughness Ra is 0.05 μm, 0.0. The thickness was changed to 1 μm, 0.3 μm, 0.5 μm, 0.6 μm, 1.0 μm, and 2.0 μm. For each surface roughness Ra, the radius R of the inscribed circle 10 at the corner 6 was set to 0%, 3%, 5%, 10%, 20%, and 30% of the width W.

この研磨に際し、比較的大きなサイズの素体の研磨の場合には、大径研磨剤の径を大きくし、小さい素体の研磨の場合には大径研磨剤、小径研磨剤の径を小さくした。また、表面粗さRaの値を小さく(平滑度を高く)し、前記角部6の内接円10の半径Rを小さくする場合には大径研磨剤の小径研磨剤に対する相対混合率α(重量%)=大径研磨剤/(大径研磨剤+小径研磨剤)を小さくした。また、表面粗さRaの値を大きく(平滑度を低下)し、前記角部6の内接円10の半径Rを大きくする場合には前記大径研磨剤の小径研磨剤に対する相対混合率(前記αの値)を大きくした。また、平滑度を高く(Raの値を小さく)、前記半径Rを大きくする場合には、研磨時間を長くした。   In this polishing, the diameter of the large-diameter abrasive is increased in the case of polishing a relatively large size element, and the diameter of the large-diameter and small-diameter abrasive is decreased in the case of polishing a small element. . Further, when the surface roughness Ra is decreased (smoothness is increased) and the radius R of the inscribed circle 10 of the corner portion 6 is decreased, the relative mixing ratio α ( (Weight%) = large diameter abrasive / (large diameter abrasive + small diameter abrasive) was made smaller. Further, when the value of the surface roughness Ra is increased (smoothness is lowered) and the radius R of the inscribed circle 10 of the corner 6 is increased, the relative mixing ratio of the large-diameter abrasive to the small-diameter abrasive ( The value of α was increased. Also, when the smoothness was high (Ra value was small) and the radius R was large, the polishing time was lengthened.

具体的には、素子のサイズに応じて下記の径の研磨剤を使用した。
サイズA:大径研磨剤の径0.3mm〜1.0mm
小径研磨剤の径0.1μm〜2.0μm
サイズB:大径研磨剤の径0.3mm〜0.8mm
小径研磨剤の径0.1μm〜1.0μm
サイズC:大径研磨剤の径0.1mm〜0.5mm
小径研磨剤の径0.1μm〜0.5μm
サイズD:大径研磨剤の径0.1mm〜0.5mm
小径研磨剤の径0.1μm〜0.5μm
Specifically, an abrasive having the following diameter was used according to the size of the element.
Size A: Large abrasive particle diameter of 0.3 mm to 1.0 mm
The diameter of the small-diameter abrasive is 0.1 μm to 2.0 μm
Size B: Large diameter abrasive 0.3 mm to 0.8 mm
The diameter of the small-diameter abrasive is 0.1 μm to 1.0 μm
Size C: Diameter of the large diameter abrasive 0.1 mm to 0.5 mm
Diameter of small diameter abrasive 0.1μm ~ 0.5μm
Size D: The diameter of the large-diameter abrasive is 0.1 mm to 0.5 mm
Diameter of small diameter abrasive 0.1μm ~ 0.5μm

また、例えばサイズAのものについて、表面粗さRa=0.1μm(後述の表2参照)とする場合、前記半径Rが0%、3%、5%、10%、20%、30%(素体幅Wに対する割合)を有するものを得るため、それぞれ下記の大小研磨剤の混合率αと水に対する研磨剤の含有率β(重量%)=研磨剤/(研磨剤+水)と研磨時間Tとした。
R=0%:α=5% β=15% T=60分
R=3%:α=30% β=15% T=180分
R=5%:α=50% β=15% T=180分
R=10%:α=80% β=15% T=180分
R=20%:α=80% β=15% T=240分
R=30%:α=80% β=15% T=480分
For example, when the surface roughness Ra is set to 0.1 μm (see Table 2 described later) for the size A, the radius R is 0%, 3%, 5%, 10%, 20%, 30% ( In order to obtain a material having a ratio to the element body width W), the mixing ratio α of the following large and small abrasives and the content ratio β (weight%) of the abrasive with respect to water = abrasive / (abrasive + water) and the polishing time, respectively. T.
R = 0%: α = 5% β = 15% T = 60 minutes R = 3%: α = 30% β = 15% T = 180 minutes R = 5%: α = 50% β = 15% T = 180 Minute R = 10%: α = 80% β = 15% T = 180 minutes R = 20%: α = 80% β = 15% T = 240 minutes R = 30%: α = 80% β = 15% T = 480 minutes

また、例えばサイズAのものについて、前記半径Rが3%で、表面粗さRaが0.05μm、0.1μm、0.3μm、0.5μm、0.6μm、1.0μm、2.0μm(後述の表1〜表7参照)のものを得るため、下記のような大小研磨剤混合率α、水に対する研磨剤含有率βのものを使用し、下記の時間研磨した。
Ra=0.05μm:α=10% β=25% T=480分
Ra=0.1μm:α=30% β=15% T=180分
Ra=0.3μm:α=30% β=15% T=180分
Ra=0.5μm:α=30% β=15% T=180分
Ra=0.6μm:α=30% β=15% T=180分
Ra=1.0μm:α=50% β=10% T=120分
Ra=2.0μm:α=50% β=5% T=120分
For example, for the size A, the radius R is 3%, and the surface roughness Ra is 0.05 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.6 μm, 1.0 μm, 2.0 μm ( In order to obtain the following (see Table 1 to Table 7), the following large and small abrasive mixing ratio α and abrasive content β with respect to water were used and polished for the following time.
Ra = 0.05 μm: α = 10% β = 25% T = 480 minutes Ra = 0.1 μm: α = 30% β = 15% T = 180 minutes Ra = 0.3 μm: α = 30% β = 15% T = 180 minutes Ra = 0.5 μm: α = 30% β = 15% T = 180 minutes Ra = 0.6 μm: α = 30% β = 15% T = 180 minutes Ra = 1.0 μm: α = 50% β = 10% T = 120 minutes Ra = 2.0 μm: α = 50% β = 5% T = 120 minutes

このように、大小研磨剤混合率α、水に対する研磨剤含有率β、時間研磨Tを調整することで所望の表面粗さRa、前記半径Rを有するサンプルを得た。   In this way, a sample having a desired surface roughness Ra and the radius R was obtained by adjusting the mixing ratio α of the large and small abrasives, the abrasive content β with respect to water, and the time polishing T.

そしてこれらのサンプルについて、めっき伸びを調べた。めっき伸びは、図4において、端子電極の素体長手方向の幅をb、めっき伸びaをしたとき、a>b×0.1の場合をめっき伸びが発生したものと判定し、それぞれ1万個中のサンプルに対して何%めっき伸びが発生したかを調べた。   And about these samples, plating elongation was investigated. In FIG. 4, when the width of the terminal electrode in the longitudinal direction of the terminal body is b and the plating elongation is a in FIG. 4, the case where a> b × 0.1 is determined as the occurrence of plating elongation. It was investigated how much plating elongation occurred with respect to the samples in the individual.

また、前記アルミナでなる小径研磨剤の無いものでバレル研磨した場合と、バレル研磨しない場合とについてもめっき伸びを調べた。これらの各サンプルについてのめっき伸びの有無を表1〜表8に示す。表1〜表8内の数値(%)はめっき伸びの発生率を示している。   Further, the plating elongation was examined for the case where barrel polishing was performed using the alumina without a small-diameter abrasive and for the case where barrel polishing was not performed. Tables 1 to 8 show the presence or absence of plating elongation for each of these samples. Numerical values (%) in Tables 1 to 8 indicate the rate of occurrence of plating elongation.

表8に示すように研磨しない素体1の表面粗さRaは4.0μmであった。表1に示すように、表面粗さRaが0.05μmの場合には平滑度が高すぎて、銀でなる電極ペーストを焼付けた際の密着性が悪く、ニッケルめっき中に端子電極が素体1から剥離し、正常なめっきができなかった。 As shown in Table 8, the surface roughness Ra of the element body 1 that was not polished was 4.0 μm. As shown in Table 1, when the surface roughness Ra is 0.05 μm, the smoothness is too high, and the adhesion when the electrode paste made of silver is baked is poor, and the terminal electrode is the base body during nickel plating. It peeled from 1 and normal plating was not able to be performed.

表2〜表4に示すように、0.1μm≦Ra≦0.5μmの場合、前記角部6の内接円10の半径Rが幅Wに対してR≧0.03×Wであればめっき伸びが発生しなかった。   As shown in Tables 2 to 4, when 0.1 μm ≦ Ra ≦ 0.5 μm, the radius R of the inscribed circle 10 of the corner 6 is R ≧ 0.03 × W with respect to the width W. No plating elongation occurred.

また、表2〜表5に示すように、0.1μm≦Ra≦0.6μmの場合、前記角部の内接円10の半径Rが幅Wに対してR≧0.05×Wであればめっき伸びが発生しなかった。   In addition, as shown in Tables 2 to 5, when 0.1 μm ≦ Ra ≦ 0.6 μm, the radius R of the inscribed circle 10 at the corner may be R ≧ 0.05 × W with respect to the width W. No plating elongation occurred.

また、表2〜表7に示すように、0.1μm≦Ra≦2.0μmの場合、前記角部6の内接円10の半径Rが幅Wに対してR≧0.10×Wであればめっき伸びが発生しなかった。   As shown in Tables 2 to 7, when 0.1 μm ≦ Ra ≦ 2.0 μm, the radius R of the inscribed circle 10 of the corner 6 is R ≧ 0.10 × W with respect to the width W. If present, plating elongation did not occur.

また、バレル研磨なしの場合と、砥石粉末がなく、大径研磨剤であるジルコニアボールだけで研磨した場合には、表8に示すように、いずれの半径Rの場合にもめっき伸びが発生した。これは大径研磨剤だけの場合には、表面粗さRaがかえって粗くなるためと考えられる。   In addition, in the case of no barrel polishing and in the case of polishing with only a zirconia ball that is a large-diameter abrasive without a grinding stone powder, as shown in Table 8, plating elongation occurred at any radius R. . This is presumably because the surface roughness Ra is rather rough when only the large-diameter abrasive is used.

このようなことから、表面粗さRaと角部の内接円の半径Rとの相乗効果によってめっき伸びが有効に防止できることが判明した。なお、前記半径Rについては、0.30×W以下である(より好ましくは0.20×W以下)ことが、チップを安定して収容具に収容することや研磨時間を短縮する意味で好ましい。   From this, it has been found that the plating elongation can be effectively prevented by the synergistic effect of the surface roughness Ra and the radius R of the inscribed circle at the corner. The radius R is preferably 0.30 × W or less (more preferably 0.20 × W or less) in order to stably accommodate the chip in the container and to shorten the polishing time. .

また、本発明は、NTCサーミスタ以外に、素体としてセラミックス半導体を用いるPTCサーミスタやバリスタに適用することができる。   In addition to the NTC thermistor, the present invention can be applied to a PTC thermistor and a varistor using a ceramic semiconductor as an element body.

本発明によるチップ型電子部品の一実施の形態であるNTCサーミスタの斜視図である。1 is a perspective view of an NTC thermistor which is an embodiment of a chip-type electronic component according to the present invention. 本実施の形態のNTCサーミスタの縦断面図である。It is a longitudinal cross-sectional view of the NTC thermistor of this Embodiment. 図2のE−E断面図である。It is EE sectional drawing of FIG. 従来のチップ型電子部品を示す斜視図である。It is a perspective view which shows the conventional chip-type electronic component.

符号の説明Explanation of symbols

1:素体、2、3:内部電極、4、5:端子電極、6:角部、7:焼付電極、8:第1のめっき層、9:第2のめっき層、10:内接円、R:内接円の半径、Ra:表面粗さ 1: Element, 2, 3: Internal electrode, 4, 5: Terminal electrode, 6: Corner portion, 7: Baking electrode, 8: First plating layer, 9: Second plating layer, 10: Inscribed circle , R: radius of the inscribed circle, Ra: surface roughness

Claims (3)

直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦0.5μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.03×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とするチップ型電子部品。
A semiconductor ceramic body having a rectangular parallelepiped shape has a plurality of internal electrodes facing each other inside, one or more internal electrodes are drawn out to one end of the element body, and the remaining internal electrodes are connected to the other side of the element body. It has terminal electrodes connected to internal electrodes drawn to the ends and connected to the internal electrodes drawn to the ends at both ends of the element body, and the terminal electrodes are baked electrodes on the element body and on the baked electrodes A chip-type electronic component having a plating electrode formed by electroplating,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 0.5 μm,
When the width of the element body is W, and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.03 × W,
The chip-type electronic component according to claim 1, wherein the element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.
直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦0.6μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.05×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とするチップ型電子部品。
A semiconductor ceramic body having a rectangular parallelepiped shape has a plurality of internal electrodes facing each other inside, one or more internal electrodes are drawn out to one end of the element body, and the remaining internal electrodes are connected to the other side of the element body. It has terminal electrodes connected to internal electrodes drawn to the ends and connected to the internal electrodes drawn to the ends at both ends of the element body, and the terminal electrodes are baked electrodes on the element body and on the baked electrodes A chip-type electronic component having a plating electrode formed by electroplating,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 0.6 μm,
When the width of the element body is W, and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.05 × W,
The chip-type electronic component according to claim 1, wherein the element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.
直方体状をなす半導体セラミックス素体内に互いに内部で対向する複数の内部電極を有し、1以上の内部電極を前記素体の一方の端部に引き出し、残りの内部電極を前記素体の他方の端部に引き出し、前記素体の両端にそれぞれの端部に引き出された内部電極に接続された端子電極を有し、前記端子電極は、素体に焼き付けた焼付電極と、この焼付電極上に電気めっきにより形成されためっき電極とを有するチップ型電子部品であって、
前記素体の表面粗さRaを0.1μm≦Ra≦2.0μmとし、
前記素体の幅をW、前記素体の側面と上下面との間の角部の内接円の半径をRとしたとき、R≧0.10×Wとし、
前記素体は前記端子電極で覆われた部分以外の部分が外部に露出した構造としたことを特徴とするチップ型電子部品。
A semiconductor ceramic body having a rectangular parallelepiped shape has a plurality of internal electrodes facing each other inside, one or more internal electrodes are drawn out to one end of the element body, and the remaining internal electrodes are connected to the other side of the element body. It has terminal electrodes connected to internal electrodes drawn to the ends and connected to the internal electrodes drawn to the ends at both ends of the element body, and the terminal electrodes are baked electrodes on the element body and on the baked electrodes A chip-type electronic component having a plating electrode formed by electroplating,
The element body has a surface roughness Ra of 0.1 μm ≦ Ra ≦ 2.0 μm,
When the width of the element body is W and the radius of the inscribed circle at the corner between the side surface and the upper and lower surfaces of the element body is R, R ≧ 0.10 × W,
The chip-type electronic component according to claim 1, wherein the element body has a structure in which a portion other than a portion covered with the terminal electrode is exposed to the outside.
JP2004060602A 2004-03-04 2004-03-04 Chip-type electronic components Active JP4111340B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004060602A JP4111340B2 (en) 2004-03-04 2004-03-04 Chip-type electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004060602A JP4111340B2 (en) 2004-03-04 2004-03-04 Chip-type electronic components

Publications (2)

Publication Number Publication Date
JP2005251993A true JP2005251993A (en) 2005-09-15
JP4111340B2 JP4111340B2 (en) 2008-07-02

Family

ID=35032189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004060602A Active JP4111340B2 (en) 2004-03-04 2004-03-04 Chip-type electronic components

Country Status (1)

Country Link
JP (1) JP4111340B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011176238A (en) * 2010-02-25 2011-09-08 Tdk Corp Chip-type electronic component
CN103854852A (en) * 2012-12-04 2014-06-11 三星电机株式会社 Embedded multilayer ceramic electronic component and method of manufacturing the same, and printed circuit board having embedded multilayer ceramic electronic component therein
JP2014130987A (en) * 2012-12-28 2014-07-10 Samsung Electro-Mechanics Co Ltd Board built-in multilayer ceramic electronic component and multilayer ceramic electronic component built-in printed circuit board
CN104008830A (en) * 2013-02-21 2014-08-27 株式会社村田制作所 Chip type positive-character thermistor element
JP2015088659A (en) * 2013-10-31 2015-05-07 京セラ株式会社 Electronic component
JPWO2016002305A1 (en) * 2014-07-04 2017-04-27 株式会社村田製作所 Thermistor element and electronic component
KR20190033433A (en) 2017-09-21 2019-03-29 다이요 유덴 가부시키가이샤 Ceramic electronic device and manufacturing method of ceramic electronic device
WO2019087777A1 (en) * 2017-11-02 2019-05-09 株式会社村田製作所 Thermistor element and method for producing same

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011176238A (en) * 2010-02-25 2011-09-08 Tdk Corp Chip-type electronic component
CN103854852A (en) * 2012-12-04 2014-06-11 三星电机株式会社 Embedded multilayer ceramic electronic component and method of manufacturing the same, and printed circuit board having embedded multilayer ceramic electronic component therein
JP2014110417A (en) * 2012-12-04 2014-06-12 Samsung Electro-Mechanics Co Ltd Board built-in multilayer ceramic electronic component and manufacturing method therefor, printed circuit board including board built-in multilayer ceramic electronic component
JP2014130987A (en) * 2012-12-28 2014-07-10 Samsung Electro-Mechanics Co Ltd Board built-in multilayer ceramic electronic component and multilayer ceramic electronic component built-in printed circuit board
US9370102B2 (en) 2012-12-28 2016-06-14 Samsung Electro-Mechanics Co., Ltd. Embedded multilayer ceramic electronic component and printed circuit board having embedded multilayer ceramic electronic component
CN104008830A (en) * 2013-02-21 2014-08-27 株式会社村田制作所 Chip type positive-character thermistor element
JP2014165184A (en) * 2013-02-21 2014-09-08 Murata Mfg Co Ltd Chip type positive characteristics thermistor element
JP2015088659A (en) * 2013-10-31 2015-05-07 京セラ株式会社 Electronic component
JPWO2016002305A1 (en) * 2014-07-04 2017-04-27 株式会社村田製作所 Thermistor element and electronic component
KR20190033433A (en) 2017-09-21 2019-03-29 다이요 유덴 가부시키가이샤 Ceramic electronic device and manufacturing method of ceramic electronic device
US10607782B2 (en) 2017-09-21 2020-03-31 Taiyo Yuden Co., Ltd. Ceramic electronic device and manufacturing method of ceramic electronic device
WO2019087777A1 (en) * 2017-11-02 2019-05-09 株式会社村田製作所 Thermistor element and method for producing same
CN111295724A (en) * 2017-11-02 2020-06-16 株式会社村田制作所 Thermistor element and method for manufacturing the same
US20200234856A1 (en) * 2017-11-02 2020-07-23 Murata Manufacturing Co., Ltd. Thermistor element and manufacturing method therefor
JPWO2019087777A1 (en) * 2017-11-02 2020-10-22 株式会社村田製作所 Thermistor element and its manufacturing method
US10854361B2 (en) 2017-11-02 2020-12-01 Murata Manufacturing Co., Ltd. Thermistor element and manufacturing method therefor

Also Published As

Publication number Publication date
JP4111340B2 (en) 2008-07-02

Similar Documents

Publication Publication Date Title
JP4111340B2 (en) Chip-type electronic components
JP4311124B2 (en) Chip-type electronic components
JP4936087B2 (en) Multilayer positive temperature coefficient thermistor
JP2009177085A (en) Ceramic element
JP3254399B2 (en) Multilayer chip varistor and method of manufacturing the same
CN108364786A (en) Monolithic ceramic capacitor and its manufacturing method
CN112242254B (en) Laminated electronic component and mounting structure thereof
JP2005353845A (en) Laminated chip varistor
JP2002203707A (en) Ceramic chip element with glass coating film and its manufacturing method
EP2680301B1 (en) Structure comprising electronic component and mounting body
JP6394702B2 (en) Chip ceramic semiconductor electronic components
JP2007099532A (en) Ceramic composition for varistor and laminated varistor
US20150091690A1 (en) Laminated ptc thermistor element
JP2006229005A (en) Chip-type electronic component
JP2010147169A (en) Multilayer ceramic electronic component
JP4515334B2 (en) Barrel plating method and electronic component manufacturing method
JP2007234330A (en) Conductor paste and electronic part
JP2005093574A (en) Multilayer positive characteristic thermistor and method of manufacturing the same
JP3038296B2 (en) Electronic component manufacturing method
JP2005327929A (en) Method for manufacturing semiconductor ceramic electronic component
JP4968309B2 (en) Paste composition, electronic component and method for producing multilayer ceramic capacitor
JP2005167010A (en) Manufacturing method of chip type varistor
JP4841613B2 (en) Ferrite core, manufacturing method thereof, and common mode noise filter
JP7031574B2 (en) Electronic components and their manufacturing methods
JP4041082B2 (en) Varistor and varistor manufacturing method

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070502

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070911

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071108

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080402

R150 Certificate of patent or registration of utility model

Ref document number: 4111340

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110418

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110418

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120418

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130418

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140418

Year of fee payment: 6