JP2005244862A - Power amplifier for multiple power mode having bias modulation option without using bypass switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power amplifier for multiple power modes having a low power mode and a high power mode without using a switch for reducing power consumption in the low power mode and elongating operation time of a battery type device. <P>SOLUTION: A power amplifier includes two or more impedance matching units (130, 140, 150, 160), an impedance converter (170), and an electric power stage (120). In a low power mode, the electric power stage (120) is turned off, and a signal is passed through a first impedance matching unit 130 and an impedance converter 170 and transmitted to a forth impedance matching unit 160. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to power amplifiers, and more particularly to wireless radio frequency (RF) amplifiers used in mobile handsets and other battery powered applications (eg, portable wireless devices, personal digital assistants (PDAs), notebook computers, etc.). . More particularly, the present invention relates to a highly efficient multi-power mode power amplifier suitable for amplifying power corresponding to various output power levels without using a bypass switching circuit.

  Mobile handsets or mobile phones (also called cellular horns) for wireless communication services are becoming increasingly smaller and lighter. This means that the size of the battery, usually a much larger part of the mobile handset, has also been reduced to facilitate the manufacture of smaller and lighter mobile handsets. At the same time, the phone and its battery are getting smaller, but it is preferable to extend the talk time of the mobile handset. As can be seen, this is a difficult goal to harmonize, and as the power consumption of the device is the same and the battery is smaller, the operating time of the device per battery charge amount is reduced.

  In conventional mobile handsets, radio frequency (RF) power amplifiers consume most of the power of the entire mobile handset system. Thus, a low efficiency RF power amplifier reduces the overall system efficiency and drains the battery more quickly, thus reducing call time. For this reason, much research in this area has focused on improving the efficiency of RF power amplification. If the RF power amplifier is more efficient, it will reduce power and battery drain and eventually increase the talk time or operating time of the device per battery charge.

  The multiple power mode power amplifier is one of the devices recently introduced as a result of such studies conducted to improve the efficiency of RF power amplifiers. This multiple power mode power amplifier is configured to operate its own power stage in response to a desired situation and to operate in one of several operating modes in response to the output power level. (For example, see Patent Documents 1 to 10). Bypass switching circuits have been used for this operation of multiple power mode power amplifiers.

  When low output power is required, it is preferable to adjust the transmission path to bypass the power stage. On the other hand, when high output power is required, it is preferable to adjust the power transmission path so as to pass the power stage in order to supply high output power. Using a conventional power amplifier for multiple power modes (using a bypass switch) that selectively performs mode transitions in response to a desired output power level can reduce DC power consumption when transmitting low output power signals. it can.

  However, multi-power mode power amplifiers with switches (eg, PIN diodes) are relatively expensive to manufacture, and the switches can have negative gains (eg, gain of -1 dB per switch), resulting in some reduction in efficiency. Let In order to execute the power amplifier for the multiple power mode, one or more power stages must be switched among a plurality of power stages connected in series with each other. A complex logic control circuit is required to control this.

  The output power is reduced due to the power loss due to the switching operation in the bypass switching circuit, and the efficiency of the power amplifier for the multiple power mode is reduced due to the reduction of the output power. There is another problem that the adjacent channel power ratio (ACPR) becomes worse. In addition, because the bypass switching circuit itself and the complex logic control circuit added to control the bypass switching circuit increase the overall system size, conventional power amplifiers for multiple power modes are miniaturized for mobile handsets. It is thought to go against the trend. Further, when the size of the entire system is increased, the switch is an expensive part, which is disadvantageous in price competitiveness.

  FIG. 1 illustrates conventional multiple power mode power amplification using a bypass switch or bypass switch circuit. The power amplifier for multiple power mode shown in FIG. 1 is configured using three bypass switch circuits.

  When this power amplifier operates in the high power mode, the first switch 31 and the second switch 32 are closed and the third switch 33 is opened, so that the output of the driver 10 including the impedance matching unit is the power stage 22 (or power amplification unit). Is input. In contrast, when the power amplifier operates in the low power mode, the first switch 31 and the second switch 32 are opened and the third switch 33 is closed, so that the output of the driver 10 including the impedance matching unit bypasses the power stage 22. .

  The power amplifier for the multiple power mode shown in FIG. 1 has a drawback that the size of the entire system increases and the power loss of the entire system increases due to the power loss of the bypass switch circuit. In particular, the power loss of the second switch 32 connected to the output terminal of the power stage has a large effect on the efficiency and linearity of the operation in the high power mode, so that the bypass switch circuit has a high power capacity and excellent loss characteristics. However, it is expensive to use a bypass switching circuit with high power handling capability and very low power loss.

  For example, a typical switch can be a PIN diode with a gain of -1 dB. When multiple switches are in series (ie, a series switch), gain loss accumulates. Also, since PIN diodes are usually not integrated with amplifiers, the number of required integrated circuits (ICs) or chips or components is increased, thereby increasing costs. Also, the PIN diode itself is relatively expensive to include in the circuit. Examples of other types of switches are relays, micromachined switches, transistor switches, PIN diode switches, and Schottky diode switches.

  The switch can be made from active or passive elements. Common active devices include PIN diodes, Schottky diodes, and transistors. The term “active” means that a DC supply and power consumption are required for the device to operate properly.

  The switch can also be implemented using passive elements such as mechanical relays. Also, with the recent development of MEMS (micro electro mechanical system) technology, machined mechanical switches that can be used in integrated circuits have become possible. Passive switches do not require power consumption, but still require a control DC signal for operation.

  In general, these switches can all be classified as switches or switch elements, which share three distinct features. These switches add loss to the signal and add cost to the overall system. Also, an external control signal is required to turn this switch on and off.

  FIG. 2 shows a conventional multiple power mode power amplifier using another bypass switch circuit. The power amplifier for multiple power mode shown in FIG. 2 is configured by combining a single-pole and double-throw (SPDT) switch and a shunt switch (non-series) in the bypass path.

  An input signal to be amplified is connected to the pole 41 of the switch 44. Switch 44 may operate to connect the input signal to throw 42 or throw 43. The slow 43 is connected to the input of the power amplification stage 45. The output of the power amplification stage 45 is connected to the first side of the first impedance converter 47. The second side of the first impedance converter 47 is connected to the output node 50. The slow 42 is connected to the first side of the second impedance converter 46. The third impedance converter 48 has a second side of the first impedance converter 47 and a first side directly connected to the output node 50. The second side of the third impedance converter 48 is switched between the second side of the second impedance converter 46 and the ground by a switch 49.

  The operation of the switch 49 is combined with the operation of the switch 44. The impedance conversion unit or the like is configured so that the output of the amplification stage 45 meets the correct load impedance by the first impedance conversion unit 47 when the input signal is connected to the amplification stage 45 via the switch 44 in the high power mode. Having a selected impedance value; When operating in the low power mode, i.e., when the switch 44 is connected to the slow 42 and transmits the input signal through the impedance converter 46, the input signal meets the correct load impedance by the second impedance converter 46.

  Since the power amplifier shown in FIG. 2 must use at least two SPDTs, the characteristic is deteriorated due to the inherent loss of the switch, and the manufacturing cost is increased due to the use of a relatively expensive switch and a large power amplification stage.

  FIG. 3A shows a conventional multiple power mode power amplifier used by a bypass switch circuit, where the switch circuit is connected to the output terminal of the λ / 4 bypass transmission line. The power amplifier for multiple power mode shown in FIG. 3A includes a carrier amplifier 51 and has a bypass executed by a bypass switch circuit made up of a λ / 4 bypass transmission line 52 and a shunt switch 53.

  In the high power mode, the shunt switch 53 of the bypass switch circuit is connected to the ground, and the bypass switching circuit including the shunt switch 53 is connected to the λ / 4 bypass transmission line 52 to operate as a short-circuited stub. Open circuit as seen from the carrier amplifier.

  In the low power mode, the shunt switch 53 of the bypass switching circuit is connected to the output terminal of the carrier amplifier 51 and operates as a bypass together with the λ / 4 bypass transmission line 52.

  FIG. 3B shows a conventional multiple power mode power amplifier using a bypass switch circuit, where the switch circuit is connected to the input terminal of the λ / 4 bypass transmission line.

  The difference between the multiple power mode power amplifier shown in FIG. 3B and the multiple power mode power amplifier shown in FIG. 3A is only in the order of the λ / 4 bypass transmission line and the bypass switch circuit.

  Since the power amplifier for multiple power mode shown in FIGS. 3A and 3B includes only one bypass switch circuit, it has an advantage that the size of the entire system is small. However, at the same time, the bandwidth is limited by the use of the λ / 4 bypass transmission line, which has the disadvantage of requiring a large area to accommodate a long transmission line.

  FIG. 4 shows a conventional multiple power mode power amplifier using another bypass switch circuit. The power amplifier includes an input stage transistor 62, an output amplifier stage transistor 65, a series switch 66 composed of two parallel diodes, and a switching transistor 68.

  In the high power mode, the switching transistor 68 is off and the series switch 66 is open. Therefore, the output of the input stage transistor 62 is input to the output stage transistor 65 and the first impedance matching unit 63 that converts the input impedance to an impedance of 15 ohms.

  In the low power mode, since the base bias of the output stage transistor 65 is off and the switching transistor 68 is on, the switch 66 is closed. The second impedance matching unit 64 converts the load impedance into an impedance of 25 ohms. The second impedance matching unit 64 has an impedance smaller than the input impedance of the output stage transistor 65 when the switch 66 is turned on, but has an impedance larger than the input impedance of the output stage transistor 65 when the switch 66 is turned on. Therefore, the second impedance matching unit 64 operates as a bypass.

US Pat. No. 5,152,004 US Pat. No. 5,175,871 US Pat. No. 5,276,912 US Pat. No. 5,530,923 US Pat. No. 5,661,434 US Pat. No. 5,758,269 US Pat. No. 5,909,643 US Pat. No. 6,060,949 US Pat. No. 6,069,526 US Pat. No. 6,356,150

  Accordingly, the present invention has been made in view of the conventional problems as described above, and an object thereof is to provide a more efficient power amplifier, particularly a power amplifier for a multiple power mode that does not use any switch.

  To achieve the above objective, the present invention includes a switch so as to avoid problems such as power loss, increased size, and increased cost associated with conventional multiple power mode power amplifiers using bypass switches. Provided is a power amplifier for a multiple power mode that amplifies various levels of power with a bypass circuit. Moreover, since the power amplifier for multiple power mode of the present invention reduces DC power in the low power mode, the power added efficiency (PAE) characteristic of the power amplifier is improved, and the power amplifier having the power amplifier for multiple power mode of the present invention is provided. The operating time of the electronic device (for example, the talk time of the mobile handset) can be extended.

  In one embodiment, the multiple power mode power amplifier of the present invention uses a variable gain amplifier as a driver to minimize power loss associated with conventional multiple power mode power amplifiers in the high power mode. PAE characteristics in the power mode are improved, and poor linearity in the high power mode can be solved. In addition, improvement in sound quality and reduction in size can be obtained in a mobile handset or telephone equipped with the power amplifier for multiple power modes of the present invention.

  One embodiment of the present invention solves the above-mentioned problems of a conventional power amplifier for multiple power modes using a bypass switch, and forms a path that bypasses the power stage and a path that passes through the power stage connected at the optimum point. In addition, by providing an optimum impedance converter on a path that bypasses the power stage, a high-efficiency multi-power mode power amplifier that can amplify various levels of power without using a bypass switch is provided. .

  In one embodiment, the present invention is amplified by a driver through a first impedance matching unit connected in series to a driver that amplifies input power and a second impedance matching unit connected to the first impedance matching unit. A power stage that receives power, amplifies the power again, and outputs the amplified power, and an application connected to the power stage to control applied voltages corresponding to the first power mode and the second power mode According to the operation of the voltage control circuit, the applied voltage control circuit, an impedance converter that receives the power amplified by the driver via the first impedance matching unit, and according to the operation of the applied voltage control circuit, In order to receive the power amplified by the power stage, it is connected in series to the power stage. A third impedance matching unit; and the third impedance matching unit and the impedance to transmit the power transmitted from the third impedance matching unit or the impedance converter to an output stage according to the operation of the applied voltage control circuit. A high-efficiency multi-power mode power amplifier including a fourth impedance matching unit connected to a converter is provided.

  According to an embodiment, the power stage is connected to the second impedance matching unit, and in the second power mode, the power stage receives the power amplified by the driver via the second impedance matching unit, This power is amplified again.

  In one embodiment, the applied voltage control circuit includes a voltage applied to the power stage so that the power stage is turned off in the first power mode and the power stage is turned on in the second power mode. Adjust.

  In one embodiment, the impedance converter is connected in a branch parallel to the second impedance matching unit, the power stage, and the third impedance matching unit, and in the first power mode, the impedance converter is driven by the driver. The amplified power is received through the first impedance matching unit, and this power is output to the fourth impedance matching unit. In a specific embodiment, the impedance converter has a band-pass filter structure. In another embodiment, the impedance converter is any of a band selection filter such as a band pass filter, a band reject filter, a low pass filter, or a high pass filter.

  In one embodiment, the third impedance matching unit prevents power transmitted through the impedance converter from leaking to the power stage.

  In one embodiment, the fourth impedance matching unit receives power from the impedance converter in the first power mode, and the fourth impedance matching unit receives power from the third impedance matching unit in the second power mode. .

  In one embodiment, the path through which the power that has passed through the first impedance matching unit is transmitted to the fourth impedance matching unit is the impedance when viewed from the first impedance matching unit to the power stage side. It is determined by comparing the impedance when viewed from the first impedance matching unit to the impedance converter side.

  In one embodiment, the impedance when viewed from the first impedance matching unit to the impedance converter side is interstage matching between the driver and the power stage together with the first impedance matching unit in the second power mode. Part of the part is formed.

  In another specific example, a high-efficiency multiple power mode power amplifier includes a driver that variably amplifies the gain of an input signal using a variable gain amplifier, and a first impedance matching unit connected in series to the driver And a power stage that receives the power amplified by the driver via the second impedance matching unit connected to the first impedance matching unit, amplifies the power again, and outputs the amplified power, In order to control the applied voltage corresponding to the 1 power mode and the di 2 power mode, the applied voltage control unit connected to the power stage and the power amplified by the driver according to the operation of the applied voltage control circuit are Impedance converter received via first impedance matching unit, and applied power control circuit In order to receive the power amplified by the power stage according to the operation, the third impedance matching unit connected in series to the power stage, and the power transmitted from the third impedance matching unit or the impedance converter In order to transmit to the output stage according to the operation of the applied voltage control circuit, the third impedance matching unit and a fourth impedance matching unit connected to the impedance converter are included.

  In one embodiment, the power stage is connected in series to the second impedance matching unit, and in the second power mode, the power stage receives the power amplified by the driver through the second impedance matching unit. This power is amplified again.

  In one embodiment, the applied voltage control circuit controls the driver so that a gain of a signal input to the driver is variously amplified according to the first power mode and the second power mode. The applied voltage control circuit adjusts a voltage applied to the power stage so that the power stage is turned off in the first power mode and the power stage is turned on in the second power mode.

  The amplifier may have more than one power mode. For example, the amplifier may have three, four, five, six or more modes, such as several different power modes using various amounts of power.

  In one embodiment, the impedance converter is connected in parallel to a circuit branch including the second impedance matching unit, the power stage, and the third impedance matching unit, and in the first power mode, the impedance converter is The power amplified by the driver is received via the first impedance matching unit, and this power is output to the fourth impedance matching unit. The impedance converter has a bandpass filter structure. In other embodiments, the impedance converter can be any band selection filter such as a band pass filter, a band reject filter, a low pass filter, or a high pass filter.

  In one embodiment, the third impedance matching unit prevents power transmitted through the impedance converter from leaking to the power stage.

  In one embodiment, the fourth impedance matching unit receives power from the impedance converter in the first power mode, and the fourth impedance matching unit receives power from the third impedance matching unit in the second power mode. .

  In one embodiment, a path through which power passes through the first impedance matching unit and is transmitted to the fourth impedance matching unit is an impedance when viewed from the first impedance matching unit to the power stage side. And the impedance when viewed from the first impedance matching unit to the impedance converter side.

  In one embodiment, the impedance when viewed from the first impedance matching unit to the impedance converter side is interstage matching between the driver and the power stage together with the first impedance matching unit in the second power mode. Part of the part is formed.

  In one embodiment, a multiple power mode power amplifier configured for a portable electronic device includes a driver for supplying power. The power stage transistor includes an input node and an output node. An input node of the power stage transistor is coupled to the driver for receiving power from the driver in a high power mode. The impedance converter includes an input node and an output node, and is provided in a parallel branch to the power stage transistor. The input node of the impedance converter is configured to receive power from the driver in a low power mode.

  In another embodiment, the portable electronic device includes a power source and a power amplifier connected to the power source. The power amplifier includes a driver for supplying power, an input node, and an output node, and the input node is connected to the driver to receive power from the driver and receives power from the driver in a high power mode. A power stage transistor configured as described above and an input node and an output node provided in parallel branches to the power stage transistor, wherein the input node is configured to receive power from the driver in a low power mode Including a converter.

  In another specific example, a power amplifier for a multiple power mode configured for a mobile phone includes a driver that supplies power, an input node, and an output node, wherein the input node is coupled to the driver and is high-powered. A power stage transistor that receives power from the driver during a power mode; a first impedance matching unit coupled to the driver to receive power output by the driver; the first impedance matching unit and the power A second impedance matching unit provided between the stage transistors; and an input node and an output node. The power stage transistor is provided in a parallel branch, wherein the input node is in the low power mode operation. To receive power from the club An impedance converter; a third impedance matching unit having a first side and a second side, wherein the first side is connected to the output node of the power stage transistor; and the third impedance matching. And a fourth impedance matching unit connected to the output node of the impedance converter.

  In still another specific example, the power amplifier for the multiple power mode receives the first power from the driver through the first and second impedance matching units during the high power mode and outputs a second power larger than the first power. A power stage transistor configured to be coupled to the power stage transistor and applying a first signal to the power stage transistor during the high power mode to turn on the power stage transistor and during the low power mode An applied voltage control circuit configured to apply a second signal to the power stage transistor to turn off the power stage transistor; and from the driver via the first impedance matching unit during the low power mode; Configured to receive a third power less than the second power An impedance converter, a third impedance matching unit coupled in series with the power stage transistor and configured to receive the second power output by the power stage transistor during the high power mode; and The second power is connected in series to the impedance matching unit, receives the second power from the third impedance matching unit or receives the third power from the impedance converter, and transmits the received second or third power to the output stage. 4 impedance.

  As described above, the present invention uses an amplifier circuit having a plurality of modes without a switch in a wireless transmitter or receiver such as a mobile phone. Since the present invention uses an amplifier circuit having a plurality of modes without a switch, the transmission time of the portable wireless device is extended. The present invention uses an amplifier circuit having multiple modes without a switch, thus extending the battery life of the portable wireless device. The present invention uses an amplifier circuit having two or more modes without a switch so as to operate in a low power mode or a high power mode depending on the distance to the receiving antenna, thereby improving efficiency and reducing power consumption. cut back. The present invention varies the impedance of the power stage in order to vary from the low power mode to the high power mode or from the high power mode to the low power mode without using a switch. The present invention uses the impedance section to change from one power mode of the amplifier to another power mode without a switch.

  The present invention also provides a bias modulation circuit that reduces power consumption by varying biasing to the amplifier. This is different from the technique of switching off the amplifier. By changing the biasing of the amplifier, the operation mode is changed and the class AB is closer to the class B than the class A. With such a technique, power consumption in the low power mode is reduced compared to an amplifier module without a bias modulation circuit.

  Other objects, features and advantages of the present invention can be clearly understood from the following detailed description and the accompanying drawings.

  Hereinafter, a high-efficiency multiple power mode power amplifier according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, the first power mode is referred to as a low power mode, and the second power mode is referred to as a high power mode.

  FIG. 5 illustrates a high efficiency multi-power mode power amplifier using a power mode transition structure without a bypass switch circuit, according to one embodiment of the present invention. In other words, the amplifier does not include any switches or switch elements in the circuit configuration. As described above, examples of switches include relays, micromachined switches, transistor switches, PIN diode switches, and Schottky diode switches.

  The present invention does not use any switch, there is no external control circuit provided to control the switch, and there is no increase in cost and loss due to having the switch. This allows circuits such as multimode amplifiers to be filled in a compact, simple and cost effective manner. Also, no loss means that performance (ie, linearity and efficiency) can be maximized. Although described for a multimode amplifier, the techniques of the present invention can be applied to other types of circuits.

  The high-efficiency multi-power mode power amplifier shown in FIG. 5 includes a driver 100 that amplifies input power, a first impedance matching unit 130 that connects the power amplified by the driver 100 to the driver, and the first impedance. A power stage 120 that receives the power through the second impedance matching unit 140 connected to the matching unit 130, re-amplifies the power, and outputs the re-amplified power, and corresponds to the low power mode and the high power mode. In order to control the applied voltage, the applied voltage control circuit 90 connected to the power stage 120 and the operation of the applied voltage control circuit 90 cause the power amplified by the driver 100 to pass through the first impedance matching unit 130. And transmit power to the fourth impedance matching unit 160. A third impedance matching unit 150 connected in series to the power stage 120 to transmit the power amplified by the impedance converter 170 and the power stage 120 to the fourth impedance matching unit 160; The fourth impedance connected to the third impedance matching unit 150 and the impedance converter 170 to transmit the power transmitted from the unit 150 or the impedance converter 170 to the output node 240 by the operation of the applied voltage control circuit 90. And a matching unit 160.

  As will be described below, in one embodiment, the power stage 120 includes one or more transistors that regulate the power flow through the power stage. The power stage 120 can also amplify the power received from the driver 100 during the high power mode operation. Therefore, the power stage 120 can also be referred to as a “power amplification stage” or a “power stage transistor”. In one embodiment, the power stage includes one or more transistors. Further details are described below. A transistor that amplifies the signal in the signal path may be referred to as a power stage transistor.

  The applied voltage control circuit 90 adjusts the voltage applied to the power stage 120 by inputting an external control signal corresponding to the low power mode and the high power mode. Since the output power decreases in the low power mode by passing through the optimized first impedance matching unit 130 and the optimized impedance converter 170 instead of the power stage 120, the transistor 120 of the power stage 120 is turned off. Thus, the applied voltage control circuit 90 adjusts the voltage applied to the power stage 120.

  In contrast, in the high power mode, the output power is increased by passing through the first impedance matching unit 130, the second impedance matching unit 140, and the power stage 120, so that the applied voltage control circuit 90 is a transistor of the power stage 120. A voltage suitable for the operation is applied. This increases power consumption.

  In the low power mode, the driver 100 amplifies the input power and transmits the amplified power to the impedance converter 170 through the optimized first impedance matching unit 130. In contrast, in the high power mode, the driver 100 amplifies the input power, and the power stage passes through the first impedance matching unit 130 and the optimized second impedance matching unit 140 that optimize the amplified power. 120.

  The power stage 120 in the low power mode is turned off by the applied voltage control circuit 90. In the high power mode, the power stage 120 is turned on, and the signal input to the power stage 120 is amplified by the driver 100.

  The first impedance matching unit 130 is a circuit optimized to operate optimally corresponding to the low power mode and the high power mode. The first impedance matching unit 130 transmits the input power amplified by the driver 100 corresponding to the operation mode to the impedance converter 170 or the power stage 120.

  The second impedance matching unit 140 is a circuit optimized to operate optimally in accordance with the low power mode and the high power mode. In the low power mode, the second impedance matching unit 140 transmits the power amplified by the driver 100 and transmitted through the first impedance matching unit 130 to the impedance converter 170. In the high power mode, the second impedance matching unit 140 transmits the power to the power stage 120. To transmit. In the high power mode, the second impedance matching circuit also functions as an interstage matching circuit that efficiently transmits power from the driver to the power stage. For this purpose, the second impedance matching unit works with the first impedance matching unit and the impedance converter to perform power matching.

  The impedance converter 170 is an impedance conversion circuit that converts the impedance appropriately corresponding to the low power mode or the high power mode. In the low power mode, impedance converter 170 forms a path that bypasses power stage 120 so that the output of driver 100 is communicated via node 76 to output node 240 of the power amplifier.

  FIG. 6 shows the high-efficiency multi-power mode power amplifier shown in FIG. 5 in order to explain the power mode transition structure without a bypass switching circuit in more detail.

  The output power of the driver 100 reaches the junction 72. In the junction 72, a path is divided through the first impedance matching unit 130 corresponding to the power mode.

In the low power mode, it is turned off by the voltage applied by the applied voltage control circuit 90, and the input impedance (Z _INT-H ) of the power stage 120 viewed from the first impedance matching unit 130 (see FIG. 5) is the first impedance matching. It is larger than the input impedance (Z _INT-L ) of the path bypassing the power stage 120 as viewed from the unit 130. The input impedance (Z _INT-H ) is significantly or considerably larger than the input impedance (Z _INT-L ). In one embodiment, Z _INT-H is in the range of approximately 2 to 3 times greater than Z _INT-L . In one embodiment, Z _INT-H is less than approximately three times Z _INT-L . In one _{embodiment, Z INT-H} has 2 times greater greater than _{Z INT-L,} about three times smaller than _{Z INT-L.}

  The design of the impedance converter 170 is optimized together with the third impedance matching unit 150 and the fourth impedance matching unit 160 so as to lower the impedance level viewed from the first impedance matching unit 130 in the low power mode. Therefore, since the power signal amplified by the driver 100 and transmitted to the junction 72 is optimized, the amount of power input to the impedance converter 170 is significantly or considerably larger than the amount of power input to the power stage 120. The output power signal is transmitted to the output node 240, but the power leakage to the power stage is minimized by the impedance conversion action of the second impedance matching unit 170 together with the third impedance matching unit 150 and the fourth impedance matching unit 160.

In the high power mode, the power stage 120 is turned on under the control of the voltage applied by the applied voltage control circuit 90, and the input impedance (Z _INT-H ) of the power stage 120 viewed from the first impedance matching unit 130 is the first. The impedance is smaller than the input impedance (Z _INT-L ) of the path bypassing the power stage 120 as viewed from the one impedance matching unit 130. The impedance converter 170 is optimally used with the third impedance matching unit 150 and the fourth impedance matching unit 160 to increase the Z _INT-L of the bypass path that is much larger than the Z _INT-H of the power stage 120 in the high power mode. Designed. The second impedance matching unit 140 is designed to increase the impedance level viewed from the first impedance matching unit 130 and perform interstage matching in the high power mode. Therefore, most of the power amplified by the driver 100 and transmitted to the junction 72 is amplified by the power stage 120 and transmitted to the output node 240 of the power amplifier, while the optimized third impedance matching unit 150 and the optimal The power leakage to the impedance 170 is minimized by the converted fourth impedance matching unit 160.

The input impedance (Z _INT-L ) of the path bypassing the power stage 120 when viewed from the first impedance matching unit 130 is the driver 100 and the power stage 120 together with the first impedance matching unit 130 and the second impedance matching unit 140 in the high power mode. Since the interstage matching unit is formed therebetween, the output power of the driver 100 is well transmitted to the power stage 120 without power reflection.

In the high power mode, the input impedance (Z _INT-L ) is significantly or significantly greater than the input impedance (Z _INT-H ). In one embodiment, Z _INT-L is approximately twice as large as Z _INT-H . In one embodiment, Z _INT-L is approximately three times larger than Z _INT-H . In one embodiment, Z _INT-L is greater than twice Z _INT-H . In one embodiment, Z _INT-L is greater than 3 times Z _INT-H . In one embodiment, Z _INT-L is in the range of approximately 2 to 3 times greater than Z _INT-H . In one embodiment, Z _INT-L is less than approximately 3 times Z _INT-H . In one _{embodiment, Z INT-L} is at least 2 times greater than _{Z INT-H,} about three times smaller than _{Z INT-H.}

  In the low power mode, the power stage is in a state called an off state, and in the high power mode, the power stage is in a state called an on state. In the on state, the power stage consumes much more power than in the off state. Also, in one embodiment, the input impedance to the power stage is approximately twice as large in the off state as in the on state. In one embodiment, the input impedance to the power stage is approximately twice as large in the off state as compared to the on state.

  FIG. 7A is a graph showing gain characteristics corresponding to a high power mode and a low power mode of a power amplifier for multiple power modes according to an embodiment of the present invention.

  In the low power mode, the power stage 120 is turned off under the control of the applied voltage control circuit 90, so that the output of the driver 100 is amplified by the power stage 120, and the output of the driver 100 is output to the output node 240 via the impedance converter 170. Is transmitted to. Therefore, the gain characteristic is different from the characteristic when the output of the driver 100 is amplified by the power stage 120. The dotted line indicates the gain when the power stage is on, while the solid line indicates the gain when the power stage is off. In the low power mode, DC power is not consumed by the power stage 120, and thus has excellent power added efficiency (PAE) characteristics. PAE is ((Pout-Pin) / Pdc). In FIG. 7B, the PAE when the power stage is on is indicated by a dotted line, and when the power stage is off, the PAE is a solid line. Using the technique of the present invention, the amplifier has excellent PAE in low power mode.

  In contrast, in the high power mode, the driver 100 is amplified by the power stage 120 and reaches the output node 240, so that a power gain is added to the output of the driver 100, and the PAE characteristic is generally a power having a high output power level. According to stage 120.

  Therefore, as shown in FIG. 7A, the gain characteristic is relatively low in the low power mode (that is, gain of A), and the gain characteristic is relatively high in the high power mode (that is, gain of B).

  FIG. 7B is a graph showing PAE characteristics corresponding to a high power mode and a low power mode of a power amplifier for multiple power modes according to an embodiment of the present invention.

  As shown in FIG. 7B, since the DC consumption by the power stage 120 can be eliminated, the PAE characteristic (see the solid line) in the low power mode is excellent. In the high power mode, the output of the power stage 120 is transmitted to the output node 240 through the third impedance matching unit 150 and the fourth impedance matching unit 160, and the third impedance matching unit 150, the fourth impedance matching unit 160, and the impedance conversion. Since the device 170 does not use a switch, the output of the power stage 120 is transmitted to the output node 240 without loss, and the PAE characteristic in the high power mode is excellent.

  FIG. 8 shows a more detailed circuit diagram of a specific embodiment of the multiple power mode power amplifier of FIG. A specific circuit embodiment of the first impedance matching circuit 130 of FIG. 5 is shown in box 130 of FIG. A specific circuit embodiment of the second impedance matching circuit 140 of FIG. 5 is shown in box 140 of FIG. A specific circuit embodiment of the third impedance matching circuit 150 of FIG. 5 is shown in box 150 of FIG. A specific circuit embodiment of the fourth impedance matching circuit 160 of FIG. 5 is shown in box 160 of FIG. A specific circuit embodiment of the impedance transformation circuit 170 of FIG. 5 is shown in box 170 of FIG. A specific circuit embodiment of the driver circuit 100 of FIG. 5 is shown in box 100 of FIG. A specific circuit embodiment of the power stage circuit 120 of FIG. 5 is shown in box 120 of FIG. A specific circuit embodiment of the applied voltage control circuit 90 of FIG. 5 is shown in box 90 of FIG.

  FIG. 8 also shows an input matching circuit 80 not shown in FIG. 5 that is used to provide impedance to the input to prevent or minimize reflected waves. This is merely an example of an input matching circuit, and many other circuit configurations are also used.

  The input signal is connected to the power mode amplifier at node 70 to input matching circuit 80. In the input matching circuit 80, the inductor 9003 is connected between the node 70 and the node 9006, the capacitor 9009 is connected between the node 9006 and the node 9011, and the capacitor 9013 is connected between the node 9006 and the reference voltage line, that is, the ground. .

  The embodiment of FIG. 8 uses a bipolar junction transistor (BJT). However, in other embodiments, the present invention is heterostructure bipolar transistor, heterojunction bipolar transistor, MOS transistor, field effect transistor (FET), MESFET, JFET, BiCMOS, triode, complementary metal oxide semiconductor (CMOS) transistor technology. Metal oxide semiconductor transistor, p-type metal oxide semiconductor transistor, n-type metal oxide semiconductor transistor, high electron mobility transistor, metal semiconductor field effect transistor, and similar elements, and other types of active elements as appropriate It can also be used in combination. These devices can be manufactured using semiconductor technologies including silicon, gallium arsenide, silicon insulator, or silicon germanium. One or more elements can also be manufactured using nanotechnology. Further, the specific type of BJT shown is an npn type element. However, it can be seen that this circuit configuration can also use pnp-type elements if changes are required. As yet another example, NMOS (or n-channel MOSFET) or PMOS (or p-channel MOSFET) devices may also be used. CMOS production technology allows the fabrication of NMOS and PMOS device types for single integrated circuits.

  Driver 100 has a BJT transistor Q5, also called a driver transistor, whose base is connected to node 9011 and whose emitter is connected to a reference voltage (ground in a specific example). The collector of the BJC transistor Q5 is connected to the node 9015 that is the input of the first impedance matching unit 130 while being the output of the driver. The circuit configuration shown for the driver is merely an example of a usable driver circuit, and other amplifier designs can be used. The driver 100 is a common emitter type amplifier circuit. Other amplifier circuit structures that can be used include common base, cascade and cascode. These amplifier circuits can require different bias circuits and voltages or currents as shown or described in FIG. 8, and the circuits can be varied appropriately.

  DC power is supplied to the BJT transistor (Q5) through two voltage sources, ie, a first voltage and a second voltage. The second voltage is supplied to the node 9011 through the transistor 9017 and the resistor or impedance 9019. A capacitor or capacitance 9021 is connected between the second voltage and the reference voltage. A base electrode of the transistor 9017 is connected to the node 9023. A resistor 9025 is connected between the first voltage and the node 9023. Two diodes are connected between the node 9023 and the reference voltage. Although two diodes are shown, other numbers (for voltage drops) of diodes can be used to provide a bias voltage. Providing more diodes increases the voltage drop.

  In a particular embodiment, the voltage is approximately 2.85V. The first voltage may be a relatively constant voltage supplied from a voltage source such as a voltage stabilizer to the multiple power mode amplifier circuit. As mentioned above, the application of the circuit configuration is in battery powered devices such as mobile or cellular horns powered by a battery. In such applications, the particular level of one or more voltage sources can vary depending on battery conditions. When newly charged, the battery usually provides a high voltage level, which depends on the specific battery technology or chemical component (eg, nickel metal hydride battery, nickel cadmium battery, lithium ion battery, lead acid battery). Descends gradually as it depletes. In certain embodiments, the second voltage is a voltage source having a level corresponding to the battery condition. For example, when the battery is fully charged, the second voltage is 4.2V, and when the battery is nearly or completely exhausted, the second voltage is approximately 3.2V. The amplifier circuit of FIG. 8 must operate properly in all battery voltage conditions. In general, the worst operating condition is given at the lowest voltage level that appears during normal operation, which occurs when the battery is almost depleted.

  The first impedance matching unit 130 is connected between the node 9015 and the node 72. In the embodiment of FIG. 8, the first impedance matching unit includes a transmission line 9028 connected between the node 9015 and the second voltage, a capacitor 9030 connected between the second voltage and the reference voltage, and between the node 9015 and the node 72. And a capacitor 9032 connected to.

  The transmission line can simply be a wire or wire that can be designed as a ladder network of series inductors and shunt capacitors. The characteristics of a transmission line depend on the length and width of the line or wire, which is a design variable. In one specific example, the transmission line is a wire whose wire length is 1/10 or more of the guide wavelength in the medium. This wavelength usually varies depending on the particular medium. For example, if the medium is air versus semiconductor, the wavelength will be different. For semiconductor media and 2 GHz signals, the transmission line can have a line length of approximately 10 μm or more. The width of this transmission line can be approximately 5 μm or more.

  In another embodiment, the transmission line is a line whose wire length is 1/20 or more of the guide wavelength in the medium. In another embodiment, the transmission line is a line whose wire length is 1/30 of the guide wavelength in the medium. In another embodiment, the transmission line is a line whose wire length is 1/50 of the guide wavelength in the medium. In another embodiment, the transmission line is a line whose wire length is 1/100 of the guide wavelength in the medium.

  A second impedance matching unit 140 is connected between the node 72 and the node 74. In the embodiment of FIG. 8, the second impedance matching unit includes an inductor 9037 connected between the node 72 and the reference voltage, and a capacitor 9039 connected between the node 72 and the node 74. The inductor of this circuit or any circuit of the present invention can be constructed by any technique for providing an inductance device. Examples of inductance devices or inductor embodiments include wire bonding, transmission lines, microstrip lines, strip lines, coaxial cables, or coplanar waveguides. Any of these or a combination thereof may be used to construct the inductance of the present invention, such as that shown in the circuit diagram with an inductor symbol.

  An impedance conversion circuit 170 is connected between the nodes 72 and 76. In the embodiment of FIG. 8, the impedance transformation circuit is connected between node 7244 and node 9042, capacitor 9042 connected between node 9044 and reference voltage, node 9044 connected between node 9044 and node 76. An inductor 9048.

  A power stage is connected between node 74 and node 9116. The power stage is an amplifier circuit including a BJT transistor Q6 whose base is connected to node 74, a collector connected to node 9116, and an emitter connected to a reference voltage. Similar to driver 100, power stage 120 is a common emitter amplifier circuit. Other amplifier circuit structures that can be used include common base, cascade and cascode. These amplifier circuits can require various bias circuits and the voltages or currents shown or described in FIG. 8, and the circuits can be modified appropriately. The power stage 120 can also be other types of amplifier circuits from the driver 100.

  The power stage can be turned on or off depending on the voltage at voltage control node 9051. FIG. 8 shows a specific embodiment of the applied voltage control circuit 90. Other circuits that perform similar functions can also be used. When the voltage control node is at a first level (eg, approximately the first voltage level or 2.85V), the amplifier circuit may be in a low power mode. The circuit may be in a high power mode when the voltage control node is at a second level (eg, approximately the level of the reference voltage or ground or 0V). When in low power mode, transistor Q6 is in high impedance mode and draws little current. When in the high power mode, the transistor Q6 operates and draws current, thereby amplifying the input signal. In one embodiment, in the high power mode, the power stage provides a gain of approximately 5-15 dB. However, the exact one depends on the transistor used or the device technology or how the amplifier circuit is biased. Hereinafter, other specific examples of the multi-mode amplifier configured using other technologies such as CMOS and MESFET will be described.

  In operation, depending on the voltage level at node 9051, the current from the first voltage passes through node 9103 and then either (a) proceeds to the reference voltage through transistor 9105 or (b) through transistor 9108. Go to node 74 and then to the base of transistor Q6. When in the low power mode, node 9051 is 2.85V, a relatively small current passes through transistor 9108 compared to the path through transistor 9105, and transistor Q6 is at approximately the reference voltage or 0V. The stage is turned off. When in the high power mode, node 9051 is at the reference voltage or 0V, and a relatively small current passes through transistor 9105 compared to the path through transistor 9108, and the base of transistor Q6 is approximately 1.0V and 1. Since it is 4V, the power stage is activated or turned on.

  The third impedance matching unit 150 is connected between the nodes 9116 and 76. In the embodiment of FIG. 8, the third impedance matching unit includes a transmission line 9072 connected between the node 76 and the second voltage, and a capacitor 9074 connected between the second voltage and the reference level. In certain embodiments, capacitor 9074 is relatively large, approximately 100 picofarads. This capacitor provides RF or virtual ground at the second voltage to stabilize the second voltage. A capacitor 9119 is connected between node 9116 and the reference level. Inductor 9122 is connected between nodes 9116 and 76.

  An inductor 9122 can be formed on the same integrated circuit as one or more other components in the MMIC box of FIG. In certain embodiments, inductor 9122 is formed using wire bond lines between components at nodes 9116 and 76. The inductor 9122 can be formed using a passive component such as an inductor coil.

  In one embodiment, the components shown in the MMIC box are on-chip, meaning that these components are included in a single integrated circuit such as the same semiconductor die or semiconductor body. Inclusion of as many components as possible on a single integrated circuit saves money and reduces the space required for the amplifier. This is particularly important for portable electronic devices where consumers desire a more compact form factor. In other embodiments, one or more components shown in the MMIC box can be off-chip using separate components or different integrated circuits. A fourth impedance matching unit 160 is connected between the node 76 and the output signal node 240. In the embodiment of FIG. 8, the fourth impedance matching unit includes a transmission line 9082 connected between the node 76 and the node 9084, a capacitor 9088 connected between the node 76 and the reference level, and between the node 9084 and the output signal 240. And a connected capacitor 9090. In one embodiment, capacitor 9086 is an optimal capacitor and may be omitted in certain embodiments of the present invention. Also, by way of example, this capacitor can be constructed using parasitic capacitance. Examples of parasitic capacitances include the size of a device or component attached to a node or a large number of devices, such as the capacitance of a line or other conductor (eg, long line length), the capacitance of a transistor gate, and the capacitance at the node. Including.

  FIG. 9 shows another example of the present invention when the driver 110 is a variable gain amplifier (VGA). The gain control circuit 91 generates a signal for controlling the gain of the driver. The circuit configuration of FIG. 9 operates similarly and provides the same advantages as the circuit configuration of FIG. However, the embodiment of FIG. 9 has additional features where the gain can be changed using the driver 110.

  This circuit structure can be used when variable gain is required for a particular application. This circuit can also be used for fixed gain applications, but at this time, the gain of the driver 110 is fixed. This allows the circuit to be used in a variety of applications without having to have different components. Also, as radiotelephone standards change and different systems require different gains, the variable gain version of the present invention can be used to accommodate different system specifications without the need for separate components to meet each standard. be able to. For example, the amplifier of the present invention can be electrically programmed by fuses, laser cutting, programmable cells, or other post-fabrication techniques.

  Alternatively, in fixed gain applications, driver 110 can function as a predistorter circuit. The predistorter circuit overemphasizes to compensate for the gain roll off of the main stage amplifier. In general, the gain of the amplifier decreases as the power increases. To compensate for this gain drop in the main stage 120, the driver or predistorter circuit 110 increases its gain as power increases, so the total gain of the circuit configuration (amplifiers 110 and 120) becomes more constant. This increases the linearity of the amplifier, particularly in the high power region. Thus, when using the predistorter 110, this circuitry provides a fixed gain for a wider power range.

  FIG. 9 provides a basic two amplifier embodiment of the present invention. The first stage can be a fixed gain or variable gain amplification stage. The latter can be used as a predistorter. The basic concept is to bypass one or more stages of a multi-stage amplifier to reduce DC current consumption. For example, for an N-stage amplifier, the second stage such as the Nth and (N-1) th can be bypassed using a bypass switching circuit without using any switch. The later stage (eg, Nth) is preferably bypassed to consume more DC current. In the low power mode, the voltage control circuit 90 turns off the main stage. The impedance converter 170 functions as a bypass circuit. The core idea is that this circuit functions as a bypass switching circuit without any expensive switch, which is made by optimizing the impedance matching sections 1, 2, 3 and 4.

  In a particular embodiment, the present invention is a first circuit branch coupled between a first node and a second node, the first circuit branch having N series of amplification stages, where N is It is an integer of 0 or more. The second circuit branch is connected between the second node and the third node, and the second circuit branch has M amplification stages in series, where M is an integer greater than or equal to one. The third circuit branch is connected between the second node and the third node, and the third circuit branch has an impedance converter. During the first operating mode of the circuit, at least one of the M amplification stages of the second part launch is in the off state, so that less power is consumed in the on state and N pieces of the first part launch are consumed. The signal output from the amplifier circuit passes through the third circuit branch. During the second operating mode of the circuit, the M amplification stages of the second circuit branch are in the on state, and the signals output from the N amplification stages of the first branch pass through the second circuit branch. In operation, if N is 0 and M is greater than 1, the bypass circuit bypasses all amplifier stages of the amplifier, which means that there is amplification or not.

  FIG. 10 shows another embodiment of the present invention having two drivers and one power stage. Compared with the embodiment of FIG. 5, the amplifier circuit further includes a second driver 105 controlled by the voltage control circuit 90, and a fifth impedance matching unit 145 located between the second impedance matching unit 140 and the main power stage 120. . The first driver 100 has a fixed gain or a variable gain (or predistorter) like the driver 110 of FIG. The bypass node 72 includes an impedance matching unit (that is, a first impedance matching unit 130, a second impedance matching unit 140, and an impedance conversion unit 170) for each branch. FIG. 11 shows a structure in which the first driver 110 is a variable gain amplifier controlled by a gain control circuit 91. Besides this difference, this circuit operates similarly to the circuit of FIG. During operation of the three stage amplifier, the third (last and main) and second stages are both bypassed, so that only the first stage is always turned on. In this case, when in the low power mode, the voltage control circuit turns off the second stage and the third stage.

  While the circuit of FIG. 10 has a maximum of three gain stages, the circuit of FIG. 5 has a maximum of two gain stages. The bypass path having the impedance converter 170 bypasses the second driver and the main power stage. When in the low power mode, both the second driver and the main power stage are turned off and draw a minimum current. When in the high power mode, the second driver and the main power stage are turned on to provide gain.

  Because there are more gain stages, the circuit of FIG. 10 generally has more gain than the circuit of FIG. Further, since there are more stages in FIG. 10, the degree of freedom in design increases, and the design and use thereof become more flexible. This allows a multi-node amplifier to be designed with techniques such as gallium arsenide versus silicon. Since gallium arsenide technology amplifiers generally provide higher gain, fewer amplification stages are required to obtain the same gain as with technology such as silicon.

  FIG. 12 shows another specific example of the amplifier circuit. This example is similar to FIG. 10, and in this example, there are three amplification stages for increasing the gain. However, the bypass path having the impedance converter bypasses only the main power stage, not the second driver stage as shown in FIG.

  This circuit bypasses only the main power stage instead of the second driver and the main power stage.

  FIG. 13 shows a more detailed circuit diagram of the amplifier circuit of FIG. The details of each block in FIG. 12 are shown in the box indicated by the similar reference number. This detail is similar to that previously described in FIG. 8 except for blocks 85 and 105. In this specific example, the amplifier circuit of the second driver 105 is similar to the amplifier circuit of the main driver, but the transistor size is small. However, as mentioned above, other amplifier circuit designs and structures can be used in any combination for a multimode amplifier.

  FIG. 14 shows an amplifier circuit similar to FIG. 12 in which the driver 110 is a variable gain amplifier or predistorter to provide the advantages described above. FIG. 14 is based on a concept similar to the concept described in FIG. 9, but this concept extends to three stages in FIG.

  FIG. 15 shows various other circuit arrangements for the first impedance matching block 130 and the second impedance matching block 140. Any of these circuits can be replaced with the corresponding block in the multi-mode amplifier circuit described above with reference to FIGS. 5 and 8-14.

  For example, in configuration 15-1, block 130 of the multimode amplifier circuit can be replaced with that shown in box 1605 and block 140 can be replaced with that shown in box 1607. This circuit combination in boxes 1605 and 1607 provides the functionality of the first impedance matching unit and the second impedance matching unit as described above. Configurations 16-2 to 16-9 show other circuit combinations. Any of the other embodiments of this circuit can be used to form the multiple amplifier circuit of the present invention. FIG. 16 merely shows examples of possible circuit combinations, and does not mean exhaustive. Other combinations are possible.

  FIG. 17 shows a variety of different circuit arrangements for the impedance converter block 170. Any of these circuits can be replaced by corresponding blocks in the amplifier circuits of FIGS. 5 and 8-14.

  For example, in configuration 17-1, the block 170 of the multi-mode amplifier circuit can be replaced with that shown in box 1805. The circuitry in box 1805 provides the functionality of the impedance converter described above. Other circuits are shown in configurations 17-2 to 17-8. Any of these other circuit embodiments can be used to form the multimode amplifier circuit of the present invention. FIG. 17 merely shows an example of a possible circuit and does not mean exhaustive. Other circuits are possible.

  FIG. 18 shows a more detailed circuit diagram of FIG. However, the first impedance matching circuit 130 is omitted from the circuit of FIG. Accordingly, impedance converter 170 is directly connected to driver stage amplifier Q5 at node 72. Further, the impedance converter 170 is realized using a single inductor. Thus, the net effect is a reduction in the number of parts, thus reducing the cost of the amplifier module.

  As the example of FIG. 18 shows, it is not necessary to use all of the impedance matching units 130, 140, 150, 160 to implement the inventive concept to implement the amplifier according to the present invention. By optimizing the other impedance matching units 140, 150, 160 and the impedance conversion unit 170, one or more of the impedance matching units can be removed. For example, in one embodiment, the second impedance matching unit 140 can be omitted. In other embodiments, the third impedance matching unit 150 can be omitted. In other embodiments, the fourth impedance matching unit 160 may be omitted. In still other specific examples, any combination of these impedance matching units can be omitted.

  FIG. 19 shows a variety of different circuit arrangements for the voltage control circuit 90. Any of these circuits can be replaced by corresponding blocks in the amplifier circuits of FIGS. 7 and 8-14.

  For example, in configuration 19-1, block 90 of the multimode amplifier circuit can be replaced with that shown in box 1905. The circuitry in box 1905 provides voltage control circuit functionality as described above. Other circuits are shown in configurations 19-2 to 19-4. Any of these other circuit embodiments can be used to form the multiple amplifier circuit of the present invention. FIG. 19 merely shows examples of possible circuits, and does not mean exhaustive. Other circuits are possible.

  FIG. 20 shows a multimode amplifier circuit of the present invention constructed using CMOS technology. This is an embodiment having two stages as shown in FIG. This figure merely shows one embodiment of the present invention, and other embodiments are possible. For example, any of the other circuit configurations for the circuits shown in FIGS. 15 to 17 and 19 can be replaced with the block of FIG.

  FIG. 21 shows a multimode amplifier circuit of the present invention constructed using CMOS technology. This is an embodiment having three stages as shown in FIG. This figure merely shows one embodiment of the present invention, and other embodiments are possible. For example, any of the other circuit configurations for the circuits shown in FIGS. 15 to 17 and 19 can be replaced with the block of FIG.

  FIG. 22 shows a multimode amplifier circuit of the present invention constructed using MESFET technology. This is an embodiment having two stages as shown in FIG. This figure merely shows one embodiment of the present invention, and other embodiments are possible. For example, any of the other circuit configurations for the circuits shown in FIGS. 15 to 17 and 19 can be replaced with the block of FIG.

  FIG. 23 shows a multimode amplifier circuit of the present invention constructed using MESFET technology. This is an embodiment having three stages as shown in FIG. This figure merely shows one embodiment of the present invention, and other embodiments are possible. For example, any of the other circuit configurations for the circuits shown in FIGS. 15 to 17 and 19 can be replaced with the block of FIG.

  FIG. 24 shows an embodiment of the amplifier circuit of FIG. 5 having a bias modulation circuit. FIG. 24 further shows a second voltage control circuit 95 of the bias modulation circuit. Although the bias modulation circuit of this embodiment is shown as a single block, in other embodiments the circuit can be divided into two or more blocks. In order to control the operation of this circuit, a mode control voltage (not shown) is connected to the second voltage control circuit 95. The second voltage control circuit 95 is connected to the driver 100 and the power stage 120. In operation, the mode control voltage controls the operation of the second voltage control circuit 95. In accordance with the mode control voltage, the second voltage control circuit 95 changes the bias of the driver 100 in order to change the operating characteristics and turn the power stage 120 on or off.

  In one embodiment, the mode control voltage and second voltage control circuit 95 is used to change the bias of the driver 100 to reduce the power consumption of the driver 100 used to construct the amplifier. The amplifier has a design or various modes of operation such as Class A, Class AB, Class B and other classes. Because the output transistor draws much power until the amplifier begins to clip, the full class A operation of the amplifier represents high power consumption while being a very linear transmission curve. Thus, Class A amplifiers generate a large amount of heat because they have low distortion and high power consumption. Class B amplifiers have zero reserve current and begin to consume power when there is a signal. Class B amplifiers have good power efficiency and this type of amplifier has significant distortion, especially when compared to A-type amplification.

  The amplifier can operate somewhere between class A and class B, which is known as a class AB amplifier. Class AB amplifiers conduct current for more than half of the input cycle and for smaller cycles. In the present invention, in low power mode, the biasing of an amplifier, such as driver 100, can be altered so that the amplifier saves additional power but at the same time provides good output characteristics. Depending on the number of amplifiers in the circuit, the techniques of the present invention can be used to vary power consumption and gain or degree of amplification.

  For example, in the circuit of FIG. 24, in the high power mode, the power stage 120 is on and the driver 100 is on. In the low power mode, the power stage 120 is off and the driver 100 is on. This is similar to the amplifier circuit of FIG. However, in FIG. 24, the second voltage control circuit 95 can further reduce (for example, reduce) the biasing of the driver 100 to reduce power consumption compared to that of FIG. In other words, the driver 100 is on in both the high power mode and the low power mode, but the driver 100 consumes less power in the low power mode than in the high power mode. This further saves power. This feature of the present invention can be applied to any amplifier in the circuit to obtain additional power savings.

  The bias modulation circuit of the present invention can be added to all power amplification module configurations described in the present invention, ie, embodiments having two stages, three stages, four stages, and N stages. Although FIG. 24 is provided as a simple example to illustrate the concept of the present invention, similar circuitry and techniques can be applied to other power amplification module configurations. For example, a bias modulation circuit can be used in the power amplification module configurations of FIGS. 5, 8 to 14, 18, 20 to 23.

  The second voltage control circuit 95 for bias modulation takes the mode control signal and reduces the bias current to the first stage transistor in the low power mode. The difference between the second voltage control circuit 95 and the voltage control circuit 90 for bias modulation is the fact that the bias control modulation circuit only reduces the bias supply in the low power mode without turning off the bias. Thus, the bias supply to the first stage transistor is reduced in the low power mode to maximize efficiency in the low power mode. Adding this circuit further improves the efficiency in the low power mode.

  FIG. 25 shows a specific example of an amplifier configuration having the three stages of FIG. 12 with amplification bias modulation. In FIG. 12, a switchless switching power amplifier turns off one or more stages when in a low power mode. For example, in the embodiment with three stages of FIG. 12, the voltage control circuit 90 turns off the final stage (power stage 120) when in the low power mode. In the configuration of FIG. 25, an additional bias modulation circuit is included in the second driver 105 so that a reduced bias supply current (zero input current) to the second driver can be applied in the low power mode. In other words, the main transistor is turned off in the low power mode, and the transistor of the second driver is biased at a reduced bias current level (close to class AB and class B). In this way, the efficiency of the low power mode is further improved.

  26A and 26B illustrate the reduced biasing concept of the present invention. In FIG. 26A, the control signal (Vcntr) effectively turns the main stage control circuit on or off, thus reducing the total power consumption when the main stage is off. In the configuration of FIG. 26B, the mode control signal (Vcntr) uses the main stage bias control circuit 90 to turn off the main stage transistor. At the same time, the driver stage control circuit 96 is used to reduce the bias current to the driver transistor. As described above, the circuit configuration in the block 95 is divided into a plurality of blocks. For example, the main stage control circuit may be in a different block from the driver stage control circuit 96.

  FIG. 27 shows a more detailed circuit diagram of a particular embodiment of the bias modulation circuit configuration of FIG. 26B. FIG. 27 shows the details of the control circuit in box 95. Box 95 has a circuit 90 as in FIG. 26A. Further, since the bias modulation circuit for reducing the bias voltage to the transistor of the driver 2 is provided in the box 95, the power consumption in the low power mode is further reduced. There are two voltage levels, namely Vref and VCC, which are also shown as the first constant voltage and the second constant voltage. In operation, depending on the mode control voltage (Vcntr), the main transistor driver is turned on or off, and the second driver transistor is in a specific operating mode, ie, high bias mode or low bias mode, where the high bias mode is low bias Increase amplification at higher power costs in mode. In operation, when the voltage (Vcntr) is increased, the bias voltage at the second driver is decreased. When the voltage (Vcntr) is decreased, the bias voltage at the second driver is increased. Therefore, the bias voltage at the second driver has a negative relationship with Vcntr. However, in other embodiments, the relationship between Vcntr and the second driver can be positive, where increasing Vcntr increases the bias voltage and decreasing Vcntr decreases the bias voltage. 27 shows a common Vcntr signal used in the circuit configurations of the box 90 and the box 96. In other embodiments, this signal is a separate signal.

  FIG. 28 shows four examples of driver stage control circuit configurations. Configuration 28-1 has two resistors or impedances (in addition to the impedance connected to Vcntr) for fine tuning the bias of the second driver. However, only one resistor or impedance such as configuration 28-2 and configuration 28-3 may be required (in addition to the impedance connected to Vcntr). In general, a large number of diodes means a greater voltage or potential difference. Any of these configurations can replace the circuit configuration 96 of FIG.

  FIG. 29A shows a voltage control circuit connected to the amplifier circuit to change the bias voltage. 29B and 29C are graphs showing how R1 or R2 can be used to fine tune the bias supply current to the second driver transistor at the design stage. By using smaller R1 and R2 resistors during design, the quiescent current of the second driver is reduced. The extreme case of this curve is when R1 and R2 are 0, but at this time, the stage of the second driver is almost turned off as in the case of the main stage transistor in the low power mode (the bias of the main stage transistor). See control circuit 90).

  FIG. 30 shows a graph of current change versus output power. This bias modulation concept further reduces the total bias current in the low power mode by reducing the bias current of the second driver. The current reduction is more significant in the actual low power region and is advantageous for certain applications that improve the talk time of CDMA based handsets. In the graph, the solid line is for a power amplifier module (PAM) that is bias modulated to reduce power consumption. The dotted line is for the power amplifier module that only performs switching (ie, to turn off the main amplifier).

  FIG. 31 shows a graph of efficiency (PAE) versus output power. As the current consumption is reduced, the efficiency in the low power mode is further improved. In the graph, the solid line is for a power amplifier module that performs bias modulation to reduce power consumption. The dotted line is for a power amplifier module that only performs switching (ie, to turn off the main amplifier).

  FIG. 32 shows a graph of ACPR versus output power. By further reducing the bias current in the low power mode, it is naturally possible to predict a compromise linearity. However, this result is still within acceptable limits. In other words, it tries to minimize total current consumption by more compromise while maintaining linearity within the limits of the system (eg, CDMA system).

  FIG. 33 shows a graph of gain versus output power. By further reducing the bias current in the low power mode, the bias to the stage of the second driver is almost similar to the case of class B instead of class AB. Of course, the gain expands as the output power increases in a class B amplifier. This graph clearly shows such a gain change in the low power mode. When the total quiescent current is reduced to 10 mA, the gain can be approximately 2 dB. The basic power amplifier configuration (no bias modulation) of the present invention provides a total quiescent current of 22 mA.

  Although specific examples of the present invention have been described for the purpose of illustrating the present invention, the present invention is not limited to the specific forms described above or is exhaustive. Many variations and modifications are possible from the above teachings. Accordingly, the scope of the invention is determined by the claims.

It is a figure which shows the conventional power amplifier for multiple power modes using a bypass switch. It is a figure which shows the conventional power amplifier for multiple power modes using another bypass switch. It is a figure which shows the conventional power amplifier for multiple power modes using the bypass switch connected to the output terminal of (lambda) / 4 bypass transmission line. It is a figure which shows the conventional power amplifier for multiple power modes using the bypass switch connected to the input terminal of (lambda) / 4 bypass transmission line. It is a figure which shows the conventional power amplifier for multiple power modes using another bypass switch. FIG. 3 is a diagram illustrating a highly efficient multiple power mode power amplifier using a power mode transition structure without a bypass switch circuit, according to one embodiment of the present invention. FIG. 6 is a diagram illustrating the high-efficiency multi-power mode power amplifier of FIG. 5 for explaining in detail a power mode transition structure without a bypass switch. 6 is a graph illustrating gain characteristics corresponding to a high power mode and a low power mode of a power amplifier for a plurality of power modes according to an example of the present invention. 3 is a graph illustrating power added efficiency (PAE) characteristics corresponding to a high power mode and a low power mode of a power amplifier for a multiple power mode according to an embodiment of the present invention. FIG. 4 shows a more detailed circuit diagram of an embodiment having two stages of a power amplifier for multiple power modes. It is a figure which shows the other specific example of the power amplifier for multiple power modes in case a driver is a variable gain amplifier (VGA) or a predistorter circuit. It is a figure which shows the other specific example of the power amplifier for multiple power modes which has three stages, two drivers, and one power stage. It is a figure which shows the other specific example of the power amplifier for multiple power modes which has three stages in case one driver is a variable gain amplifier or a predistorter circuit among drivers. It is a figure which shows the other specific example of the power amplifier for multiple power modes which has three stages in which an impedance converter bypasses only a main power stage. FIG. 13 shows a more detailed circuit diagram of the amplifier circuit of FIG. It is a figure which shows the other specific example of the amplifier circuit of FIG. 12 in case one driver is a variable gain amplifier or a predistorter circuit among drivers. It is a figure which shows the various different circuit structure with respect to a 1st impedance matching part and a 2nd impedance matching part. It is a figure which shows the various different circuit structure with respect to a 3rd impedance matching part and a 4th impedance matching part. It is a figure which shows the various different circuit structure with respect to an impedance converter. Fig. 15 shows a more detailed circuit diagram of the embodiment of the amplifier circuit of Fig. 14; It is a figure which shows the various different circuit structure of a voltage control circuit. It is a figure which shows the multi-mode amplifier circuit which has the two stages of this invention comprised using CMOS technology. It is a figure which shows the multi-mode amplifier circuit which has the three stages of this invention comprised using CMOS technology. It is a figure which shows the multi-mode amplifier circuit which has the two stages of this invention comprised using the MESFET technique. It is a figure which shows the multi-mode amplifier circuit which has the three stages of this invention comprised using the MESFET technique. FIG. 6 is a diagram illustrating an embodiment of the amplifier circuit of FIG. 5 having a bias modulation circuit configuration. FIG. 13 illustrates a specific example of an amplifier configuration having the three stages of FIG. 12 with amplification bias modulation. FIG. 4 is a diagram illustrating a reduced bias supply concept of the present invention. FIG. 4 is a diagram illustrating a reduced bias supply concept of the present invention. FIG. 26B is a more detailed circuit diagram of the configuration of FIG. 26B. It is a figure which shows four examples of a driver stage control circuit structure. FIG. 3 shows a voltage control circuit connected to an amplifier driver for changing the bias voltage. 6 is a graph showing how R1 or R2 can be used to finely tune the bias supply current to the transistor of the second driver at the design stage. 6 is a graph showing how R1 or R2 can be used to finely tune the bias supply current to the transistor of the second driver at the design stage. 6 is a graph of current change versus output power. FIG. 6 is a graph of efficiency (PAE) versus output power. It is a graph of ACPR versus output power. It is a graph of gain versus output power.

Explanation of symbols

90 Applied Voltage Control Circuit 100 Driver 120 Power Stage 130 First Impedance Matching Unit 140 Second Impedance Matching Unit 150 Third Impedance Matching Unit 160 Fourth Impedance Matching Unit 170 Impedance Converter

Claims (127)

A first circuit branch connected between the first node and the second node and comprising a first amplification stage;
A second circuit branch connected between the second node and the third node, wherein the first impedance matching unit and the second amplification stage are connected in series;
A third circuit branch connected between the second node and the third node and including an impedance converter;
During the first operating mode of the circuit, the second amplification stage is in an off state and consumes less power in the on state, and the signal output from the first amplification stage substantially passes through the third circuit branch. Pass through
An integrated circuit, wherein the second amplification stage is in an ON state during the second operation mode of the circuit, and a signal output from the first amplification stage substantially passes through the second circuit branch.   The integrated circuit according to claim 1, wherein a gain of the first amplification stage is variable.   The integrated circuit according to claim 1, wherein a gain of the first amplification stage is fixed.   The integrated circuit of claim 1, wherein the first amplification stage includes a predistorter circuit.   The integrated circuit according to claim 1, wherein the first amplification stage includes a gain characteristic for compensating for nonlinearity of the gain characteristic of the second amplification stage.   2. The integrated circuit according to claim 1, wherein after passing through the first amplification stage and the second amplification stage, the gain characteristic of the circuit is more linear than the gain characteristic of the second amplification stage. .   The integrated circuit of claim 1, wherein the first circuit branch, the second circuit branch, and the third circuit branch are formed on a single semiconductor substrate.   The integrated circuit further includes a voltage control circuit coupled to the second amplification stage, and the voltage control circuit supplies a signal to the second amplification stage in accordance with a mode control voltage to cause the second amplification stage to operate. 2. The integrated circuit according to claim 1, wherein the integrated circuit is set to an on state or an off state. The integrated circuit further includes a voltage control circuit coupled to the first amplification stage and the second amplification stage,
The voltage control circuit supplies a first signal to the first amplification stage according to a mode control voltage to adjust a bias of the first amplification stage, and during the first operation mode, the bias of the first amplification stage is Reduced compared to the bias of the first amplification stage during the second operation mode;
2. The voltage control circuit according to claim 1, wherein the voltage control circuit supplies a second signal to the second amplification stage according to the mode control voltage to set the second amplification stage to an on state or an off state. Integrated circuit. The integrated circuit further includes a voltage control circuit coupled to the first amplification stage and the second amplification stage,
The voltage control circuit supplies a first signal to the first amplification stage according to a mode control voltage to adjust a bias current of the first amplification stage. During the first operation mode, the voltage control circuit The bias current is reduced compared to the bias current of the first amplification stage during the second operation mode,
2. The voltage control circuit according to claim 1, wherein the voltage control circuit supplies a second signal to the second amplification stage according to the mode control voltage to set the second amplification stage to an on state or an off state. Integrated circuit. A first circuit branch connected between the first node and the second node, wherein the first amplification stage and the second amplification stage are connected in series;
A second circuit branch connected between the second node and the third node, wherein the first impedance matching unit and the third amplification stage are connected in series;
A third circuit branch connected between the second node and the third node and including an impedance converter;
During the first operation mode of the circuit, the third amplification stage is in an off state and consumes less power in the on state, and a signal output from the first amplification stage is the second amplification stage and the third amplification stage. Go through the circuit branch,
In the second operation mode of the circuit, the third amplification stage is in an on state, and a signal output from the first amplification stage passes through the second amplification stage and the second circuit branch. Integrated circuit.   12. The integrated circuit according to claim 11, wherein the gain of the first amplification stage is variable.   The integrated circuit according to claim 11, wherein a gain of the first amplification stage is fixed.   The integrated circuit of claim 11, wherein the first amplification stage includes a predistorter circuit.   12. The integrated circuit according to claim 11, wherein the first amplification stage includes a gain characteristic for compensating for nonlinearity of the gain characteristic of the second amplification stage and the third amplification stage.   12. The gain characteristic of the circuit is more linear than the gain characteristic of the third amplification stage after passing through the first amplification stage, the second amplification stage, and the third amplification stage, respectively. An integrated circuit according to 1.   The integrated circuit of claim 11, wherein the first circuit branch, the second circuit branch, and the third circuit branch are formed on a single semiconductor substrate.   The integrated circuit further includes a voltage control circuit coupled to the third amplification stage, and the voltage control circuit supplies a signal to the third amplification stage in accordance with a mode control voltage, thereby causing the third amplification stage to operate. The integrated circuit according to claim 11, wherein the integrated circuit is set to an on state or an off state. The integrated circuit further includes a voltage control circuit coupled to the first amplification stage, the second amplification stage, and the third amplification stage;
The voltage control circuit supplies a first signal to the first amplification stage or the second amplification stage according to a mode control voltage to adjust a bias of the first amplification stage or the second amplification stage, and During one operation mode, the bias of the first amplification stage or the second amplification stage is reduced compared to the bias of the first amplification stage or the second amplification stage during the second operation mode;
12. The voltage control circuit according to claim 11, wherein the voltage control circuit supplies a second signal to the third amplification stage according to the mode control voltage to set the third amplification stage to an on state or an off state. Integrated circuit. The integrated circuit further includes a voltage control circuit coupled to each of the first amplification stage, the second amplification stage, and the third amplification stage,
The voltage control circuit adjusts a bias current of the first amplification stage or the second amplification stage by supplying a first signal to the first amplification stage or the second amplification stage according to a mode control voltage, During the first operation mode, the bias current of the first amplification stage or the second amplification stage is reduced compared to the bias current of the first amplification stage or the second amplification stage during the second operation mode;
12. The voltage control circuit according to claim 11, wherein the voltage control circuit supplies a second signal to the third amplification stage according to the mode control voltage to set the third amplification stage to an on state or an off state. Integrated circuit. A first transistor coupled between the input node and the first node;
A first circuit block connected between the first node and the second node;
A second circuit block connected between the second node and the third node;
A second transistor connected between the third node and the fourth node;
A third circuit block connected between the fourth node and the fifth node;
A fourth circuit block connected between the second node and the fifth node;
In the first operation mode, a signal supplied to the input node passes through the first transistor, the first circuit block, and the fourth circuit block.
In the second operation mode, the signal supplied to the input node passes through the first transistor, the first circuit block, the second circuit block, the second transistor, and the third circuit block. Integrated circuit. The fourth circuit block includes
An inductance device coupled between the second node and the sixth node;
A capacitor connected between the sixth node and the fifth node;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
A capacitor connected between the second node and the sixth node;
An inductance device coupled between the sixth node and the fifth node;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
A first capacitor connected between the second node and the sixth node;
An inductance device coupled between the sixth node and the fifth node;
A second capacitor coupled between the sixth node and a reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the second node and the sixth node;
A first capacitor connected between the sixth node and the fifth node;
A second capacitor coupled between the sixth node and a reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the second node and the fifth node;
A capacitor connected between the second node and the fifth node;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the second node and the fifth node;
A first capacitor coupled between the second node and a reference voltage level;
A second capacitor coupled between the fifth node and the reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the second node and the fifth node;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The third circuit block is
An inductance device coupled between the fourth node and the fifth node;
A capacitor coupled between the fourth node and a reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The third circuit block is
A first capacitor coupled between the fourth node and a reference voltage level;
A first inductance device coupled between the fourth node and the reference voltage level;
A second inductance device connected between the fourth node and the fifth node;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide, and the second inductance device includes an inductor, a wire The integrated circuit according to claim 21, comprising at least one of bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. The third circuit block is
A first inductance device coupled between the fourth node and a reference voltage level;
A first capacitor coupled between the fourth node and the reference voltage level;
A second inductance device connected between the fourth node and the fifth node;
A second capacitor device coupled between the fifth node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide, and the second inductance device includes an inductor, a wire The integrated circuit according to claim 21, comprising at least one of bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. The third circuit block is
A first inductance device coupled between the fourth node and a reference voltage level;
A second inductance device connected between the fourth node and the fifth node;
A first capacitor coupled between the fifth node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, or a coplanar waveguide, and the second inductance device includes an inductor, a wire The integrated circuit according to claim 21, comprising at least one of bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. The third circuit block is
A first capacitor coupled between the fourth node and a reference voltage level;
A first inductance device coupled between the fourth node and the fifth node;
A second inductance device coupled between the fifth node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide, and the second inductance device includes an inductor, a wire The integrated circuit according to claim 21, comprising at least one of bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. The first circuit block includes a first capacitor connected between the first node and the second node;
The integrated circuit of claim 21, wherein the second circuit block includes a second capacitor connected between the second node and the third node.   The first circuit block does not include a passive element connected between the first node and the second node, and the second circuit block includes a second element connected between the second node and the third node. The integrated circuit of claim 21, comprising two capacitors. The first circuit block further includes an inductance device and a third capacitor connected in series between the first node and a reference voltage level.
35. The integrated circuit of claim 34, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   The integrated circuit of claim 36, wherein the inductance device is further coupled to a supply voltage level. The second circuit block further includes an inductance device connected between the second node and a reference voltage level;
35. The integrated circuit of claim 34, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   37. The integrated circuit of claim 36, wherein the second circuit block further includes an inductance device connected between the second node and a reference voltage level. The second circuit block further includes an inductance device connected between the third node and a reference voltage level;
35. The integrated circuit of claim 34, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   35. The integrated circuit of claim 34, wherein the second circuit block further includes a third capacitor connected between the second node and a reference voltage level. The first circuit block includes an inductance device connected between the first node and a reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The second circuit block includes
A first capacitor connected between the second node and the sixth node;
An inductance device coupled between the sixth node and a reference voltage level;
A second capacitor connected between the sixth node and the third node;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. .   The integrated circuit further includes a voltage control circuit coupled to the second transistor, and the voltage control circuit supplies a control signal to the second transistor according to a mode control voltage to turn on the second transistor. The integrated circuit according to claim 21, wherein the integrated circuit is set to an off state.   45. The voltage control circuit of claim 44, wherein the voltage control circuit includes a third transistor connected between the second transistor and a reference voltage level, and an electrode of the third transistor is connected to a voltage control line. Integrated circuit.   The voltage control circuit includes a third transistor connected between the second transistor and a reference voltage level, and a fourth transistor connected between a supply voltage line and a reference voltage level. 45. The integrated circuit of claim 44, wherein the integrated circuit is connected to a connection point of the fourth transistor toward a supply voltage line, and an electrode of the fourth transistor is connected to a voltage control line.   The voltage control circuit includes a third transistor connected between the second transistor and a reference voltage level, and a fourth transistor connected between an electrode of the third transistor and a supply voltage line. 45. The integrated circuit of claim 44, wherein the electrodes of the first transistor are connected to the fourth transistor, and the electrodes of the large four transistors are connected to a voltage control line.   The integrated circuit further includes a voltage control circuit connected to the first transistor, and the voltage control circuit supplies a signal to the first transistor according to the mode control voltage to adjust a bias of the first transistor. 23. The integrated circuit of claim 21, wherein the bias of the first transistor decreases during the first operation mode as compared to the bias of the first transistor during the second operation mode.   The voltage control circuit includes a third transistor connected to the first transistor via a resistor and connected to a reference voltage level via a resistor, and an electrode of the third transistor is connected to a voltage control line. 49. The integrated circuit of claim 48.   The voltage control circuit includes a third transistor connected to the first transistor and connected to a reference voltage level through a resistor, and an electrode of the third transistor is connected to a voltage control line. 49. An integrated circuit according to claim 48.   The voltage control circuit includes a third transistor connected to the first transistor through a resistor and connected to a reference voltage level, and an electrode of the third transistor is connected to a voltage control line. 49. An integrated circuit according to claim 48. The voltage control circuit includes:
A third transistor;
Resistance,
One or more level transfer diodes connected in series with the resistor,
The resistor and the one or more level transfer diodes are connected in series to the first transistor;
The third transistor is coupled to the resistor and the one or more level transfer diodes and to a reference voltage level;
49. The integrated circuit of claim 48, wherein an electrode of the third transistor is connected to a voltage control line.   The first transistor or the second transistor includes a bipolar junction transistor, a heterojunction bipolar transistor, a field effect transistor, a complementary metal oxide semiconductor transistor, a metal oxide semiconductor transistor, a p-type metal oxide semiconductor transistor, and an n-type metal oxide. The integrated circuit of claim 21, wherein the integrated circuit is a film semiconductor transistor, a high electron mobility transistor, or a metal semiconductor field effect transistor. A first transistor coupled between the input node and the first node;
A matching circuit block connected between the first node and the second node;
A second transistor connected between the second node and a third node;
A first circuit block connected between the third node and the fourth node;
A second circuit block connected between the fourth node and the fifth node;
A third transistor connected between the fifth node and the sixth node;
A third circuit block connected between the sixth node and the seventh node;
A fourth circuit block connected between the fourth node and the seventh node;
In the first operation mode, the signal supplied to the input node passes through the first transistor, the matching circuit block, the second transistor, the first circuit block, and the fourth circuit block.
In the second operation mode, the signal supplied to the input node is the first transistor, the matching circuit block, the second transistor, the first circuit block, the second circuit block, the third transistor, and the third transistor. An integrated circuit characterized by passing through a circuit block. The fourth circuit block includes
An inductance device coupled between the fourth node and the eighth node;
A capacitor connected between the eighth node and the seventh node;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fourth circuit block includes
A capacitor connected between the fourth node and the eighth node;
An inductance device coupled between the eighth node and the seventh node;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fourth circuit block includes
A first capacitor connected between the fourth node and the eighth node;
An inductance device coupled between the eighth node and the seventh node;
A second capacitor coupled between the eighth node and a reference voltage level;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the fourth node and the eighth node;
A first capacitor connected between the eighth node and the seventh node;
A second capacitor coupled between the eighth node and a reference voltage level;
The integrated circuit of claim 21, wherein the inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the fourth node and the seventh node;
A capacitor connected between the fourth node and the seventh node;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the fourth node and the seventh node;
A first capacitor coupled between the fourth node and a reference voltage level;
A second capacitor coupled between the seventh node and the reference voltage level;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fourth circuit block includes
An inductance device coupled between the second node and the fifth node;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The third circuit block is
An inductance device coupled between the sixth node and the seventh node;
A capacitor coupled between the sixth node and a reference voltage level;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The third circuit block is
A first capacitor coupled between the sixth node and a reference voltage level;
A first inductance device coupled between the sixth node and the reference voltage level;
A second inductance device connected between the sixth node and the seventh node;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, or a coplanar waveguide,
55. The device of claim 54, wherein the second inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. Integrated circuit. The third circuit block is
A first inductance device coupled between the sixth node and a reference voltage level;
A first capacitor coupled between the sixth node and the reference voltage level;
A second inductance device coupled between the sixth node and the seventh node;
A second capacitor coupled between the seventh node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, or a coplanar waveguide,
55. The device of claim 54, wherein the second inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. Integrated circuit. The third circuit block is
A first inductance device coupled between the sixth node and the reference voltage level;
A second inductance device coupled between the sixth node and the seventh node;
A first capacitor coupled between the seventh node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, or a coplanar waveguide,
55. The device of claim 54, wherein the second inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. Integrated circuit. The third circuit block is
A first capacitor coupled between the sixth node and a reference voltage level;
A first inductance device coupled between the sixth node and the seventh node;
A second inductance device coupled between the seventh node and the reference voltage level;
The first inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, or a coplanar waveguide,
55. The device of claim 54, wherein the second inductance device includes at least one of an inductor, wire bonding, a transmission line, a microstrip line, a strip line, a coaxial cable, and a coplanar waveguide. Integrated circuit. The first circuit block includes a first capacitor connected between the third node and the fourth node;
55. The integrated circuit of claim 54, wherein the second circuit block includes a second capacitor connected between the fourth node and the fifth node.   The first circuit block does not include a passive element connected between the third node and the fourth node, and the second circuit block is connected between the fourth node and the fifth node. 55. The integrated circuit of claim 54, comprising a second capacitor. The first circuit block further includes an inductance device and a third capacitor connected in series between the third node and a reference voltage level,
68. The integrated circuit of claim 67, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   70. The integrated circuit of claim 69, wherein the inductance device is further coupled to a supply voltage level. The second circuit block further includes an inductance device connected between the fourth node and a reference voltage level;
68. The integrated circuit of claim 67, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   70. The integrated circuit of claim 69, wherein the second circuit block further includes an inductance device connected between the fourth node and the reference voltage level. The second circuit block further includes an inductance device connected between the fifth node and a reference voltage level;
68. The integrated circuit of claim 67, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   68. The integrated circuit of claim 67, wherein the second circuit block further includes a third capacitor connected between the fourth node and the reference voltage level. The first circuit block includes an inductance device connected between the third node and a reference voltage level;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The second circuit block includes
A first capacitor connected between the fourth node and the eighth node;
An inductance device coupled between the eighth node and a reference voltage level;
A second capacitor connected between the eighth node and the fifth node;
55. The integrated circuit of claim 54, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   The integrated circuit further includes a voltage control circuit connected to the third transistor, and the voltage control circuit supplies a control signal to the third transistor according to a mode control voltage to turn on the third transistor. The integrated circuit according to claim 54, wherein the integrated circuit is set to an off state.   78. The voltage control circuit of claim 77, wherein the voltage control circuit includes a fourth transistor connected between the third transistor and a reference voltage level, and an electrode of the fourth transistor is connected to a voltage control line. Integrated circuit. The voltage control circuit includes:
A fourth transistor coupled between the third transistor and a reference voltage level;
A fifth transistor coupled between the supply voltage line and the reference voltage level;
The electrode of the fourth transistor is connected to a point connecting the fifth transistor and the supply voltage line;
78. The integrated circuit of claim 77, wherein the electrode of the fifth transistor is connected to a voltage control line. The voltage control circuit includes:
A fourth transistor coupled between the third transistor and a reference voltage level;
A fifth voltage transistor connected between a supply voltage line and an electrode of the fourth transistor;
78. The integrated circuit of claim 77, wherein the electrode of the fifth transistor is connected to a voltage control line. The integrated circuit further includes a voltage control circuit coupled to the first transistor or the second transistor,
The voltage control circuit adjusts the first transistor or the second transistor by supplying a signal to the first transistor or the second transistor according to a node control voltage. During the first operation mode, the voltage control circuit 55. The integrated circuit of claim 54, wherein a bias of the transistor or the second transistor is reduced compared to a bias of the first transistor or the second transistor during the second operation mode.   The voltage control circuit includes a fourth transistor connected to the first transistor or the second transistor via a resistor and connected to a reference voltage level via a resistor, and the electrode of the fourth transistor is a voltage control line. 82. The integrated circuit of claim 81, wherein the integrated circuit is coupled to the circuit.   The voltage control circuit includes a fourth transistor connected to the first transistor or the second transistor and connected to a reference voltage level through a resistor, and an electrode of the fourth transistor is connected to a voltage control line. 84. The integrated circuit of claim 81.   The voltage control circuit includes a fourth transistor connected to the first transistor or the second transistor through a resistor and connected to a reference voltage level, and an electrode of the fourth transistor is connected to a voltage control line. 84. The integrated circuit of claim 81. The voltage control circuit includes:
A fourth transistor;
Resistance,
One or more level transfer diodes connected in series with the resistor,
The resistor and the one or more level transfer diodes are connected in series to the first transistor or the second transistor;
The fourth is coupled to the resistor and the one or more level transfer diodes and to a reference voltage level;
The integrated circuit of claim 81, wherein the electrode of the fourth transistor is connected to a voltage control line.   The first transistor, the second transistor, or the third transistor is a bipolar junction transistor, a heterojunction bipolar transistor, a field effect transistor, a complementary metal oxide semiconductor transistor, a metal oxide semiconductor transistor, or a p-type metal oxide semiconductor transistor. 55. The integrated circuit of claim 54, wherein the integrated circuit is an n-type metal oxide semiconductor transistor, a high electron mobility transistor, or a metal semiconductor field effect transistor. In integrated circuits,
A first circuit branch connected between the first node and the second node and comprising N (an integer greater than or equal to 0) serial amplification stages;
A second circuit branch connected between the second node and the third node and comprising M (an integer greater than or equal to 1) serial amplification stages;
A third circuit branch connected between the second node and the third node and including an impedance converter;
During the first operating mode of the circuit, at least one of the M amplification stages of the second branch is in an off state and consumes less power in the on state, and N in the first branch The signals output from the amplification stages pass through the third circuit branch,
During the second operation mode of the circuit, the M amplification stages of the second circuit branch are in an on state, and signals output from the N amplification stages of the first branch pass through the second circuit branch. An integrated circuit characterized by that.   88. The integrated circuit of claim 87, wherein a gain of at least one amplification stage among the N amplification stages of the first branch is variable.   88. The integrated circuit of claim 87, wherein a gain of at least one amplification stage among the N amplification stages of the first branch is fixed.   88. The integrated circuit of claim 87, wherein at least one of the N amplification stages of the first branch includes a predistorter circuit.   At least one of the N amplification stages of the first branch is used to compensate for nonlinearity in the gain characteristic of at least one of the M amplification stages of the second branch. 90. The integrated circuit of claim 87 including a gain characteristic.   88. The integrated circuit of claim 87, wherein after passing through the first branch and the second branch, the gain characteristic of the circuit is more linear than the gain characteristic of the second branch.   88. The integrated circuit of claim 87, wherein the first circuit branch, the second circuit branch, and the third circuit branch are formed on a single semiconductor substrate.   The integrated circuit further includes a voltage control circuit coupled to the at least one amplification stage among the M amplification stages of the second branch, and the voltage control circuit includes the second control circuit according to a mode control voltage. A control signal is supplied to the at least one amplification stage among the M amplification stages of the branch, and the at least one amplification stage is set to the on state or the off state among the M amplification stages of the second branch. 90. The integrated circuit of claim 87. The integrated circuit includes a voltage control circuit coupled to at least one of the N amplification stages of the first branch and the at least one of the M amplification stages of the second branch. Further including
The voltage control circuit supplies a first signal to the at least one amplification stage among the N amplification stages of the first branch according to the mode control voltage, and among the N amplification stages of the first branch, The bias of the at least one amplification stage is adjusted, and during the first operation mode, the bias of the at least one amplification stage among the N amplification stages of the first branch is the second operation mode during the second operation mode. Reduced compared to the bias of the at least one amplification stage among the N amplification stages of one branch,
The voltage control circuit supplies a second signal to the at least one amplification stage among the M amplification stages of the second branch in accordance with the mode control voltage, so that the M amplification stages of the second branch. 88. The integrated circuit of claim 87, wherein the at least one amplification stage is set to an on state or an off state. The integrated circuit includes a voltage control circuit coupled to at least one of the N amplification stages of the first branch and the at least one of the M amplification stages of the second branch. Further including
The voltage control circuit supplies a first signal to the at least one amplification stage among the N amplification stages of the first branch according to the mode control voltage, and among the N amplification stages of the first branch, The bias current of the at least one amplification stage is adjusted, and during the first operation mode, the bias current of the at least one amplification stage among the N amplification stages of the first branch is in the second operation mode. Of the N amplification stages of the first branch, reduced compared to the bias current of the at least one amplification stage;
The voltage control circuit supplies a second signal to the at least one amplification stage among the M amplification stages of the second branch in accordance with the mode control voltage, so that the M amplification stages of the second branch. 88. The integrated circuit of claim 87, wherein the at least one amplification stage is set to an on state or an off state.   The voltage control circuit includes a transistor connected between the at least one amplification stage and a reference voltage level among the M amplification stages of the second branch, and an electrode of the transistor is connected to a voltage control line. 95. The integrated circuit of claim 94.   The voltage control circuit includes a first transistor coupled between the at least one amplification stage of the M amplification stages of the second branch and a reference voltage level, and a first transistor coupled between a supply voltage line and the reference voltage level. The electrode of the first transistor is connected to a connection point of the second transistor to the supply voltage line, and the electrode of the second transistor is connected to a voltage control line. 95. The integrated circuit according to Item 94.   The voltage control circuit is connected between the at least one amplification stage and a reference voltage level among the M amplification stages of the second branch, and connected between a supply voltage line and the first transistor. 95. The integrated circuit of claim 94, further comprising: a second transistor, wherein an electrode of the first transistor is coupled to the second transistor, and an electrode of the second transistor is coupled to a voltage control line. circuit.   The integrated circuit further includes a voltage control circuit coupled to the at least one amplification stage among the N amplification stages of the first branch, and the voltage control circuit is configured to output the first control circuit according to the mode control voltage. A signal is supplied to the at least one amplification stage among the N amplification stages of one branch to adjust a bias of the at least one amplification stage among the N amplification stages of the first branch, and During one operation mode, the bias of the at least one amplification stage among the N amplification stages of the first branch is the at least one of the N amplification stages of the first branch during the second operation mode. 88. The integrated circuit of claim 87, wherein the integrated circuit is reduced compared to two amplification stages.   The voltage control circuit includes a transistor coupled to the at least one amplification stage among the N amplification stages of the first branch through a resistor and coupled to a reference voltage level through a resistor. 101. The integrated circuit of claim 100, wherein the electrodes of the three transistors are connected to a voltage control line.   The voltage control circuit includes a transistor coupled to the at least one amplification stage among the N amplification stages of the first branch and coupled to a reference voltage level through a resistor, and the electrode of the third transistor 101. The integrated circuit of claim 100, wherein is coupled to a voltage control line.   The voltage control circuit includes a transistor connected to the at least one amplification stage among the N amplification stages of the first branch through a resistor and connected to a reference voltage level. 101. The integrated circuit of claim 100, coupled to a control line. The voltage control circuit includes:
A transistor,
Resistance,
One or more level transfer diodes connected in series with the resistor,
The resistor and the one or more level shift diodes are connected in series to the at least one amplification stage among the N amplification stages of the first branch;
The transistor is coupled to the resistor and the one or more level transfer diodes and to a reference voltage level;
The integrated circuit of claim 100, wherein the electrode of the transistor is connected to a voltage control line.   The integrated circuit does not have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. An integrated circuit as described.   The first branch, the second branch and the third branch have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. The integrated circuit of claim 1, wherein the integrated circuit is not.   The integrated circuit does not have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. An integrated circuit as described.   The first branch, the second branch and the third branch have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. The integrated circuit of claim 11, wherein the integrated circuit is not.   88. The integrated circuit does not have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. An integrated circuit as described.   The first branch, the second branch and the third branch have a bypass switch including any of a relay, a micromachined switch, a transistor switch, a PIN diode switch, or a Schottky diode switch. 90. The integrated circuit of claim 87, wherein:   The integrated circuit of claim 21, further comprising a fifth circuit block connected between the fifth node and the sixth node.   The integrated circuit of claim 111, wherein the fifth circuit block includes a capacitor connected between the fifth node and the sixth node. The fifth circuit block includes
An inductance device coupled between the fifth node and the sixth node;
A capacitor coupled between the sixth node and a reference voltage level;
112. The integrated circuit of claim 111, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block includes
An inductance device connected between the fifth node and the seventh node;
A first capacitor coupled between the seventh node and a reference voltage level;
A second capacitor connected between the seventh node and the sixth node;
112. The integrated circuit of claim 111, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   The fifth circuit block includes an inductance device and a capacitor connected in series between the fifth node and the sixth node. The inductance device includes an inductor, a wire bonding, a transmission line, a microstrip line, a strip line, and a coaxial line. 112. The integrated circuit of claim 111, comprising at least one of a cable or a coplanar waveguide. The fifth circuit block includes
A first capacitor coupled between the fifth node and a reference voltage level;
An inductance device coupled between the fifth node and the sixth node;
A second capacitor coupled between the sixth node and a reference voltage level;
112. The integrated circuit of claim 111, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block is
A capacitor connected between the fifth node and a reference voltage level;
An inductance device connected between the fifth node and the sixth node;
112. The integrated circuit of claim 111, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   55. The integrated circuit of claim 54, further comprising a fifth circuit block connected between the seventh node and the eighth node.   119. The integrated circuit of claim 118, wherein the fifth circuit block includes a capacitor connected between the seventh node and the eighth node. The fifth circuit block is
An inductance device connected between the seventh node and the eighth node;
A capacitor coupled between the eighth node and a reference voltage level;
119. The integrated circuit of claim 118, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block includes
An inductance device connected between the sixth node and the ninth node;
A first capacitor coupled between the ninth node and a reference voltage level;
A second capacitor connected between the ninth node and the eighth node;
119. The integrated circuit of claim 118, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block includes an inductance device and a capacitor connected in series between the seventh node and the eighth node;
119. The integrated circuit of claim 118, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block includes
A first capacitor coupled between the seventh node and a reference voltage level;
An inductance device coupled between the seventh node and the eighth node;
A second capacitor coupled between the eighth node and a reference voltage level;
119. The integrated circuit of claim 118, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. . The fifth circuit block includes
A capacitor coupled between the seventh node and a reference voltage level;
An inductance coupled between the seventh node and the eighth node;
119. The integrated circuit of claim 118, wherein the inductance device comprises at least one of an inductor, wire bonding, transmission line, microstrip line, strip line, coaxial cable, or coplanar waveguide. .   88. The integrated circuit of claim 87, wherein N is 0, 1, 2, 3, 4 or 5.   88. The integrated circuit of claim 87, wherein M is 2, 3, 4 or 5. 88. The integrated circuit of claim 87, wherein N is 0, 1, 2, 3, 4 or 5, and M is 2, 3, 4 or 5.

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