JP2005079320A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the potential of a fixed potential insulating electrode is not stable depending on a connection state, especially the off-operation of a semiconductor device has a problem, although the fixed potential insulating electrode and a metal layer are subjected to ohmic contact in a conventional semiconductor device. <P>SOLUTION: In the semiconductor device, a projecting region 16 is formed at the connection region of the fixed potential insulating electrode 5 connected to a metal layer, and a region for ohmic contact is increased. As a result, the ohmic contact properties between the fixed potential insulating electrode and the metal layer are improved, and the fixed potential insulating electrode is grounded reliably. Accordingly, the breaking properties of a channel region 8 are improved, and the off-operation of the semiconductor region is stabilized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The semiconductor device of the present invention relates to an element that improves ohmic connectivity between a fixed potential insulating electrode formed of polycrystalline silicon and a metal layer.

  In a conventional semiconductor device, an element structure that is normally off-type, excellent in controllability, low on-resistance, improved switching speed and operation reliability, and further miniaturized and high withstand voltage is known. (For example, refer to Patent Document 1).

  An example of the structure of a conventional semiconductor device is shown with reference to FIGS. FIG. 9A is a perspective view of the element, and FIG. 9B is a top view. 10A is a cross-sectional view in the DD line direction of FIG. 9B, and FIG. 10B is a cross-sectional view in the EE line direction of FIG. 9B.

  First, as shown in FIG. 9A, in the conventional semiconductor device, an N + type semiconductor substrate 51 and an N− type epitaxial layer 52 are formed on the N + type semiconductor substrate 51. An N + type source region 54 and a trench 57 are formed in the N− type epitaxial layer 52 so as to be orthogonal to each other. The trench 57 is formed with an insulating film 56 and a fixed potential insulating electrode 55 made of high-concentration P + type polycrystalline silicon (polysilicon) so as to cover the inner wall thereof. The fixed potential insulating electrode 55 and the source region 54 are, for example, in ohmic contact with an aluminum (Al) layer 61 (see FIG. 10), and both potentials are fixed to the same potential. The epitaxial layer 52 is mainly used as the drain region 53, and a region sandwiched between the fixed potential insulating electrodes 55 of the epitaxial layer 52 is referred to as a channel region 58.

  The fixed potential insulating electrode 55 is high-concentration P + type polysilicon, and the source region 54 formed on the surface of the channel region 58 and the fixed potential insulating electrode 55 are kept at the same potential via the Al layer 61. Therefore, a depletion layer is formed in the channel region 58 from the surrounding fixed potential insulating electrode 55 due to a work function difference. A potential barrier against conduction electrons is formed in the channel region 58, and the source region 54 and the drain region 53 are electrically cut off from the beginning.

  Next, as shown in FIG. 9B, the fixed potential insulating electrode 55 has a stripe shape, and both ends thereof are in contact with the P-type gate region 59. A gate electrode G is formed on the surface of the gate region 59 and supplies free carriers (holes) from the gate region 59 to the drain region 53. In addition, the channel region 58 surrounded by the fixed potential insulating electrodes 55 forms one unit cell. Note that the shape of the fixed potential insulating electrode 55 and the shape of the source region 54 constituting the unit cell are arbitrary as long as the condition that the current can be interrupted or the amount of current can be controlled depending on the channel state.

As shown in FIG. 10A, H2 is called a channel thickness and L2 is called a channel length. That is, the channel thickness H2 is the distance between the insulating films 56 facing each other in the channel region, and the channel length L2 is the distance from the bottom surface of the source region 54 to the bottom surface of the fixed potential insulating electrode 55 along the side wall of the groove. Say distance. An Al layer 60 is formed on the back surface of the substrate 51.
Japanese Patent Laid-Open No. 11-40802 (pages 13-14, FIGS. 16-17)

  As described above, in a conventional semiconductor device, a positive high voltage is applied to the drain electrode D, the source electrode S is grounded, the gate electrode G is grounded, or a negative voltage is applied to the gate electrode G. Is applied to perform the OFF operation. In this semiconductor device OFF operation, the channel region 58 becomes a pseudo P-type region due to a work function difference between the N-type channel region 58 and the P-type fixed potential insulating electrode 55. As a result, a positive high voltage is applied to the drain region 53 and the channel region 58 is grounded, so that the channel region 58 serving as a pseudo P-type region and the drain region 3 of the N-type region are reversely biased. The semiconductor device is turned off.

  On the other hand, in order to turn on the semiconductor device, a positive voltage is applied to the gate electrode G, free carriers (holes) are injected from the gate region 59, and the channel region 58 is changed to an N-type region. In the channel region 58 and the drain region 53, conductivity is modulated by the injected free carriers (holes), and a low resistance state is achieved. That is, since the semiconductor device performs the ON operation and the OFF operation by free carriers (holes) injected from the gate region 59, the direct current signal amplification factor is increased by the amount of free carriers (holes) injected from the gate region 59. It depends.

  However, in the conventional semiconductor device, as shown in FIGS. 10A and 10B, the connection surface of the fixed potential insulating electrode 55 that is in ohmic contact with the Al layer 61 is formed to be substantially flat. Yes. If the ohmic connectivity between the fixed potential insulating electrode 55 made of polysilicon and the Al layer 61 is not good, the fixed potential insulating electrode 55 floats. As a result, the fixed potential insulating electrode 55 cannot be kept at the same potential as the potential of the source electrode S, and the OFF operation of the semiconductor device, that is, the blocking property by the depletion layer in the channel region 58 is deteriorated. there were.

  The present invention is a semiconductor device that improves the ohmic connectivity between a fixed potential insulating electrode and an Al layer, wherein a protruding region is formed on the connection surface of the fixed potential insulating electrode, and the contact area between the fixed potential insulating electrode and the Al layer is increased. The purpose is to improve the ohmic connectivity between the two and increase the fixed potential insulating electrode more reliably at the same potential as the source region.

  The present invention has been made in view of the above circumstances, and in the semiconductor device of the present invention, the semiconductor device is substantially parallel to each other at an equal interval with the one-conductivity-type semiconductor layer constituting the drain region. A plurality of trenches formed from the surface of the layer, and a fixed potential insulating electrode made of reverse-conductivity-type polycrystalline silicon having an insulating film formed on the inner wall of the trench and filling the trench so as to cover the insulating film; A source region of one conductivity type located between the trenches and maintained at the same potential as the fixed potential insulating electrode, spaced from the source region, and disposed so that at least a part of the insulating film is adjacent to the source region. A gate region located between the fixed potential insulating electrodes and at least a channel region located below the source region, and the polycrystalline silicon has an ohmic contact with the metal layer on the surface thereof. It continued, and the connection surface of the polycrystalline silicon is characterized in that it has a projection area. Therefore, in the semiconductor device of the present invention, by forming a protruding region on the connection surface of the fixed potential insulating electrode made of polycrystalline silicon, the connection area between the fixed potential insulating electrode and the metal layer is increased, and the ohmic connectivity is improved. Can be made.

  In the semiconductor device of the present invention, the polycrystalline silicon in the projecting region and in the vicinity of the projecting region contains an oxidizing substance. Therefore, in the semiconductor device of the present invention, the protrusion region is formed on the connection surface of the fixed potential insulating electrode by utilizing the etching rate difference between the region containing the oxidizing substance and the region not containing the oxide substance.

  In the method for manufacturing a semiconductor device of the present invention, a step of forming a semiconductor layer of one conductivity type, and forming a plurality of trenches from the surface of the semiconductor layer so as to be substantially parallel to each other at an equal interval, Forming an oxide film so as to cover an inner wall of the trench; depositing a plurality of layers of polycrystalline silicon in the trench; etching the polycrystalline silicon; depositing the polycrystalline silicon in the trench It has the process of forming a protrusion area | region on an upper surface. Therefore, in the method for manufacturing a semiconductor device of the present invention, multilayer polycrystalline silicon can be etched back to form a projection region on the surface of the polycrystalline silicon in the trench formation region.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the polycrystalline silicon, a first layer of polycrystalline silicon is deposited in the trench, and the first layer of polycrystalline silicon is reversely conductive. After introducing the impurity of the type, the second layer of polycrystalline silicon is deposited. Therefore, in the method for manufacturing a semiconductor device of the present invention, impurities are introduced into the first layer of polycrystalline silicon, and the introduced impurities diffuse into the second layer of polycrystalline silicon. The heat treatment time for this can be shortened.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the protruding region, the protruding region is formed by using an etching rate difference between the region having the silicon oxide film and the region made of polycrystalline silicon. It is characterized by that. Therefore, in the method for manufacturing a semiconductor device of the present invention, the protrusion region is formed by using the etching rate difference between the region containing the oxide film and the region not containing the oxide film in the first and second polycrystalline silicon. Can do.

  As described above, first, in the semiconductor device of the present invention, the fixed potential insulating electrode is in ohmic contact with the metal layer on the surface thereof. A projecting region is formed on the connection surface of the fixed potential insulating electrode, and the projecting region is also in ohmic contact with the metal layer. Thus, in the semiconductor device of the present invention, the connection area between the fixed potential insulating electrode and the metal layer can be increased, and the ohmic contact property can be improved. As a result, in the semiconductor device of the present invention, the fixed potential insulating electrode is surely grounded, so that the semiconductor device can be turned off more reliably.

  Second, in the method for manufacturing a semiconductor device of the present invention, multiple layers of polycrystalline silicon are stacked in a trench, and a silicon oxide film is formed on the boundary surface. Then, when the fixed potential insulating electrode is formed in the trench, the polycrystalline silicon is etched back. In the present invention, the region containing the polycrystalline silicon and the silicon oxide film are included in the etching back. The difference in etching rate is used. Accordingly, in the present invention, a protruding region can be formed on the connection surface of the fixed potential insulating electrode.

  Thirdly, in the method for manufacturing a semiconductor device of the present invention, after depositing the first layer of polycrystalline silicon, a P-type impurity is introduced and diffused. Thereafter, a second layer of polycrystalline silicon is stacked. As a result, in the second layer of polycrystalline silicon, impurities can be diffused using the first layer of polycrystalline silicon as a diffusion source. As a result, it is not necessary to thermally diffuse the first-layer polycrystalline silicon from the surface of the second-layer polycrystalline silicon, and the diffusion time can be greatly shortened, so that the heat treatment can be rationalized.

  Fourth, in the method of manufacturing a semiconductor device of the present invention, as described in the third effect, after introducing a P-type impurity into the first layer of polycrystalline silicon, the second layer of polycrystalline silicon is used. To deposit. As a result, the P-type impurity concentration of polycrystalline silicon in the vicinity of the oxide film formed on the inner wall of the trench can be increased in the fixed potential insulating electrode that is important for forming a blocking state in the channel region. As a result, the depletion layer is reliably formed, and the semiconductor device can be turned off more reliably.

  Fifth, in the semiconductor device manufacturing method of the present invention, as described in the third effect, the heat treatment time can be shortened by reducing the diffusion depth in the polycrystalline silicon. As a result, in the heat treatment process using the fixed potential insulating electrode, diffusion of the diffusion regions constituting the source region and the gate region can be suppressed, so that element miniaturization can be realized.

  Hereinafter, an embodiment of a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS.

  First, the semiconductor device of this embodiment will be described below with reference to FIGS.

  1A is a perspective view showing the structure of the semiconductor device of the present invention, and FIG. 1B is a top view showing the structure of the semiconductor device of the present invention. As shown in FIG. 1A, an N− type epitaxial layer 2 is deposited on an N + type semiconductor substrate 1. In the epitaxial layer 2, a plurality of trenches 7 are formed from the surface of the epitaxial layer 2 at equal intervals and parallel to each other. The substrate 1 is used as a drain extraction region, and the epitaxial layer 2 is mainly used as a drain region 3. Further, the trench 7 is etched so that the side wall thereof is substantially perpendicular to the surface of the epitaxial layer 2, and the insulating film 6 is formed on the inner wall thereof. Further, for example, polycrystalline silicon into which a P-type impurity is introduced is deposited in the trench 7. As will be described in detail later, the polycrystalline silicon in the trench 7 is electrically connected to the source region 4 via, for example, aluminum (Al) on the surface of the epitaxial layer 2. Thus, the P-type polycrystalline silicon in the trench 7 is used as the fixed potential insulating electrode 5 having the same potential as the source electrode S. On the other hand, the epitaxial layer 2 located between the plurality of trenches 7 is used as the channel region 8.

  As shown in FIGS. 1A and 1B, in this embodiment, a plurality of gate regions 9 are provided at a certain interval in the epitaxial layer 2 that is separated from the source region 4 and is in contact with the insulating film 6. It has been. As shown in the figure, one source region 4 is formed between two gate regions 9 extending in the longitudinal direction of the gate region 9, that is, in the Y-axis direction and forming one cell. . In the present embodiment, the source region 4 is positioned substantially parallel to the gate region 9 in the Y-axis direction, and is disposed at an equal distance from each gate region 9. On the other hand, the trench 7 forming the fixed potential insulating electrode 5 is formed to extend in a direction orthogonal to the source region 4 and the gate region 9, that is, in the X-axis direction. Then, both ends of the trench 7 overlap the gate region 9 and a part of the formation region, respectively, and the trench 7 is formed between the gate regions 9 at a constant interval in the Y-axis direction.

  Next, the cross-sectional structure and operation of the semiconductor device of the present invention will be described with reference to FIG. 2A is a cross-sectional view taken along line AA in FIG. 1B, and FIG. 2B is a cross-sectional view taken along line BB in FIG. 1B.

  As shown in FIG. 2A, with respect to the epitaxial layer 2, the region mainly located below the source region 4 and surrounded by the trench 7 is the channel region 8, the arrow H1 is the channel thickness, and the arrow L1 is the channel. Long. That is, the channel thickness H1 is the distance between the insulating films 6 facing each other in the channel region 8, and the channel length L1 is from the bottom surface of the source region 4 to the bottom surface of the fixed potential insulating electrode 5 along the sidewall of the trench 7. The distance. Further, for example, an Al layer 10 is in ohmic contact with the back surface of the N + type substrate 1 used as a drain extraction region, and a drain electrode D is formed through the Al layer 10.

  On the other hand, although not shown in FIG. 2A, a silicon oxide film 12 as an insulating layer is formed on the surface of the epitaxial layer 2. The Al layer 11 is in ohmic contact with the source region 4 through a contact region 13 (see FIG. 2B) provided in the silicon oxide film 12. The Al layer 11 is also in ohmic contact with the fixed potential insulating electrode 5 through the contact region 13. With this structure, as described above, the fixed potential insulating electrode 5 is grounded, and the source region 4 and the fixed potential insulating electrode 5 are kept at the same potential. In addition, the channel region 8 located substantially below the source region 4 is also maintained at the same potential as the fixed potential insulating electrode 5. In the semiconductor device of the present embodiment, the conduction and interruption of the main current are controlled by the depletion layer formed in the channel region 8, so that the fixed potential insulating electrode 5 constituting the unit cell is satisfied if the condition is satisfied. The shape and the shape of the source region 4 are arbitrary.

  As shown in FIG. 2B, a silicon oxide film 12 is deposited on the surface of the epitaxial layer 2 including on the gate region 9. A gate electrode G made of, for example, Al is formed on the gate region 9 via a contact region 14 provided in the silicon oxide film 12. The broken line in the figure indicates the presence of the fixed potential insulating electrode 5. As shown in the drawing, the corners of the insulating film 6 in the cross-sectional view and the surface view are drawn with a square shape, but these are schematic views and may be rounded in practice. That is, it is widely adopted to round these corners in order to suppress electric field concentration.

  FIG. 3A is a cross-sectional view of a fixed potential insulated electrode which is a semiconductor device of the present invention, and FIG. 3B is a perspective view of the fixed potential insulated electrode.

  As shown in FIG. 3A, in the present embodiment, there is a protruding region 16 on the connection surface of the fixed potential insulating electrode 5 that is in ohmic contact with the Al layer 11. A method for forming the protrusion region 16 will be described later in the method for manufacturing a semiconductor device. As shown in FIG. 3B, the protrusion region 16 is formed in parallel with the extending direction of the trench. In the region exposed from the contact region 13 (see FIG. 2B), the protruding regions 16 are formed in two rows substantially parallel to the connection surface of the fixed potential insulating electrode 5. As described above, the fixed potential insulating electrode 5 is in ohmic contact with the Al layer 11 (see FIG. 2A), but the protruding region 16 formed on the connection surface thereof is also in ohmic contact with the Al layer 11. In the connection region of the fixed potential insulating electrode 5, the contact area between the Al layer 11 and the fixed potential insulating electrode 5 can be increased by arranging the protruding region 16.

  Specifically, in the present embodiment, the polycrystalline silicon constituting the fixed potential insulating electrode 5 has a laminated structure, and the projection region 16 is formed on the boundary surface of the polycrystalline silicon and the region in the vicinity thereof. A silicon oxide film 17 is formed on the boundary surface, and the thickness of the silicon oxide film 17 is, for example, about 5 to 20 mm. With this structure, the silicon oxide film 17 is contained in the polycrystalline silicon in the lower portion where the projection region 16 and the projection region 16 are formed. In the present embodiment, the protruding region 16 is formed by the difference in etching rate between the region containing the silicon oxide film 17 and the region made of polycrystalline silicon.

  In other words, in the present embodiment, in the connection region of the fixed potential insulating electrode 5, the contact area with the Al layer 11 is increased by the protruding region 16, so that the fixed potential insulating electrode 5 can be securely connected as in the source region 4. Can be grounded. Although described below with reference to FIG. 4, in the semiconductor device of the present embodiment, the source region 4 and the fixed potential insulating electrode 5 are set to the same potential, and the channel region 8 and the fixed potential insulating electrode 5 are substantially By keeping the same potential, ON operation and OFF operation are controlled. In the present embodiment, the fixed potential insulating electrode 5 can be more reliably grounded by improving the ohmic contact property between the Al layer 11 and the fixed potential insulating electrode 5. As a result, in the semiconductor device of the present embodiment, as described above, the ON operation and the OFF operation can be reliably performed, and in particular, the blocking property by the depletion layer of the channel region 8 in the OFF operation can be improved.

  Further, in the present embodiment, by arranging the protruding region 16 in the connection region with the Al layer 11, the ohmic contact property can be improved even for polycrystalline silicon formed in the trench 7 having a fine width. Furthermore, miniaturization of the element can be realized.

  In this embodiment, the case where the silicon oxide film 17 is disposed on the boundary surface of the stacked polycrystalline silicon is shown in FIGS. 3A and 3B. It is presumed that the oxide film 17 is mixed with the surrounding polycrystalline silicon.

  Next, the operation principle of the semiconductor element of the present invention will be described.

  First, the OFF operation of the semiconductor element will be described. As described above, the current path of the semiconductor element includes the N + type substrate 1 serving as the drain extraction region, the drain region 3 including the N− type epitaxial layer 2, the N− type channel region 8 positioned between the trenches 7, and And an N + type source region 4. That is, all the regions are composed of N-type regions. At first glance, when a positive voltage is applied to the drain electrode D and the source electrode S is operated in a grounded state, it seems that the OFF operation cannot be performed. .

  However, as described above, the N-type region composed of the source region 4 and the channel region 8 and the P-type region which is the fixed potential insulating electrode 5 are connected via the Al layer 11 and have the same potential. Therefore, in the channel region 8 around the fixed potential insulating electrode 5, a depletion layer spreads so as to surround the fixed potential insulating electrode 5 due to a work function difference between the P + type polysilicon and the N− type epitaxial layer 2. That is, by adjusting the width between the trenches 7 forming the fixed potential insulating electrode 5, that is, the channel thickness H1, the channel region 8 is filled with the depletion layers extending from the fixed potential insulating electrodes 5 on both sides. Although details will be described later, the channel region 8 filled with the depletion layer is a pseudo P-type region.

  With this structure, the N− type drain region 3 and the N + type source region 4 can be separated by a PN junction by the channel region 8 which is a pseudo P type region. That is, the semiconductor device of the present invention is in the cutoff state (OFF state) from the beginning by forming a pseudo P-type region in the channel region 8. In addition, when the semiconductor device is OFF, a positive voltage is applied to the drain electrode D, the source electrode S is grounded, and the gate electrode G is in a ground state, or a negative potential is applied to the gate electrode G. ing. At this time, a depletion layer is formed on the boundary surface between the channel region 8 which is a pseudo P-type region and the drain region 3 which is an N-type region by applying a reverse bias to the lower surface of the drawing. The formation state of this depletion layer affects the breakdown voltage characteristics of the semiconductor device.

  Here, the pseudo P-type region described above will be described below with reference to FIG. FIG. 4A shows an energy band diagram in the channel region 8 when OFF, and FIG. 4B schematically shows a depletion layer formed in the channel region 8 when OFF. The P + type polysilicon region which is the fixed potential insulating electrode 5 and the N− type epitaxial layer 2 region which is the channel region 8 are opposed to each other via the insulating film 6. Both are maintained at the same potential through the Al layer 11 on the surface of the epitaxial layer 2. As a result, a depletion layer is formed around the trench 7 due to the work function difference between the two, and a P-type region is formed by a small number of free carriers (holes) slightly present in the depletion layer.

  Specifically, when the P + type polysilicon region and the N− type epitaxial layer 2 region are set to the same potential via the Al layer 11, an energy band diagram is formed as shown in FIG. First, in the P + type polysilicon region, the valence band is formed with a negative slope at the interface of the insulating film 6, and the interface of the insulating film 6 has high potential energy for free carriers (holes). Show. That is, free carriers (holes) in the P + type polysilicon region cannot exist at the interface of the insulating film 6 and are driven away from the insulating film 6. As a result, negative charges composed of ionized acceptors are left behind at the interface of the insulating film 6 in the P + type polysilicon region. A negative charge composed of an ionized acceptor exists at the interface of the insulating film 6 in the P + type polysilicon region. As a result, in the N− type epitaxial layer 2 region, a negative charge consisting of this ionization acceptor and a positive charge consisting of an ionized donor pairing with it are required. For this reason, the channel region 8 is depleted from the interface of the insulating film 6.

However, since the impurity concentration of the channel region 8 is about 1E14 (/ cm ³ ) and the thickness is about 0.8 to 1.4 μm, the channel region 8 is completely a depletion layer extending from the fixed potential insulating electrode 5. Will be occupied. Actually, since the positive charge enough to balance with the ionization acceptor cannot be secured only by forming the channel region 8 into a depletion layer, a small number of free carriers (holes) also exist in the channel region 8. As a result, as shown in the figure, the ionized acceptor in the P + type polysilicon region and the free carriers (holes) or ionized donors in the N− type epitaxial layer 2 form a pair to form an electric field. As a result, the depletion layer formed from the interface of the insulating film 6 becomes a P-type region, and the channel region 8 filled with this depletion layer becomes a P-type region.

  Next, a state where the semiconductor element changes from the OFF operation to the ON operation will be described. First, a positive voltage is applied to the gate electrode G from the ground state. At this time, free carriers (holes) are introduced from the gate region 9, but as described above, the free carriers (holes) are attracted by the ionization acceptor and flow into the interface of the insulating film 6. Then, free carriers (holes) are filled in the interface of the insulating film 6 in the channel region 8 so that only an ionization acceptor and free carriers (holes) in the P + type polysilicon region are paired to form an electric field. As a result, free carriers (electrons) are present from the region farthest from the insulating film 6 in the channel region 8, that is, from the central region of the channel region 8, and a neutral region appears. As a result, the depletion layer in the channel region 8 is reduced, the channel is opened from the central region, free carriers (electrons) move from the source region 4 to the drain region 3, and a main current flows.

  That is, free carriers (holes) instantaneously spread through the wall surface of the trench 7, the depletion layer extending from the fixed potential insulating electrode 5 to the channel region 8 recedes, and the channel opens. Further, when a voltage higher than a predetermined value is applied to the gate electrode G, the PN junction formed by the gate region 9, the channel region 8 and the drain region 3 becomes a forward bias. Free carriers (holes) are directly injected into the channel region 8 and the drain region 3. As a result, a large number of free carriers (holes) are distributed in the channel region 8 and the drain region 3, whereby conductivity modulation occurs, and the main current flows with a low on-resistance.

  Finally, a state where the semiconductor element turns from ON to OFF will be described. In order to turn off the semiconductor element, the potential of the gate electrode G is set to the ground state (0 V) or a negative potential. Then, a large amount of free carriers (holes) present in the drain region 3 and the channel region 8 disappear or are excluded from the device through the gate region 9. As a result, the channel region 8 is again filled with the depletion layer, becomes a pseudo P-type region again, maintains the breakdown voltage, and the main current stops.

  Next, with reference to FIGS. 5 to 8, a method for manufacturing the semiconductor device of the present embodiment will be described below. In the following description, the same components as those described in the structure of the semiconductor device shown in FIG.

First, FIG. 5 is a cross-sectional view taken along the line C-C in FIG. 1B, and a P-type diffusion region constituting the gate region 9 is formed. An N + type semiconductor substrate 1 is prepared, and the substrate 1 is placed on a susceptor of an epitaxial growth apparatus. Then, a high temperature of, for example, about 1000 ° C. is given to the substrate 1 by lamp heating, and SiH ₂ Cl ₂ gas and H ₂ gas are introduced into the reaction tube. As a result, an N− type epitaxial layer 2 is grown on the substrate 1.

Then, a P type diffusion region constituting the gate region 9 is formed. On the surface of the epitaxial layer 2, a silicon oxide film having an opening provided in a portion where a P-type diffusion region is formed is formed by a known photolithography technique as a selection mask. Then, a P-type impurity such as boron (B) is ion-implanted and diffused at an acceleration voltage of 60 keV and an introduction amount of about 5.0 × 10 ¹⁵ / cm ² .

Next, FIG. 6 is a cross-sectional view taken along the line AA in FIG. 1B, in which an N-type diffusion region constituting the source region 4 is formed. On the surface of the epitaxial layer 2, a photoresist having an opening provided in a portion where an N + type diffusion region is formed is formed by a known photolithography technique as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted and diffused at an acceleration voltage of 120 keV and an introduction amount of about 5.0 × 10 ¹⁵ / cm ² . Thereafter, the photoresist is removed.

  Next, FIG. 7 is a cross-sectional view in the AA direction of FIG. 1B, in which a trench 7 is formed and polycrystalline silicon is laminated. First, as shown in FIG. 7A, a silicon oxide film (not shown) is deposited on the entire surface of the epitaxial layer 2. Then, the silicon oxide film is selectively removed so that an opening is provided in a portion where the trench 7 is formed by a known photolithography technique. Then, for example, the trench 7 is formed from the surface of the epitaxial layer 2 by completely anisotropic dry etching. Thereafter, the silicon oxide film used as a mask is removed, and then the silicon surface is thermally oxidized to form an insulating film 6 on the silicon surface.

  Next, for example, a first layer of polycrystalline silicon 21 is deposited on the upper surface of the epitaxial layer 2 and the inner wall of the trench 7 by, for example, a CVD method. In this step, the first-layer polycrystalline silicon 21 is deposited from the insulating film 6 on the inner wall of the trench 7 so as to have a thickness of about 5000 mm, for example. Thereafter, a large amount of P-type impurity such as boron (B) is introduced into the polycrystalline silicon 21 and diffused.

  Next, as shown in FIG. 7B, for example, a second layer of polycrystalline silicon 22 is deposited on the upper surface of the first layer of polycrystalline silicon 21 in which boron (B) is diffused by CVD. For example, about 14000 mm is deposited.

  At this time, in the present embodiment, boron (B) is introduced and diffused into the first layer of polycrystalline silicon 21, and the second layer of polycrystalline silicon 22 is deposited by the CVD method. The substrate 1 is moved between the respective apparatuses between the processes. During this movement, the first layer of polycrystalline silicon 21 is exposed to the atmosphere, and a silicon oxide film 17 made of a thin film having a thickness of about 5 to 20 mm is formed on the surface thereof. That is, the second-layer polycrystalline silicon 22 is formed so as to cover the silicon oxide film 17 formed on the surface of the first-layer polycrystalline silicon 21. In the present embodiment, the case where the silicon oxide film 17 is formed to have a thickness of about 5 to 20 mm has been described. However, the present invention is not limited to this case. In the present embodiment, any P-type impurity, which will be described later, can be employed as long as it has a thickness enough to diffuse into the second-layer polycrystalline silicon 22.

  As a result, the first-layer polycrystalline silicon 21 and the second-layer polycrystalline silicon 22 are formed on the upper surface of the substrate 1 including the inside of the trench 7 through the silicon oxide film 17 in a two-layer stacked structure. It is formed.

  In the present embodiment, after the first-layer polycrystalline silicon 21 is stacked, a P-type impurity, for example, boron (B) is introduced and diffused, and the second-layer so as to cover the upper surface thereof. The polycrystalline silicon 22 is laminated. As a result, in the second-layer polycrystalline silicon 22, the impurity introduction step can be omitted, and P-type impurities such as boron (B) are diffused using the first-layer polycrystalline silicon 21 as a diffusion source. be able to.

  Further, in the present embodiment, a P-type impurity, for example, boron (B) is introduced and diffused into the polycrystalline silicon in the trench 7, but the impurity is introduced after the first-layer polycrystalline silicon 21 is stacked. And diffuse. Therefore, it is not necessary to introduce a P-type impurity such as boron (B) from the upper surface of the second-layer polycrystalline silicon 22 and diffuse it into the first-layer polycrystalline silicon 21. As a result, the heat treatment time for diffusing impurities in the first and second layers of polycrystalline silicon 21 and 22 can be shortened. Further, by shortening the heat treatment time, the spread of the diffusion regions such as the source region 4 and the gate region 9 can be suppressed, so that element miniaturization can be realized.

  Further, in the present embodiment, by introducing a P-type impurity such as boron (B) into the first-layer polycrystalline silicon 21, the vicinity of the oxide film 6 due to the blocking property of the channel region 8 is achieved. The polycrystalline silicon can be a high concentration region. As a result, a depletion layer can be reliably formed from the fixed potential insulating electrode 5 during the OFF operation of the semiconductor device, so that the blocking property in the channel region 8 can be improved.

Next, FIG. 8 is a cross-sectional view in the AA direction of FIG. 1 (B). As shown in the figure, the surface of the second-layer polycrystalline silicon 22 is etched back to form the fixed potential insulating electrode 5. . In the present embodiment, first, for example, dry etching using an SF ₆ + He-based etchant is performed, and then dry etching using an HBr + HCl-based etchant is performed, whereby the first and second polycrystalline silicon 21 , 22 are selectively removed.

At this time, in this embodiment, first, the above-described SF ₆ + He-based etchant is used to etch back for a certain period of time, and then an endpoint detection type etch-back is performed using an HBr + HCl-based etchant. The etch back using the SF ₆ + He-based etchant aims to shorten the etching time. In the etch-back using the HBr + HCl-based etchant, the protruding region 16 is formed in addition to the end point detection. In particular, when an HBr + HCl-based etchant is used, polycrystalline silicon is etched back by about 3000 mm per minute and the silicon oxide film is etched back by about 120 mm per minute.

  In the present embodiment, due to this etchant characteristic, there is a difference in the etching rate between the region containing the silicon oxide film 17 and the region consisting only of the polycrystalline silicon 21 and 22. For example, with respect to the above-described HBr + HCl-based etchant, the etching rate of the region containing the silicon oxide film 17 is about 120 mm, while the etching rate of the region made of polycrystalline silicon is about 3000 mm. As a result, in this embodiment, the etch back of the region containing the silicon oxide film 17 is delayed due to the above-described difference in the etching rate, and the projection region 16 is formed on the surface of the fixed potential insulating electrode 5.

Thereafter, the P-type impurity introduced into the first layer of polycrystalline silicon 21 is diffused into the second layer of polycrystalline silicon 22 by using a thermal diffusion process in a later step, and fixed potential insulation is performed. Distributed throughout the electrode 5. Then, impurities are introduced into the first layer of polycrystalline silicon 21 so that the impurity concentration in the polycrystalline silicon constituting the fixed potential insulating electrode 5 is, for example, about 1.0E20 (/ cm ³ ). Is done. In this embodiment, since the thickness of the silicon oxide film 22 is about 5 to 20 mm, the impurity diffuses from the first-layer polycrystalline silicon 21 to the second-layer polycrystalline silicon 22. To do.

  Thereafter, Al layers 10, 11, 15, silicon oxide film layer 12, contact regions 13, 14 and the like are formed, and the semiconductor device shown in FIGS. 1 and 2 is completed.

  In the present embodiment, for example, the case where the fixed potential insulating electrode has a two-layer structure with a silicon oxide film interposed therebetween is described, but it is not necessary to limit to this case. For example, it is possible to form a multi-layer structure of polycrystalline silicon, form a silicon oxide film on the boundary surface, and form a plurality of protruding regions. In this embodiment mode, the trench is formed after the source region and the gate region are formed. However, the present invention is not limited to this case. For example, the gate region and the source region may be formed after the trench is formed.

  Furthermore, in this embodiment, it is not necessary to limit to the structure of the semiconductor device described above. For example, in a vertical MOS transistor, even when polycrystalline silicon is deposited in a trench to form a gate electrode, a similar effect can be obtained by forming a protruding region in a region where the gate electrode is in ohmic contact with the metal layer. Can be obtained. The same applies to the IGBT element. In addition, various modifications can be made without departing from the scope of the present invention.

1A is a perspective view and FIG. 2B is a top view for explaining a semiconductor device of the present invention. 1A and 1B are a cross-sectional view and a cross-sectional view for explaining a semiconductor device of the present invention. It is (A) sectional drawing and (B) perspective view for demonstrating the semiconductor device of this invention. 2A is an energy band diagram for explaining a semiconductor device of the present invention, and FIG. 2B is a diagram for explaining a channel region at OFF. FIG. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is (A) sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention, (B) sectional drawing. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. It is (A) perspective view and (B) top view for demonstrating the conventional semiconductor device. It is (A) sectional drawing and (B) sectional drawing for demonstrating the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Epitaxial layer 3 Drain region 4 Source region 5 Fixed potential insulation electrode 6 Insulating film 7 Trench 8 Channel region 9 Gate region 10 Al layer 11 Al layer 12 Silicon oxide film 13 Contact region 14 Contact region 15 Al layer 16 Protrusion region 17 Silicon oxide film 21 First layer polycrystalline silicon 22 Second layer polycrystalline silicon

Claims (12)

A semiconductor layer of one conductivity type constituting the drain region;
A plurality of trenches formed from the surface of the semiconductor layer so as to be substantially parallel to each other at regular intervals;
An insulating film is formed on the inner wall of the trench, and a fixed potential insulating electrode made of reverse conductivity type polycrystalline silicon filling the trench so as to cover the insulating film,
A source region of one conductivity type located between the trenches and maintained at the same potential as the fixed potential insulating electrode;
A gate region that is spaced apart from the source region and is disposed adjacent to at least the insulating film and a portion thereof;
A channel region located between the fixed potential insulating electrodes and at least below the source region;
The polycrystalline silicon is in ohmic contact with a metal layer on the surface thereof, and the connection surface of the polycrystalline silicon has a protruding region. 2. The semiconductor device according to claim 1, wherein the polycrystalline silicon in the projecting region and a region near the projecting region contains an oxidizing substance. The semiconductor device according to claim 2, wherein the polycrystalline silicon has a two-layer stacked structure with the oxide material interposed therebetween. 4. The semiconductor device according to claim 2, wherein the oxide material is a silicon oxide film. A semiconductor layer to be an element formation region;
A current passing region and a control region exposed on the main surface of the semiconductor layer;
A metal layer in ohmic contact with each of the current passing region and the control region on the main surface;
2. The semiconductor device according to claim 1, wherein the control region is made of polycrystalline silicon, and a connection region of the polycrystalline silicon has a protruding region. 6. The semiconductor device according to claim 5, wherein the control region is formed by depositing the polycrystalline silicon in a trench formed from a main surface of the semiconductor layer. The semiconductor device according to claim 5, wherein the polycrystalline silicon in the projecting region and a region near the projecting region contains an oxidizing substance. Forming a semiconductor layer of one conductivity type;
Forming a plurality of trenches from the surface of the semiconductor layer so as to be substantially parallel to each other at regular intervals, and forming an oxide film so as to cover an inner wall of the trench;
Depositing multiple layers of polycrystalline silicon on the trench;
A method of manufacturing a semiconductor device, comprising: etching the polycrystalline silicon to form a protruding region on the upper surface of the polycrystalline silicon deposited in the trench. In the step of forming the polycrystalline silicon, a first layer of polycrystalline silicon is deposited in the trench, an impurity of a reverse conductivity type is introduced into the first layer of polycrystalline silicon, and then the second layer is formed. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the polycrystalline silicon is deposited. 10. The method of manufacturing a semiconductor device according to claim 8, wherein a silicon oxide film having a thickness of 5 to 20 mm is formed on the surface of the first layer of polycrystalline silicon. 11. The semiconductor according to claim 10, wherein in the step of forming the protruding region, the protruding region is formed using an etching rate difference between the region having the silicon oxide film and the region made of polycrystalline silicon. Device manufacturing method. Connecting the surface of the polycrystalline silicon filling the trench and the surface of the source region of one conductivity type with a metal layer,
12. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the metal layer, the protruding region and the metal layer are ohmically connected.

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