JP2005072414A - Wiring board for incorporating component and manufacturing method thereof - Google Patents

Wiring board for incorporating component and manufacturing method thereof Download PDF

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Publication number
JP2005072414A
JP2005072414A JP2003302391A JP2003302391A JP2005072414A JP 2005072414 A JP2005072414 A JP 2005072414A JP 2003302391 A JP2003302391 A JP 2003302391A JP 2003302391 A JP2003302391 A JP 2003302391A JP 2005072414 A JP2005072414 A JP 2005072414A
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wiring board
conductive
component
conductive layer
electronic component
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JP4279089B2 (en
Inventor
Satoshi Shibazaki
聡 柴崎
Tatsuro Imamura
達郎 今村
Kenji Sasaoka
賢司 笹岡
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Dai Nippon Printing Co Ltd
DT Circuit Technology Co Ltd
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Dai Nippon Printing Co Ltd
DT Circuit Technology Co Ltd
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Priority to JP2003302391A priority Critical patent/JP4279089B2/en
Priority to US10/530,518 priority patent/US7242591B2/en
Priority to KR1020057005949A priority patent/KR101046077B1/en
Priority to PCT/JP2003/012749 priority patent/WO2004034759A1/en
Publication of JP2005072414A publication Critical patent/JP2005072414A/en
Priority to US11/785,607 priority patent/US7345888B2/en
Priority to US12/007,924 priority patent/US7644497B2/en
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Abstract

<P>PROBLEM TO BE SOLVED: To further improve component packaging density without losing reliability in a wiring board for incorporating components and to provide its manufacturing method. <P>SOLUTION: First, a core-wiring board having a conductive layer at least on both upper and lower surfaces is manufactured, a nearly circular through hole is formed on the core-wiring board that is manufactured to generate space for positioning electric/electronic components to be incorporated, a conductive layer is formed so that the inner surface of the formed through hole is included, the conductive layer on the upper and lower surfaces is subjected to patterning, the conductive layer formed at the through hole is divided according to the number of terminals of the electric/electronic components, the electric/electronic components are positioned at the space, the terminal of the positioned electric/electronic components and the divided conductive layer are connected by a conductive member, and then an insulating layer is laminated and formed overlapping on both the upper and lower surfaces of the core-wiring board, where the electric/electronic components are connected by the conductive wiring, so that the periphery of the electric/electronic components is filled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、部品内蔵配線板の製造方法および部品内蔵配線板に係り、特に、さらなる部品実装密度向上に適する部品内蔵配線板の製造方法および部品内蔵配線板に関する。   The present invention relates to a method for manufacturing a component built-in wiring board and a component built-in wiring board, and more particularly, to a method for manufacturing a component built-in wiring board suitable for further improvement in component mounting density and a component built-in wiring board.

近年、エレクトロニクス技術が進展し電子機器や通信機器が高機能化され、かつ小型化も進んでいる。このような状況で配線板への例えば半導体の実装では、実装密度を向上するためパッケージ実装によらないベアチップ実装法が実用化されてきている。また、コンデンサや抵抗などの受動部品では、チップ実装型のものが、0.6mm×0.3mm(0603)のサイズまで小型化している。   In recent years, electronic technology has advanced, electronic devices and communication devices have become highly functional, and miniaturization has also progressed. In such a situation, for example, semiconductor mounting on a wiring board, a bare chip mounting method not using package mounting has been put into practical use in order to improve mounting density. In addition, passive components such as capacitors and resistors are downsized to a size of 0.6 mm × 0.3 mm (0603).

配線板自体としては、配線層間の電気的接続(層間接続)が、スルーホールの内表面に形成された導電層によるものから、COレーザやUV−YAGレーザにより各層ごとにホールを形成しその内側にめっきを形成するものや導電性ペーストを充填するものなど(いわゆるブラインドビア)に移行している。また、配線パターン形成には、その微細化のため、エッチングによる方法(サブトラクティブ工法)に代えてめっきにより配線をメタライズ形成する方法(アディティブ工法)も使用されつつある。これにより、L/S(ライン/スペース)=20μm/20μm程度まで微細形成可能となっている。 As the wiring board itself, the electrical connection between the wiring layers (interlayer connection) is based on the conductive layer formed on the inner surface of the through hole, and a hole is formed for each layer by a CO 2 laser or a UV-YAG laser. There is a shift to those that form plating on the inside and those that are filled with conductive paste (so-called blind vias). For wiring pattern formation, a method (additive method) of forming a metallized wiring by plating instead of a method by etching (subtractive method) is being used for miniaturization. Thereby, it is possible to form finely up to about L / S (line / space) = about 20 μm / 20 μm.

このような状況でさらに部品実装密度を向上し機器の小型化に資するには、例えば、配線板内に部品を内蔵する部品内蔵配線板を用いることができる。部品内蔵配線板には、例えば、実開平5−53269号公報に開示されたものがある。
実開平5−53269号公報
In such a situation, in order to further improve the component mounting density and contribute to downsizing of the device, for example, a component built-in wiring board in which components are built in the wiring board can be used. An example of the component built-in wiring board is disclosed in Japanese Utility Model Laid-Open No. 5-53269.
Japanese Utility Model Publication No. 5-53269

上記公報に開示されたものでは、基板内に内蔵して実装される部品は、基板上に実装される場合と同様に、部品の端子それぞれに対応して設けられたランド(当然、板厚み方向とは垂直方向に形成されている)上に接続される。ここで、部品が基板内に内蔵される場合には、その部品の各周りは電気的接続部を除いて絶縁樹脂で覆われ密着されるのが好ましい。未充填部位が生じると信頼性を劣化させるからである。この点で、上記公報のものは、構造上、部品とこの部品が直接実装される基板との間に隙間が生じた場合、この隙間は非常に狭く樹脂の未充填が生じやすい。   In what is disclosed in the above publication, the component mounted and mounted in the substrate is the land (corresponding to the thickness direction of the plate) provided corresponding to each terminal of the component, as in the case of mounting on the substrate. Are formed in the vertical direction). Here, when the component is built in the substrate, it is preferable that the periphery of the component is covered and intimately covered with an insulating resin except for the electrical connection portion. This is because reliability is deteriorated when an unfilled portion is formed. In this regard, in the above-mentioned publication, when a gap is generated between the component and the substrate on which the component is directly mounted, the gap is very narrow and the resin is not easily filled.

本発明は、上記した事情を考慮してなされたもので、部品内蔵配線板の製造方法および部品内蔵配線板において、信頼性を損なうことなくさらなる部品実装密度を向上することが可能な部品内蔵配線板の製造方法および部品内蔵配線板を提供することを目的とする。   The present invention has been made in consideration of the above-described circumstances. In the method for manufacturing a wiring board with a built-in component and the wiring board with a built-in component, the wiring with a built-in component that can further improve the component mounting density without impairing the reliability. It is an object to provide a board manufacturing method and a component built-in wiring board.

上記の課題を解決するため、本発明に係る部品内蔵配線板の製造方法は、少なくとも上下両面に導電層を有するコア配線板を製造する工程と、内蔵すべき電気/電子部品を位置させるべき空間が生じるように前記製造されたコア配線板にほぼ円形の貫通孔を形成する工程と、前記形成された貫通孔の内表面を含むように導電層を形成する工程と、前記上下両面の導電層をパターニングする工程と、前記貫通孔に形成された前記導電層を内蔵すべき電気/電子部品の端子の数に応じて分断する工程と、前記空間に電気/電子部品を位置させる工程と、前記位置させられた電気/電子部品の前記端子と前記分断された導電層とを導電部材で接続する工程と、前記導電部材により前記電気/電子部品が接続された前記コア配線板の上下両面それぞれに重ねてかつ前記電気/電子部品の周りを充填するように絶縁層を積層形成する工程とを具備することを特徴とする。   In order to solve the above problems, a method of manufacturing a component built-in wiring board according to the present invention includes a step of manufacturing a core wiring board having conductive layers on at least both upper and lower surfaces, and a space in which an electric / electronic component to be embedded is located. Forming a substantially circular through hole in the manufactured core wiring board so as to generate a conductive layer, forming a conductive layer so as to include an inner surface of the formed through hole, and the upper and lower conductive layers Patterning, dividing the conductive layer formed in the through-hole according to the number of terminals of the electrical / electronic component to be embedded, positioning the electrical / electronic component in the space, Connecting the terminal of the positioned electrical / electronic component and the divided conductive layer with a conductive member; and both upper and lower surfaces of the core wiring board to which the electrical / electronic component is connected by the conductive member Superimposed, characterized in that in and and a step of laminating an insulating layer is formed to fill around the electric / electronic components.

この製造方法では、内蔵部品の端子に接続するための導電層を、内蔵すべき電気/電子部品を位置させる空間である貫通孔の内表面に形成する。形成された導電層は内蔵部品の端子の数に応じて分断される。したがって、その部品の端子と導電層との接続は、例えば水平方向にブリッジした形状の導電部材によりなされ得る。よって、内蔵部品の周りに間隙を生じにくくした構造となり、内蔵部品の周りには積層のための絶縁層が充填・密着され得る。したがって、内蔵部品の周辺に空隙が発生せず信頼性を劣化させない配線板を製造することができる。   In this manufacturing method, a conductive layer for connecting to a terminal of a built-in component is formed on the inner surface of a through hole, which is a space where an electric / electronic component to be built is located. The formed conductive layer is divided according to the number of terminals of the built-in component. Therefore, the connection between the terminal of the component and the conductive layer can be made, for example, by a conductive member having a bridge shape in the horizontal direction. Therefore, it becomes a structure in which a gap is hardly generated around the built-in component, and an insulating layer for stacking can be filled and adhered around the built-in component. Therefore, it is possible to manufacture a wiring board in which no gap is generated around the built-in component and reliability is not deteriorated.

また、本発明に係る部品内蔵配線板は、板厚み方向に形成されかつ板上下面には表出せずに埋設されている導電層と、端子を有し、前記埋設された導電層に前記端子が対向するように板内埋設された電気/電子部品と、前記埋設された電気/電子部品の前記端子と前記導電層との間隙に設けられ、前記導電層の横方向端部に接触せずに前記端子と前記導電層とを電気的・機械的に接続する接続部材と、前記埋設された電気/電子部品の外表面のうち前記接続部材に接続される部位以外を覆いかつ前記電気/電子部品の板厚み方向上下に密着するように設けられた上下2つの絶縁層とを具備することを特徴とする。   The component built-in wiring board according to the present invention has a conductive layer formed in the thickness direction of the board and embedded without being exposed on the upper and lower surfaces of the board, and a terminal, and the terminal is connected to the embedded conductive layer. Is provided in a gap between the terminal of the embedded electric / electronic component and the conductive layer, and does not contact the lateral end of the conductive layer. A connection member for electrically and mechanically connecting the terminal and the conductive layer, and covering a portion of the outer surface of the embedded electric / electronic component other than the portion connected to the connection member and the electric / electronic And two upper and lower insulating layers provided so as to be in close contact with each other in the plate thickness direction of the component.

この部品内蔵配線板では、内蔵部品の端子に接続するための導電層が板厚み方向に形成されており、導電層の横方向幅は接続部材を介する内蔵部品との接続に十分余裕がある。したがって、その部品の端子と導電層との接続は、例えば水平方向にブリッジした形状の導電部材によりなされる。よって、内蔵部品の周りに間隙を生じにくくした構造となり、内蔵部品の周りには上下2つの絶縁層が密着する。したがって、内蔵部品の周辺に空隙が発生せず信頼性を劣化させない。   In this component built-in wiring board, the conductive layer for connecting to the terminal of the built-in component is formed in the plate thickness direction, and the lateral width of the conductive layer has a sufficient margin for connection with the built-in component via the connecting member. Therefore, the connection between the terminal of the component and the conductive layer is made by, for example, a conductive member bridged in the horizontal direction. Therefore, the structure is such that a gap is hardly generated around the built-in component, and the upper and lower insulating layers are in close contact with the built-in component. Therefore, no gap is generated around the built-in component, and reliability is not deteriorated.

本発明によれば、内蔵部品の端子に接続するための導電層が板厚み方向に形成され、したがって、その部品の端子と導電層との接続は、例えば水平方向にブリッジした形状の導電部材によりなされる。よって、内蔵部品の周りに間隙を生じにくくした構造となり、内蔵部品の周りには上下2つの絶縁層が密着し得る。ゆえに、内蔵部品の周辺に空隙が発生せず信頼性を劣化させない。   According to the present invention, the conductive layer for connecting to the terminal of the built-in component is formed in the plate thickness direction. Therefore, the connection between the terminal of the component and the conductive layer is performed by, for example, a conductive member bridged in the horizontal direction. Made. Therefore, the gap is less likely to occur around the built-in component, and the upper and lower two insulating layers can be in close contact with the built-in component. Therefore, no gap is generated around the built-in component, and reliability is not deteriorated.

本発明の実施態様として、前記形成された貫通孔の内表面を含むように導電層を形成する前記工程は、無電解めっきにより下地となる導電層を形成する工程と、前記形成された下地を種に用いて電解めっきにより上層となる導電層を形成する工程とを有してなされる。このような2段階のめっきを用いることで効率的なめっき形成を行なうことができる。   As an embodiment of the present invention, the step of forming a conductive layer so as to include the inner surface of the formed through-hole includes a step of forming a conductive layer serving as a base by electroless plating, and the formed base And a step of forming an upper conductive layer by electrolytic plating using the seed. Efficient plating can be formed by using such two-stage plating.

また、実施態様として、内蔵すべき電気/電子部品を位置させるべき空間が生じるように前記製造されたコア配線板にほぼ円形の貫通孔を形成する前記工程は、ドリリングまたは金型打ち抜きによりなすことができる。ドリリングを用いることで、スルーホール用の穴明け機など既存の製造装置の利用を図ることができる。金型打ち抜きでは効率的な貫通孔形成ができる   Further, as an embodiment, the step of forming a substantially circular through hole in the manufactured core wiring board so as to create a space in which to place an electrical / electronic component to be built is performed by drilling or die punching. Can do. By using drilling, it is possible to use existing manufacturing equipment such as a through-hole drilling machine. Efficient through hole formation is possible by die punching

また、実施態様として、前記空間に電気/電子部品を位置させる前記工程は、前記空間からのぞく前記コア配線板の下位置に支持部材をあてがい、前記支持部材上に前記電気/電子部品を位置させてなすことができる。部品の実装位置は、コア配線板に形成された空間であるが、このように支持部材を利用することで、通常のマウンタなど既存の製造装置の利用を図ることができる。   Further, as an embodiment, in the step of positioning the electric / electronic component in the space, a supporting member is placed under the core wiring board except for the space, and the electric / electronic component is positioned on the supporting member. It can be done. The mounting position of the component is a space formed in the core wiring board. By using the support member in this way, it is possible to use an existing manufacturing apparatus such as a normal mounter.

また、実施態様として、前記位置させられた電気/電子部品の前記端子と前記分断された導電層とを導電部材で接続する前記工程は、前記導電部材として半田または導電性樹脂が用いられ得る。利用可能な電気的・機械的接続部材として代表的なものである。   Further, as an embodiment, in the step of connecting the terminal of the positioned electrical / electronic component and the divided conductive layer with a conductive member, solder or conductive resin may be used as the conductive member. It is a typical example of an electrical / mechanical connecting member that can be used.

また、実施態様として、前記貫通孔に形成された前記導電層を内蔵すべき電気/電子部品の端子の数に応じて分断する工程は、ドリリング、金型打ち抜き、またはレーザ加工によりなされる。   As an embodiment, the step of dividing the conductive layer formed in the through hole in accordance with the number of terminals of the electric / electronic component to be incorporated is performed by drilling, die punching, or laser processing.

また、実施態様として、少なくとも上下両面に導電層を有するコア配線板を製造する前記工程は、配線層を4つ有するコア配線板を製造するものであり、かつ、これらの配線層同士の電気的接続が導電性バンプでなされるように製造され得る。配線層を4つとすることにより、コア配線板の厚さを部品内蔵空間が確保しやすい寸法とし、配線層同士の層間接続を導電性バンプで行なうことにより一層の高密度実装を実現する。   Further, as an embodiment, the step of manufacturing a core wiring board having conductive layers on at least both upper and lower surfaces is a process of manufacturing a core wiring board having four wiring layers, and electrical connection between these wiring layers. The connection can be made with conductive bumps. By using four wiring layers, the thickness of the core wiring board is set to a dimension that can easily secure the component built-in space, and the interlayer connection between the wiring layers is performed by conductive bumps, thereby realizing higher density mounting.

また、部品内蔵配線板の実施態様として、前記埋設された導電層に電気的に接続可能な複数の板方向導電層と、前記複数の板方向導電層を層間接続する導電性バンプによる層間接続体とをさらに具備するようにしてもよい。   Further, as an embodiment of the component built-in wiring board, an interlayer connection body including a plurality of plate-direction conductive layers that can be electrically connected to the embedded conductive layers, and conductive bumps that connect the plurality of plate-direction conductive layers to each other May be further provided.

以上を踏まえ、以下では本発明の実施形態を図面を参照しながら説明する。図1は、本発明の一実施形態に係る部品内蔵配線板の模式的な構成を示す断面図(図1(a))および一部平面図(図1(b))である。   Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view (FIG. 1 (a)) and a partial plan view (FIG. 1 (b)) showing a schematic configuration of a component built-in wiring board according to an embodiment of the present invention.

この実施形態は、図1(a)に示すように、絶縁層11〜14を有し、絶縁層11、12の境界付近、絶縁層13、14の境界付近、および上下面に配線層21〜24をそれぞれ有する4層配線板である。配線層21、22間、および配線層23、24間の電気的接続(層間接続)は導電性バンプ41、42によりそれぞれなされている。このような導電性バンプ41、42により、配線板主面の利用効率が向上し高密度実装に適する。内側の配線層22、23間の層間接続は、縦方向の導電層34、35によるもの以外は図示していないが、導電性組成物によるいわゆるブラインドビアなどの形成により行うことも可能である。なお、上下面の符号31、32は、半田レジストである。   As shown in FIG. 1A, this embodiment has insulating layers 11 to 14, near the boundaries of the insulating layers 11 and 12, near the boundaries of the insulating layers 13 and 14, and wiring layers 21 to 4 is a four-layer wiring board having 24 respectively. Electrical connection (interlayer connection) between the wiring layers 21 and 22 and between the wiring layers 23 and 24 is made by conductive bumps 41 and 42, respectively. Such conductive bumps 41 and 42 improve the utilization efficiency of the main surface of the wiring board and are suitable for high-density mounting. Although the interlayer connection between the inner wiring layers 22 and 23 is not shown except for the conductive layers 34 and 35 in the vertical direction, it can also be made by forming a so-called blind via or the like with a conductive composition. Reference numerals 31 and 32 on the upper and lower surfaces are solder resists.

また、内側の配線層22、23の水平レベル内に含まれるように電気/電子部品33(例えばここではチップ抵抗)が内蔵される。部品33は、その両端子が接続部材としての半田36、37を介して、板厚み方向に形成された導電層34、35に向かい合いかつ電気的、機械的に接続されている。導電層34、35は、図示するように、内側の配線層22、23との直接的な電気的接続が可能となっている。   Further, an electric / electronic component 33 (for example, a chip resistor here) is incorporated so as to be included in the horizontal level of the inner wiring layers 22 and 23. Both terminals of the component 33 face the conductive layers 34 and 35 formed in the plate thickness direction and are electrically and mechanically connected via solders 36 and 37 as connecting members. As shown in the figure, the conductive layers 34 and 35 can be directly connected to the inner wiring layers 22 and 23.

部品33は、平面的に見ると図1(b)に示すように配設されている。すなわち、部品33を内蔵するため内側の絶縁層12、13には貫通空間が形成され、この貫通空間は、部品33および接続するための半田36、37ならびに上下両側の絶縁層11、14の内側へのはみ出し部により占められている。半田36、37は、導電層34、35の横方向端部(=製造工程上バリの発生があり得る。詳しくは後述。)までは達していない。なお、部品33は、通常、図1(a)に示す厚さの方が図1(b)に示す幅より寸法が小さいが、図1では配線板の厚み方向を強調拡大して示すため部品33についても厚さの方が大きく表示されている。   The component 33 is arranged as shown in FIG. That is, a through space is formed in the inner insulating layers 12 and 13 in order to incorporate the component 33, and this through space is formed inside the insulating layers 11 and 14 on both the upper and lower sides of the component 33 and the solder 36 and 37 for connection. It is occupied by the overhanging part. The solders 36 and 37 do not reach the end portions in the lateral direction of the conductive layers 34 and 35 (= burrs may occur in the manufacturing process. Details will be described later). The component 33 is usually smaller in the thickness shown in FIG. 1 (a) than the width shown in FIG. 1 (b). However, since the thickness direction of the wiring board is shown in FIG. The thickness of 33 is also displayed larger.

具体的な寸法(厚さ)は、部品33として0603のチップ抵抗を使用したとき、絶縁層12、13の合計厚が例えば0.2mm〜0.3mm程度となるように、これらの絶縁層12、13それぞれが0.1mmないし0.15mm程度の厚さである。部品としてこれより大きい(厚い)ものを用いる場合には、それに応じた厚さを有する絶縁層12、13を用いることができる。絶縁層12、13は、単一の層のものを用いてもよいが、この実施形態では2つの層の積層により所定の厚さを得ている。   Specific dimensions (thicknesses) are such that when a chip resistance of 0603 is used as the component 33, these insulating layers 12 and 13 have a total thickness of about 0.2 mm to 0.3 mm, for example. 13 each have a thickness of about 0.1 mm to 0.15 mm. When a larger (thick) component is used as the component, the insulating layers 12 and 13 having a thickness corresponding to the component can be used. The insulating layers 12 and 13 may be a single layer, but in this embodiment, a predetermined thickness is obtained by stacking two layers.

なお、各部材料は、絶縁層11〜14には例えばエポキシ樹脂、ポリイミド樹脂、ビスマレイミドトリアジン樹脂など、配線層21〜24や導電層34、35には例えば銅など、導電性バンプ41、42には、例えば微細な金属粒(銀、銅、金、半田など)を樹脂中に分散させた導電性樹脂などを用いることができる。また、半田36、37については、これに代えて導電性樹脂を用いることができる。   The material of each part is, for example, epoxy resin, polyimide resin, bismaleimide triazine resin, etc. for the insulating layers 11-14, copper, etc., for the wiring layers 21-24 and the conductive layers 34, 35, etc. For example, a conductive resin in which fine metal particles (silver, copper, gold, solder, etc.) are dispersed in the resin can be used. For the solders 36 and 37, a conductive resin can be used instead.

この実施形態の構造の配線板では、内蔵された部品33の周りを絶縁層11、14が覆うように密着し、空隙の発生を防止するので信頼性向上に極めて好ましい。なお、以上の記述では、電気/電子部品33としてチップ抵抗を例にして説明したが、チップコンデンサ、チップインダクタ、チップダイオードなど端子の配置構造がチップ抵抗とほぼ同じものでは同様な適用が可能である。   The wiring board having the structure of this embodiment is extremely preferable for improving the reliability because the insulating layers 11 and 14 are in close contact with each other so as to cover the built-in component 33 and prevent the generation of voids. In the above description, the chip resistor has been described as an example of the electric / electronic component 33. However, the same application is possible when the terminal arrangement structure such as a chip capacitor, a chip inductor, and a chip diode is substantially the same as the chip resistor. is there.

次に、上記のような構造の部品内蔵配線板を製造するプロセスの例を図2ないし図6を参照して説明する。図2ないし図6は、本発明の一実施形態に係る部品内蔵配線板を製造するプロセスを模式的に断面(または一部平面)にて示す図である。これらの図において、同一相当の部位には同一符号を付してある。また、図1に示す配線板と対応する部位にも同一符号を付してある。   Next, an example of a process for manufacturing the component built-in wiring board having the above structure will be described with reference to FIGS. 2 to 6 are diagrams schematically showing a process of manufacturing the component built-in wiring board according to the embodiment of the present invention in a cross section (or a partial plane). In these drawings, the same reference numerals are assigned to the same equivalent portions. Moreover, the same code | symbol is attached | subjected also to the site | part corresponding to the wiring board shown in FIG.

図2は、コア配線板(部品が内蔵されるべき層を含む配線板素材)に部品内蔵用の貫通孔を形成する途中までの製造工程を示す断面図または一部平面図である。まず、図2(a)に示すように、絶縁板12、13が積層され、その上下面に銅箔(厚さは例えば18μm)22a、23aが配設された両面銅張り板を用意する。これがコア配線板になる。   FIG. 2 is a cross-sectional view or a partial plan view showing a manufacturing process up to the middle of forming a through hole for incorporating a component in a core wiring board (a wiring board material including a layer in which the component is to be incorporated). First, as shown in FIG. 2A, a double-sided copper-clad plate is prepared in which insulating plates 12 and 13 are laminated and copper foils (thickness is 18 μm, for example) 22a and 23a are arranged on the upper and lower surfaces thereof. This becomes the core wiring board.

コア配線板が用意されたら、次に、図2(b1)、(b2)に示すように、コア配線板の必要な位置に円形の貫通孔51を形成する。貫通孔51は、内蔵部品との接続に用いる、板厚み方向の導電層を形成するためのものであり、かつ内蔵部品を位置させる空間となるものである。ここでは、貫通孔51として0.8mm径のNC(numerical control)ドリルを用いて内蔵部品ごとにひとつずつ設ける。ドリルにより孔を明けたら、孔内を、例えば高圧水洗浄および所定の薬液を用いるデスミア処理で洗浄しておく。なお、貫通孔51の形成に金型打ち抜きを用いることもできる。   After the core wiring board is prepared, next, as shown in FIGS. 2B1 and 2B2, circular through holes 51 are formed at necessary positions of the core wiring board. The through-hole 51 is used to form a conductive layer in the thickness direction used for connection with the built-in component, and serves as a space for positioning the built-in component. Here, an NC (numerical control) drill having a diameter of 0.8 mm is used as the through-hole 51 for each built-in component. After drilling the hole, the inside of the hole is cleaned by, for example, high-pressure water cleaning and desmear treatment using a predetermined chemical solution. It is also possible to use die punching for forming the through hole 51.

次に、図2(c1)、(c2)に示すように、貫通孔51の内壁面を含むように例えば銅のめっき層52を例えば20μm厚で形成する。めっき層52の形成には、例えば、まず、化学銅めっきのような無電解めっきにより連続面のシード層を形成し、そのあと、形成されたシード層を種に例えば硫酸銅めっき浴にて電解めっき処理することよりなすことができる。このような2段階のめっきにより効率的にめっき層52を形成することができる。   Next, as shown in FIGS. 2C1 and 2C2, for example, a copper plating layer 52 having a thickness of, for example, 20 μm is formed so as to include the inner wall surface of the through hole 51. For the formation of the plating layer 52, for example, a continuous surface seed layer is first formed by electroless plating such as chemical copper plating, and then electrolysis is performed using, for example, a copper sulfate plating bath using the formed seed layer as a seed. This can be done by plating. The plating layer 52 can be efficiently formed by such two-stage plating.

なお、図2に示す工程は、部品内蔵用の貫通孔51の形成として説明したが、いわゆるブラインドビアによる層間接続の形成工程としての説明にもほぼなっている。すなわち、銅箔22a、23aによる配線層の間の電気的接続が必要な場合には、貫通孔51と同様な孔(ただし直径はそれより小)を形成し、さらにその内壁面にめっき層を形成すれば層間接続を形設することができる。   The process shown in FIG. 2 has been described as the formation of the component-embedded through-hole 51, but is almost the same as the process of forming the interlayer connection by so-called blind vias. That is, when electrical connection between the wiring layers by the copper foils 22a and 23a is necessary, a hole similar to the through hole 51 (however, the diameter is smaller than that) is formed, and a plating layer is formed on the inner wall surface thereof. Once formed, interlayer connections can be formed.

図3は、コア配線板に部品内蔵用の貫通孔を形成する残りの製造工程を示す断面図または一部平面図である。   FIG. 3 is a cross-sectional view or a partial plan view showing the remaining manufacturing process for forming a through hole for incorporating a component in the core wiring board.

図2(c1)、(c2)に示すようにめっき層52が形成されたら、次に、両面の銅箔22a、23a(、および両面に位置するめっき層52)にパターニングを施し配線層22、23を形成する。このパターニングは、例えば、まず、銅箔22a、23a(両面に位置するめっき層52を含む。以下、次段落まで同。)の表面を化学研磨してレジスト用のドライフィルムとの密着性を向上したうえで、レジスト用ドライフィルムを銅箔22a、23aに積層する。そして、フォトマスクを介して例えば超高圧水銀灯を有するアライメント露光機でドライフィルムを露光し、さらに炭酸ナトリウムによってスプレー現像する。この現像パターンのドライフィルムを銅箔22a、23a上に残すことにより、パターニングされたレジストが銅箔22a、23a上に形成される。   After the plating layer 52 is formed as shown in FIGS. 2C1 and 2C2, the copper layers 22a and 23a on both sides (and the plating layer 52 located on both sides) are patterned to form the wiring layer 22, 23 is formed. In this patterning, for example, first, the surfaces of the copper foils 22a and 23a (including the plating layers 52 located on both sides; the same applies to the next paragraph) are chemically polished to improve the adhesion to the resist dry film. After that, a resist dry film is laminated on the copper foils 22a and 23a. Then, the dry film is exposed with an alignment exposure machine having, for example, an ultrahigh pressure mercury lamp through a photomask, and further spray-developed with sodium carbonate. By leaving the dry film of this development pattern on the copper foils 22a and 23a, a patterned resist is formed on the copper foils 22a and 23a.

レジストが銅箔22a、23a上に形成されたら、これをマスクにエッチャントとして塩化第2鉄をベースとする薬液を用い、レジストパターンとして抜けた位置の銅箔22a、23aをスプレーエッチングする。これにより、銅箔22a、23aから配線層22、23が形成される。形成された配線層22、23は、このあと積層される絶縁層との密着性を向上するために黒化還元処理を行なっておく(これは、後述する図6(a)の段階でもよい。)。形成された配線層22、23は、図3(a2)に示すように、貫通孔51の内壁面に形成されためっき層52に対してのランド部分(その外径は例えば1.2mm)を含む。   When the resist is formed on the copper foils 22a and 23a, a chemical solution based on ferric chloride is used as an etchant using the resist as a mask, and the copper foils 22a and 23a at positions removed as a resist pattern are spray-etched. Thereby, the wiring layers 22 and 23 are formed from the copper foils 22a and 23a. The formed wiring layers 22 and 23 are subjected to blackening reduction treatment in order to improve the adhesion with the insulating layer to be subsequently laminated (this may be the stage shown in FIG. 6A described later). ). As shown in FIG. 3 (a2), the formed wiring layers 22 and 23 have land portions (the outer diameter is 1.2 mm, for example) with respect to the plating layer 52 formed on the inner wall surface of the through hole 51. Including.

次に、図3(b1)に示すように、貫通孔51内壁面のめっき層52を分断して内蔵部品との接続部である導電層34、35を独立形成するようにコア配線板を加工する。ここでの加工方法は、NCドリルを用いた孔明けによる。すなわち、貫通孔51の外形上向い合う位置に貫通孔51より小さい直径(例えば0.5mm)の孔(めっき層分断貫通孔)53を明ける。このようなドリルによるめっき層52の分断によれば、既存の装置を用いて容易に導電層34、35を分断形成することができる。   Next, as shown in FIG. 3 (b1), the core wiring board is processed so as to divide the plating layer 52 on the inner wall surface of the through-hole 51 and independently form the conductive layers 34 and 35 which are the connection parts with the built-in components. To do. The processing method here is based on drilling using an NC drill. That is, a hole (plated layer dividing through hole) 53 having a smaller diameter (for example, 0.5 mm) than the through hole 51 is opened at a position facing the outer shape of the through hole 51. According to the division of the plating layer 52 by such a drill, the conductive layers 34 and 35 can be easily divided and formed using an existing apparatus.

また、めっき層52の分断が、貫通孔51の直径に対して小さい直径の孔53によりなされるので、独立形成される導電層34、35の横方向寸法は比較的大きな幅になる。このため、図3(b2)に示すように孔53の形成によるバリ53A(主にめっき層52が剥離して切除されずに残ったもの。)が導電層34、35との境界に発生する場合にも、このバリ53Aが内蔵部品の実装に干渉することを防止できる。換言すると、バリ53Aが発生してもこれを取り除く工程を特に必要としないので生産性を向上できる(図4(b3)でも言及する。)。なお、バリ53Aは、孔53を明けるドリルの刃の劣化が進むとより発生しやすいことが分かっている。   Further, since the plating layer 52 is divided by the hole 53 having a diameter smaller than the diameter of the through hole 51, the lateral dimensions of the conductive layers 34 and 35 formed independently have a relatively large width. For this reason, as shown in FIG. 3 (b2), the burr 53A (mainly, the plating layer 52 is peeled off and remains without being removed) due to the formation of the hole 53 is generated at the boundary with the conductive layers 34 and 35. Even in this case, the burr 53A can be prevented from interfering with the mounting of the built-in component. In other words, even if the burr 53A is generated, a process for removing the burr 53A is not particularly required, so that productivity can be improved (also referred to in FIG. 4 (b3)). It has been found that the burr 53A is more likely to occur as the drill blades that open the hole 53 deteriorate.

以上により、部品を内蔵するための空間(貫通孔51による空間)が形成されたコア配線板を得ることができる。なお、上記でめっき層52の分断は、ドリリングによらなくてもなすことは可能である。例えば金型による打ち抜き(パンチング)や切削機、またはレーザ加工を用いる方法が挙げられる。   As described above, it is possible to obtain a core wiring board in which a space for incorporating a component (a space by the through hole 51) is formed. Note that the plating layer 52 can be divided without using drilling. For example, a method using punching with a mold, a cutting machine, or laser processing is used.

図4は、コア配線板に部品を内蔵するための部品実装工程を示す断面図または一部平面図である。まず、図4(a)に示すように、コア配線板の片側面を支持部材61にあてがい、この状態において、マウンタなどの実装機器により所定位置(内蔵するための空間)に部品33を位置させる。ここで、支持部材61の面上は、粘着層61aを設けるようにするとより好ましい。粘着層61aにより、マウントされた部品33がある程度固定されて次工程に供することができるからである。   FIG. 4 is a cross-sectional view or a partial plan view showing a component mounting process for incorporating components into the core wiring board. First, as shown in FIG. 4A, one side surface of the core wiring board is applied to the support member 61, and in this state, the component 33 is positioned at a predetermined position (a space for incorporation) by a mounting device such as a mounter. . Here, it is more preferable to provide the adhesive layer 61a on the surface of the support member 61. This is because the mounted component 33 is fixed to some extent by the adhesive layer 61a and can be used in the next process.

なお、このような粘着層61aを有する支持部材61に代えて、耐熱性の粘着テープ(または耐熱性の粘着シート)をコア配線板の片面に張り付けるようにしてもよい。   Instead of the support member 61 having such an adhesive layer 61a, a heat-resistant adhesive tape (or a heat-resistant adhesive sheet) may be attached to one side of the core wiring board.

次に、図4(b1)、(b2)に示すように、部品33の両端子付近の所定位置にクリーム半田36a、37a(半田は、例えばSn−3.0Ag−0.5Cuの鉛フリーのもの)を塗布する。このような塗布は、例えばスクリーン印刷またはディスペンサにより行なうことができる。ここでは、0.5mm径のピットを有するスクリーン版によるスクリーン印刷を用いた。なお、クリーム半田36a、37aは、これに代えて導電性ペーストを用いてもよい。   Next, as shown in FIGS. 4B1 and 4B2, cream solders 36a and 37a (solder is, for example, Sn-3.0Ag-0.5Cu lead-free solder) at predetermined positions near both terminals of the component 33. Apply). Such application can be performed, for example, by screen printing or a dispenser. Here, screen printing using a screen plate having 0.5 mm diameter pits was used. The cream solders 36a and 37a may use conductive paste instead.

部品33のマウント、およびクリーム半田36a、37aの塗布においては、図4(b3)に示すように、部品接続用の導電層34(35)の横方向端部にバリ53Aが生じている場合にも、これらの工程への干渉が生じない。すなわち、導電層34(35)の横方向寸法が部品33に対して大きく確保されており、バリ53Aの発生位置を避けて部品33のマウント、およびクリーム半田36a、37aの塗布が可能だからである。   In mounting the component 33 and applying the cream solders 36a and 37a, as shown in FIG. 4 (b3), when a burr 53A is generated at the lateral end of the component connecting conductive layer 34 (35). However, there is no interference with these processes. That is, the lateral dimension of the conductive layer 34 (35) is large with respect to the component 33, and it is possible to mount the component 33 and apply the cream solders 36a and 37a while avoiding the position where the burr 53A is generated. .

次に、ここで、部品の実装されたコア配線板の両面に積層すべき絶縁層および導電層を形成する工程について図5を参照して説明する。図5は、コア配線板上に積層するための配線板素材を形成する工程を示す断面図である。このような絶縁層および導電層はあらかじめ配線板素材として形成しておく。   Next, a process of forming an insulating layer and a conductive layer to be laminated on both surfaces of the core wiring board on which components are mounted will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a process of forming a wiring board material to be laminated on the core wiring board. Such an insulating layer and a conductive layer are formed in advance as a wiring board material.

まず、図5(a)に示すように、銅箔(厚さは例えば18μm)21a(24a)を用意し、この銅箔21a(24a)上の必要な位置(特定の配線板のレイアウトに従う位置)にほぼ円錐形の導電性バンプ41a(42a)を形成する。これには、例えばスクリーン印刷を用いて導電性ペーストを銅箔21a(24a)上に印刷してなすことができる。   First, as shown in FIG. 5A, a copper foil (thickness is, for example, 18 μm) 21a (24a) is prepared, and a necessary position on the copper foil 21a (24a) (a position according to a specific wiring board layout). ) Is formed with a substantially conical conductive bump 41a (42a). For this, for example, a conductive paste can be printed on the copper foil 21a (24a) using screen printing.

この場合のスクリーン版には、例えば0.2mmの貫通孔(ピット)が穿設されたものを用いることができる。これにより、例えば底面径として0.15mm程度以上の導電性バンプを形成することができる。導電性ペーストとしては、例えばエポキシ樹脂のようなペースト状樹脂の中に金属粒(銀、金、銅、半田など)を分散させ、加えて揮発性の溶剤を混合させたもの用いることができる。印刷されたあと、例えばオーブンで乾燥し導電性ペーストを硬化させる。   As the screen plate in this case, for example, a screen plate having 0.2 mm through holes (pits) can be used. Thereby, for example, a conductive bump having a bottom diameter of about 0.15 mm or more can be formed. As the conductive paste, for example, a paste in which metal particles (silver, gold, copper, solder, etc.) are dispersed in a paste-like resin such as an epoxy resin, and a volatile solvent is mixed can be used. After printing, the conductive paste is cured by drying in an oven, for example.

次に、専用機を用い、銅箔21a(24a)に絶縁層11(14)とすべきプリプレグ(厚さは例えば0.06mm)に対向させて、図5(b)に示すように、導電性バンプ41a(42a)を半硬化状態のプリプレグに貫通させる。プリプレグは、例えば、エポキシ樹脂のような硬化性樹脂をガラス繊維のような補強材に含浸させたものである。また、硬化する前には半硬化状態にあり、熱可塑性(熱による流動性)および熱硬化性を有する。図5(b)に示す状態のものを配線板素材1aまたは1bとして後述で参照する。   Next, using a dedicated machine, the copper foil 21a (24a) is made to face the prepreg (thickness is, for example, 0.06 mm) to be the insulating layer 11 (14), and as shown in FIG. The conductive bump 41a (42a) is passed through the semi-cured prepreg. For example, the prepreg is obtained by impregnating a reinforcing material such as glass fiber with a curable resin such as an epoxy resin. Moreover, it is in a semi-cured state before curing, and has thermoplasticity (fluidity due to heat) and thermosetting. The thing of the state shown in FIG.5 (b) is referred later by the wiring board raw material 1a or 1b.

図6は、部品の実装されたコア配線板を用いて完成品としての部品内蔵配線板を形成する工程を断面で示す図である。図4(b1)、(b2)に示すようにクリーム半田36a、37aをコア配線板上に塗布したら、次に、クリーム半田36a、37aをリフロー炉でリフローさせる。これにより、図6(a)に示すような状態となり、接続部材としての半田36、37が導電層34、35と部品33の端子との電気的・機械的接続を確立する。なお、クリーム半田36a、37aに代えて導電性ペーストを用いた場合には、これを例えばオーブンで乾燥させ硬化させて電気的・機械的接続を確立する。   FIG. 6 is a cross-sectional view showing a process of forming a component built-in wiring board as a finished product using the core wiring board on which the components are mounted. After the cream solders 36a and 37a are applied onto the core wiring board as shown in FIGS. 4B1 and 4B2, the cream solders 36a and 37a are then reflowed in a reflow furnace. As a result, the state shown in FIG. 6A is obtained, and the solders 36 and 37 as connection members establish electrical and mechanical connections between the conductive layers 34 and 35 and the terminals of the component 33. In the case where a conductive paste is used instead of the cream solders 36a and 37a, this is dried and cured, for example, in an oven to establish an electrical / mechanical connection.

以上により得られた部品装着のコア配線板4は、その両面の配線層22、23についてこのあと積層される絶縁層との密着性を向上するため黒化還元処理を行なっておく。   The component-mounted core wiring board 4 obtained as described above is subjected to blackening reduction treatment in order to improve the adhesion between the wiring layers 22 and 23 on both sides thereof and the insulating layer to be laminated thereafter.

次に、図6(b)に示すように、コア配線板4の両側に配線板素材1a、1bを積層し、これらを一体化する。このとき絶縁層11、14とすべきプリプレグを硬化させる。配線板素材1a、1bは、図5に示したようにして得られたものである。   Next, as shown in FIG. 6B, wiring board materials 1a and 1b are laminated on both sides of the core wiring board 4, and these are integrated. At this time, the prepreg to be the insulating layers 11 and 14 is cured. The wiring board materials 1a and 1b are obtained as shown in FIG.

この積層・一体化には、例えばレイアップ装置で位置合わせを行いコア配線板4と配線板素材1a、1bとを重ねて配置し、かつ真空積層熱プレス機を用いこれを所定の温度および圧力プロファイルに設定する。この積層・一体化により導電性バンプ41、42は、頭部がつぶされて塑性変形し、配線層22または23との電気的接続が確立する。   For this lamination / integration, for example, alignment is performed using a lay-up device, and the core wiring board 4 and the wiring board materials 1a and 1b are arranged so as to overlap each other. Set in the profile. As a result of the lamination and integration, the conductive bumps 41 and 42 are plastically deformed by crushing their heads, and electrical connection with the wiring layer 22 or 23 is established.

また、配線層22は、絶縁層11となるべきプリプレグの熱可塑性(熱による流動性)により絶縁層11側へ沈み込んで位置し、配線層23は、絶縁層14となるべきプリプレグの熱可塑性(熱による流動性)により絶縁層14側へ沈み込んで位置するようになる。さらに、絶縁層11、14となるべきプリプレグの熱可塑性(熱による流動性)により、内蔵された部品33を覆いかつ密着するようにその周辺にも絶縁層が絶縁層11、14と一体的に形成される。これにより部品33周りの穴埋め工程は不要であり工程の簡素化が実現するともに、間隙(ボイド)の発生を防止して信頼性を向上できる。   Further, the wiring layer 22 is positioned by sinking to the insulating layer 11 side due to the thermoplasticity (fluidity due to heat) of the prepreg to be the insulating layer 11, and the wiring layer 23 is thermoplasticity of the prepreg to be the insulating layer 14. Due to (fluidity by heat), it sinks into the insulating layer 14 side and comes to be positioned. Furthermore, due to the thermoplasticity (fluidity due to heat) of the prepreg that should become the insulating layers 11 and 14, the insulating layer is also integrated with the insulating layers 11 and 14 in the periphery so as to cover and closely adhere the built-in component 33. It is formed. This eliminates the need for a hole filling process around the part 33, which simplifies the process and prevents the generation of voids, thereby improving the reliability.

なお、外側に積層する配線板素材1a、1bは図5(b)に示す形態のものに代えて、さらに配線層数が多いものでもよい(例えば、図5(a)に示す銅箔21aの代わりにパターニング後の両面銅張り板を用いれば、図5(b)の段階では配線層数は2つになる。)。また、外側に積層する配線板素材1a、1bは、必ずしも、図5(b)に示すように導電性バンプ41a(42a)を伴っていなくてもよい。この場合、導電性バンプ41a(42a)がないので、銅箔21a(24a)と配線層22(23)との層間接続は、導電性バンプによって行なうことはできないが、積層後の配線板にスルーホールを設けこのスルーホールによる層間接続構造を形成することはできる。   The wiring board materials 1a and 1b laminated on the outer side may have a larger number of wiring layers instead of the one shown in FIG. 5B (for example, the copper foil 21a shown in FIG. 5A). If a patterned double-sided copper-clad plate is used instead, the number of wiring layers is two at the stage of FIG. Further, the wiring board materials 1a and 1b laminated on the outside do not necessarily need to be accompanied by the conductive bumps 41a (42a) as shown in FIG. In this case, since there is no conductive bump 41a (42a), the interlayer connection between the copper foil 21a (24a) and the wiring layer 22 (23) cannot be made by the conductive bump. It is possible to form an interlayer connection structure by providing holes and through holes.

外側に位置すべき絶縁層をコア配線板4と積層・一体化したら、次に、図6(c)に示すように、両外側の銅箔21a、24aに対してパターニングを施し配線層21、24を形成する。このパターニングは、図3(a1)、(a2)を参照した配線層22、23の形成工程と同様に行なうことができる。すなわち、化学研磨、レジスト用ドライフィルム積層、フォトマスクを介する露光、現像、エッチングという手順である。なお、以上の外側絶縁層11、14の積層、配線層21、24の形成のあと、さらにこの外側に同様の要領により絶縁層と銅箔とを積層・一体化(ビルドアップ)してもよい。   After the insulating layer to be positioned outside is laminated and integrated with the core wiring board 4, next, as shown in FIG. 6 (c), patterning is performed on the copper foils 21a and 24a on both outer sides, and the wiring layer 21, 24 is formed. This patterning can be performed in the same manner as the formation process of the wiring layers 22 and 23 with reference to FIGS. 3 (a1) and (a2). That is, the procedures are chemical polishing, resist dry film lamination, exposure through a photomask, development, and etching. Note that after the outer insulating layers 11 and 14 are stacked and the wiring layers 21 and 24 are formed, the insulating layer and the copper foil may be stacked and integrated (build-up) on the outer side in the same manner. .

次に、図6(c)に示すように、最外側面の所定の位置に半田レジスト31、32を形成する。さらに、配線層21または24の半田レジストの形成されない部位には腐蝕防止のため無電解めっき法によりニッケル/金(ニッケルが下地)の層(図示せず)を形成する。そして、配線板をルータ加工機により所定の外形となるように切り出す。以上により本実施形態に係る部品内蔵配線板を得ることができる。   Next, as shown in FIG. 6C, solder resists 31 and 32 are formed at predetermined positions on the outermost surface. Further, a nickel / gold (nickel base) layer (not shown) is formed by an electroless plating method at a portion of the wiring layer 21 or 24 where the solder resist is not formed to prevent corrosion. And a wiring board is cut out so that it may become a predetermined | prescribed external shape with a router processing machine. Thus, the component built-in wiring board according to the present embodiment can be obtained.

この実施形態では、製造設備として既存のものをほとんどそのまま使用することができ、配線板の製造コストの抑制につながる。また、最外の配線層21、24下の層間接続に導電性バンプ41、42を用いたので配線長を短くし電気的特性を向上して効率的に配線板としてレイアウトができる。また、比較的実装点数が多くなるチップ抵抗、チップコンデンサを内蔵できるので、現行設計ルールの緩和および一層の高密度実装が可能である。さらに、部品33をマウント・内蔵するための工程では、部品マウントでの不良発生が極めて小さく歩留まりのよい製造が可能である。加えて、内蔵された部品33の周りを絶縁層11、14が覆うように密着し、空隙の発生を防止するので信頼性の向上がなされる。   In this embodiment, the existing manufacturing equipment can be used almost as it is, which leads to a reduction in the manufacturing cost of the wiring board. In addition, since the conductive bumps 41 and 42 are used for the interlayer connection under the outermost wiring layers 21 and 24, the wiring length can be shortened, the electrical characteristics can be improved, and the wiring board can be efficiently laid out. In addition, since chip resistors and chip capacitors that have a relatively large number of mounting points can be incorporated, current design rules can be relaxed and higher-density mounting can be achieved. Further, in the process for mounting and incorporating the component 33, the occurrence of defects in the component mounting is extremely small, and manufacturing with a high yield is possible. In addition, since the insulating layers 11 and 14 are in close contact with each other around the built-in component 33 to prevent the generation of voids, the reliability is improved.

次に、本発明の別の実施形態に係る部品内蔵配線板について図7を参照して説明する。図7は、本発明の別の実施形態に係る部品内蔵配線板の模式的な構成を示す断面図である。図7において、すでに図1ないし図6において説明したものと同一の部位には同一の符合を付してある。以下重複を避けて説明する。   Next, a component built-in wiring board according to another embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view showing a schematic configuration of a component built-in wiring board according to another embodiment of the present invention. In FIG. 7, the same parts as those already described in FIGS. 1 to 6 are denoted by the same reference numerals. The following explanation will be made avoiding duplication.

この実施形態では、内側積層の絶縁層12、13に代えて絶縁層15、16、17を用い、それらの境界付近には配線層25、26が設けられている。また、配線層22、23と配線層25、26の4層でもそれらの隣接する配線層間の層間接続には導電性バンプ43、44、45が用いられている。部品33が半田36、37を介して接続される導電層34、35は、内側の配線層25、26とも直接的な電気的接続が可能となっている。なお、導電性バンプ43、44、45は、その製造工程として例えば図5で説明したようなスクリーン印刷を用いて形成することができる。   In this embodiment, insulating layers 15, 16, and 17 are used instead of the inner laminated insulating layers 12 and 13, and wiring layers 25 and 26 are provided in the vicinity of the boundaries between them. Further, conductive bumps 43, 44 and 45 are used for interlayer connection between the wiring layers 22 and 23 and the wiring layers 25 and 26 between the adjacent wiring layers. The conductive layers 34 and 35 to which the component 33 is connected via the solders 36 and 37 can be directly connected to the inner wiring layers 25 and 26. The conductive bumps 43, 44, and 45 can be formed by using screen printing as described in FIG.

この実施形態の利点は、部品33を内蔵するためのコア配線板の総厚(絶縁層15、16、17の総厚:例えば0.2mm)に対して、3つの導電性バンプ43、44、45で層間接続を行うことにより、すべての層間接続を導電性バンプによりなすようにしたことである。ここで、コア配線板を3つの導電性バンプ43、44、45により層間接続したのは、これより数が少ない場合には高いバンプ形成が必要となり効率的な導電性バンプの形成が難しいからである。このように3つ程度とすれば、0.2mm程度の総厚に対して必要な形成高さにはさほどの困難さは生じない。この結果、コア配線板は4層の配線層となり、全体として6層の配線層となっている。   The advantage of this embodiment is that, with respect to the total thickness of the core wiring board for incorporating the component 33 (total thickness of the insulating layers 15, 16, 17: 0.2 mm, for example), three conductive bumps 43, 44, By performing interlayer connection at 45, all interlayer connections are made by conductive bumps. Here, the reason why the core wiring board is interlayer-connected by the three conductive bumps 43, 44, 45 is that if the number is smaller than this, it is necessary to form a high bump and it is difficult to efficiently form the conductive bump. is there. If there are about three in this way, there will be no difficulty in the required formation height for a total thickness of about 0.2 mm. As a result, the core wiring board has four wiring layers, and has six wiring layers as a whole.

ただし、導電性バンプ43、44、45の形成高さをより高くすればより厚いプリプレグを貫通させることが可能であり、この結果、同じ部品33を内蔵するとしてもコア配線板の配線層の数を少なくすることができる。逆に、導電性バンプ43、44、45の形成高さをより低くすればより薄いプリプレグを用いることになり、この結果コア配線板の配線層の数を多くすることができる。   However, if the formation height of the conductive bumps 43, 44, 45 is made higher, a thicker prepreg can be penetrated. As a result, even if the same component 33 is incorporated, the number of wiring layers of the core wiring board Can be reduced. Conversely, if the formation height of the conductive bumps 43, 44, 45 is lowered, a thinner prepreg is used, and as a result, the number of wiring layers of the core wiring board can be increased.

図7に示す部品内蔵配線板を製造するには、図2(a)に示した両面銅張り板に代えて、絶縁板15、16、17、銅箔22a、23a、配線層25、26、導電性バンプ43、44、45を構成要素とする4層板を用いればよい。その後のプロセスは図2から図6に示したものと本質的に同様である。4層板を得るには、導電性バンプの印刷・形成、形成された導電性バンプにプリプレグを貫通(以上は図5を参照できる。)、貫通後に対向する側に銅箔(または配線層付きの絶縁層)を積層、というプロセスを繰り返せばよい。   In order to manufacture the component built-in wiring board shown in FIG. 7, instead of the double-sided copper-clad board shown in FIG. 2 (a), insulating plates 15, 16, 17, copper foils 22a, 23a, wiring layers 25, 26, A four-layer plate having conductive bumps 43, 44, and 45 as constituent elements may be used. The subsequent process is essentially the same as that shown in FIGS. In order to obtain a four-layer board, printing and formation of conductive bumps, penetrating the prepreg through the formed conductive bumps (see FIG. 5 above), copper foil (or wiring layer attached) on the opposite side after penetrating The insulating layer) may be laminated.

この実施形態では、先の実施形態と同様に製造設備として既存のものをほとんどそのまま使用することができ、配線板の製造コストの抑制につながる。また、部品33をマウント・内蔵するための工程では部品マウントでの不良発生が極めて小さく歩留まりのよい製造が可能であることも同様である。さらに、コア配線板における配線層を4つとすることにより、コア配線板の厚さを部品内蔵空間が確保しやすい寸法とし、配線層同士の層間接続をすべて導電性バンプ41〜45で行うことにより一層の高密度実装を実現することが可能である。   In this embodiment, as in the previous embodiment, the existing manufacturing equipment can be used almost as it is, leading to a reduction in the manufacturing cost of the wiring board. Similarly, in the process for mounting and incorporating the component 33, the occurrence of defects in component mounting is extremely small, and manufacturing with a high yield is possible. Furthermore, by using four wiring layers in the core wiring board, the thickness of the core wiring board is set to a dimension that facilitates securing the component built-in space, and all the interlayer connections between the wiring layers are performed by the conductive bumps 41 to 45. It is possible to realize higher density mounting.

本発明の一実施形態に係る部品内蔵配線板の模式的な構成を示す断面図および一部平面図。1 is a cross-sectional view and a partial plan view showing a schematic configuration of a component built-in wiring board according to an embodiment of the present invention. 本発明の一実施形態に係る部品内蔵配線板を製造するプロセスを模式的に断面(または一部平面)にて示す図。The figure which shows typically the process which manufactures the component built-in wiring board which concerns on one Embodiment of this invention in a cross section (or partial plane). 図2の続図であって、本発明の一実施形態に係る部品内蔵配線板を製造するプロセスを模式的に断面(または一部平面)にて示す図。FIG. 3 is a continuation diagram of FIG. 2, schematically showing a process of manufacturing a component built-in wiring board according to an embodiment of the present invention in a cross-section (or a partial plane). 図3の続図であって、本発明の一実施形態に係る部品内蔵配線板を製造するプロセスを模式的に断面(または一部平面)にて示す図。FIG. 4 is a continuation diagram of FIG. 3, schematically showing a cross-section (or a partial plane) of a process for manufacturing a component built-in wiring board according to an embodiment of the present invention. 本発明の一実施形態に係る部品内蔵配線板の製造に必要な配線板素材の構成を模式的に断面にて示す図。The figure which shows typically the structure of the wiring board raw material required for manufacture of the component built-in wiring board which concerns on one Embodiment of this invention in a cross section. 図4の続図であって、本発明の一実施形態に係る部品内蔵配線板を製造するプロセスを模式的に断面にて示す図。FIG. 5 is a continuation diagram of FIG. 4, schematically showing a process of manufacturing a component built-in wiring board according to an embodiment of the present invention in cross section. 本発明の別の実施形態に係る部品内蔵配線板の模式的な構成を示す断面図。Sectional drawing which shows the typical structure of the component built-in wiring board which concerns on another embodiment of this invention.

符号の説明Explanation of symbols

1a、1b…配線板素材、4…配線板素材(コア配線板)、11、12、13、14、15、16、17…絶縁層、21、22、23、24、25、26…配線層、21a、22a、23a、24a…銅箔、31、32…半田レジスト、33…電気/電子部品、34、35…導電層、36、37…半田、36a、37a…クリーム半田、41、42、43、44、45…導電性バンプ(接続形成後)、41a、42a…導電性バンプ(接続形成前)、51…貫通孔、52…めっき層、53…めっき層分断貫通孔、53A…バリ、61…支持部材、61a…粘着層。   DESCRIPTION OF SYMBOLS 1a, 1b ... Wiring board material, 4 ... Wiring board material (core wiring board), 11, 12, 13, 14, 15, 16, 17 ... Insulating layer, 21, 22, 23, 24, 25, 26 ... Wiring layer 21a, 22a, 23a, 24a ... copper foil, 31, 32 ... solder resist, 33 ... electrical / electronic component, 34,35 ... conductive layer, 36,37 ... solder, 36a, 37a ... cream solder, 41,42, 43, 44, 45 ... conductive bump (after connection formation), 41a, 42a ... conductive bump (before connection formation), 51 ... through hole, 52 ... plating layer, 53 ... plating layer dividing through hole, 53A ... burr, 61 ... support member, 61a ... adhesive layer.

Claims (9)

少なくとも上下両面に導電層を有するコア配線板を製造する工程と、
内蔵すべき電気/電子部品を位置させるべき空間が生じるように前記製造されたコア配線板にほぼ円形の貫通孔を形成する工程と、
前記形成された貫通孔の内表面を含むように導電層を形成する工程と、
前記上下両面の導電層をパターニングする工程と、
前記貫通孔に形成された前記導電層を内蔵すべき電気/電子部品の端子の数に応じて分断する工程と、
前記空間に電気/電子部品を位置させる工程と、
前記位置させられた電気/電子部品の前記端子と前記分断された導電層とを導電部材で接続する工程と、
前記導電部材により前記電気/電子部品が接続された前記コア配線板の上下両面それぞれに重ねてかつ前記電気/電子部品の周りを充填するように絶縁層を積層形成する工程と
を具備することを特徴とする部品内蔵配線板の製造方法。
Producing a core wiring board having conductive layers on at least upper and lower surfaces;
Forming a substantially circular through hole in the manufactured core wiring board so as to create a space in which an electric / electronic component to be incorporated is to be located;
Forming a conductive layer so as to include the inner surface of the formed through hole;
Patterning the upper and lower conductive layers;
Dividing the conductive layer formed in the through-hole according to the number of terminals of the electrical / electronic component to be incorporated;
Positioning electrical / electronic components in the space;
Connecting the terminal of the positioned electrical / electronic component and the divided conductive layer with a conductive member;
Forming an insulating layer so as to overlap the upper and lower surfaces of the core wiring board to which the electric / electronic component is connected by the conductive member and to fill the periphery of the electric / electronic component. A method for producing a component-embedded wiring board.
前記形成された貫通孔の内表面を含むように導電層を形成する前記工程が、無電解めっきにより下地となる導電層を形成する工程と、前記形成された下地を種に用いて電解めっきにより上層となる導電層を形成する工程とを有することを特徴とする請求項1記載の部品内蔵配線板の製造方法。   The step of forming a conductive layer so as to include the inner surface of the formed through-hole includes a step of forming a conductive layer as a base by electroless plating, and electrolytic plating using the formed base as a seed. 2. A method of manufacturing a component built-in wiring board according to claim 1, further comprising a step of forming an upper conductive layer. 内蔵すべき電気/電子部品を位置させるべき空間が生じるように前記製造されたコア配線板にほぼ円形の貫通孔を形成する前記工程が、ドリリングまたは金型打ち抜きによりなされることを特徴とする請求項1記載の部品内蔵配線板の製造方法。   The step of forming a substantially circular through-hole in the manufactured core wiring board so as to create a space in which an electric / electronic component to be incorporated is located is performed by drilling or die punching. A manufacturing method of a component built-in wiring board according to Item 1. 前記空間に電気/電子部品を位置させる前記工程が、前記空間からのぞく前記コア配線板の下位置に支持部材をあてがい、前記支持部材上に前記電気/電子部品を位置させてなされることを特徴とする請求項1記載の部品内蔵配線板の製造方法。   The step of positioning the electrical / electronic component in the space is performed by placing a support member below the core wiring board except the space and positioning the electrical / electronic component on the support member. A method of manufacturing a component built-in wiring board according to claim 1. 前記位置させられた電気/電子部品の前記端子と前記分断された導電層とを導電部材で接続する前記工程が、前記導電部材として半田または導電性樹脂が用いられることを特徴とする請求項1記載の部品内蔵配線板の製造方法。   The soldering or conductive resin is used as the conductive member in the step of connecting the terminal of the placed electrical / electronic component and the divided conductive layer with a conductive member. The manufacturing method of the component built-in wiring board of description. 前記貫通孔に形成された前記導電層を内蔵すべき電気/電子部品の端子の数に応じて分断する工程が、ドリリング、金型打ち抜き、またはレーザ加工によりなされることを特徴とする請求項1記載の部品内蔵配線板の製造方法。   2. The step of dividing the conductive layer formed in the through hole in accordance with the number of terminals of an electrical / electronic component to be built is performed by drilling, die punching, or laser processing. The manufacturing method of the component built-in wiring board of description. 少なくとも上下両面に導電層を有するコア配線板を製造する前記工程が、配線層を4つ有するコア配線板を製造するものであり、かつ、これらの配線層同士の電気的接続が導電性バンプでなされるように製造されることを特徴とする請求項1ないし6のいずれか1項記載の部品内蔵配線板の製造方法。   The step of manufacturing the core wiring board having conductive layers on at least the upper and lower surfaces is to manufacture a core wiring board having four wiring layers, and the electrical connection between these wiring layers is a conductive bump. The method of manufacturing a component built-in wiring board according to claim 1, wherein the method is manufactured as described above. 板厚み方向に形成されかつ板上下面には表出せずに埋設されている導電層と、
端子を有し、前記埋設された導電層に前記端子が対向するように板内埋設された電気/電子部品と、
前記埋設された電気/電子部品の前記端子と前記導電層との間隙に設けられ、前記導電層の横方向端部に接触せずに前記端子と前記導電層とを電気的・機械的に接続する接続部材と、
前記埋設された電気/電子部品の外表面のうち前記接続部材に接続される部位以外を覆いかつ前記電気/電子部品の板厚み方向上下に密着するように設けられた上下2つの絶縁層と
を具備することを特徴とする部品内蔵配線板。
A conductive layer formed in the thickness direction of the plate and embedded in the upper and lower surfaces of the plate without being exposed; and
An electrical / electronic component having a terminal and embedded in a plate so that the terminal faces the embedded conductive layer;
Provided in the gap between the terminal of the embedded electrical / electronic component and the conductive layer, and electrically and mechanically connect the terminal and the conductive layer without contacting the lateral end of the conductive layer. A connecting member to be
Two upper and lower insulating layers provided so as to cover a portion of the outer surface of the embedded electric / electronic component other than the portion connected to the connecting member and to be in close contact with the electric / electronic component in the plate thickness direction. A component built-in wiring board characterized by comprising:
前記埋設された導電層に電気的に接続可能な複数の板方向導電層と、
前記複数の板方向導電層を層間接続する導電性バンプによる層間接続体と
をさらに具備することを特徴とする請求項8記載の部品内蔵配線板。
A plurality of plate-direction conductive layers that can be electrically connected to the embedded conductive layers;
The component built-in wiring board according to claim 8, further comprising: an interlayer connection body formed of conductive bumps for interlayer connection between the plurality of plate direction conductive layers.
JP2003302391A 2002-10-08 2003-08-27 Manufacturing method of component built-in wiring board, component built-in wiring board Expired - Fee Related JP4279089B2 (en)

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JP2003302391A JP4279089B2 (en) 2003-08-27 2003-08-27 Manufacturing method of component built-in wiring board, component built-in wiring board
US10/530,518 US7242591B2 (en) 2002-10-08 2003-10-06 Wiring board incorporating components and process for producing the same
KR1020057005949A KR101046077B1 (en) 2002-10-08 2003-10-06 Manufacturing method of parts-embedded wiring board, manufacturing method of parts-embedded wiring board
PCT/JP2003/012749 WO2004034759A1 (en) 2002-10-08 2003-10-06 Wiring board incorporating components and process for producing the same
US11/785,607 US7345888B2 (en) 2002-10-08 2007-04-19 Component built-in wiring board and manufacturing method of component built-in wiring board
US12/007,924 US7644497B2 (en) 2002-10-08 2008-01-17 Component built-in wiring board and manufacturing method of component built-in wiring board

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049457A (en) * 2004-08-03 2006-02-16 Dt Circuit Technology Co Ltd Wiring board with built-in parts and manufacturing method thereof
JP2008277568A (en) * 2007-04-27 2008-11-13 Victor Co Of Japan Ltd Electronic component housing substrate and manufacturing method therefor
US8400776B2 (en) 2006-07-28 2013-03-19 Dai Nippon Printing Co., Ltd. Multilayered printed wiring board

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006049457A (en) * 2004-08-03 2006-02-16 Dt Circuit Technology Co Ltd Wiring board with built-in parts and manufacturing method thereof
US8400776B2 (en) 2006-07-28 2013-03-19 Dai Nippon Printing Co., Ltd. Multilayered printed wiring board
US8942003B2 (en) 2006-07-28 2015-01-27 Dai Nippon Printing Co., Ltd. Multilayered printed wiring board
JP2008277568A (en) * 2007-04-27 2008-11-13 Victor Co Of Japan Ltd Electronic component housing substrate and manufacturing method therefor

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