JP2005064217A - Method of erasing nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of erasing a nonvolatile semiconductor memory which executes the erasing operation at a high reliability, using the substrate hot electron injection operable with a lower voltage than the electron injection through an FN tunnel. <P>SOLUTION: A voltage of about -1 V to a bottom n-well 11 and a voltage of 3.3 V is applied to the source and the drain 13, 14 with a p-well 12 set to 0 V, resulting in an acceleration voltage of 4.3 V for substrate hot electrons. A voltage of 8 V is applied to a gate electrode 18 to result in a pull-in voltage of 4.7 V for a charge trap layer 16. Thus, the pull-in voltage is set to be higher than the acceleration voltage, thereby enabling a high reliability erasing operation even in the substrate hot electron injection. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an erasing method for erasing bit data written in a nonvolatile semiconductor memory device.

  In recent years, a charge trap layer such as a low-conductivity nitride film is formed in place of the floating gate of a conventional flash memory, and charges are separately injected into the source side and the drain side of the charge trap layer. There has been proposed a nonvolatile semiconductor memory that can record 2-bit information in a cell (for example, Patent Document 1).

  In other words, in this nonvolatile semiconductor memory, it is a partial region on the electron emission (source) side in the channel region that affects whether or not it is turned on when a voltage is applied between the source and drain. 1 bit is stored by injecting charges into the source side region of the charge trap layer. In addition, if the electrodes are connected in reverse, the drain becomes the electron emission side. Therefore, by injecting charges into the drain side region of the charge trap layer, the drain is grounded and a negative voltage (Vdr) is applied to the source. 1 bit read by the connection is stored. In this way, charges are separately injected into partial regions on both sides of the charge trap layer, and at the time of reading, the direction of the applied voltage is reversed, that is, as source / drain in two regions facing each other across the channel region By reversely reading the charge accumulated on both sides of the charge trapping layer by reversing the role of, it is possible to record / read 2-bit information.

  The configuration of this nonvolatile semiconductor memory and the data write / read operation will be briefly described with reference to FIG. As shown in the figure, a non-volatile semiconductor memory (memory cell) 100 includes a pair of n-type regions 102 and 103 functioning as source / drains formed in a surface region of a p-type silicon semiconductor substrate 101, and the n A tunnel oxide film 104, a charge trap layer 105, a silicon oxide film 106, and a gate electrode 107 are formed on the channel region between the mold regions 102 and 103. Here, the charge trap layer 105 is composed of a silicon nitride film.

  The nonvolatile semiconductor memory 100 traps electrons independently in the left and right program regions 108 and 109 at both ends of the charge trap layer 105, and charges are injected into the left and right program regions 108 and 109, respectively. Or (program / erase), it is possible to record data of 1 bit each and 2 bits in total. Charge injection (programming) is performed by injecting charges into the charge trap layer 105 through the tunnel oxide film 104. Charge injection is performed by channel hot electrons (CHE).

  For example, when programming the right program area 109, the source is set to 0V, the drain is set to about 5V, a potential difference is generated between the source and the drain, and a high voltage (about 10V) is applied to the gate 107 so that the source / drain is connected. The channel 110 is formed. Here, the range l1 of the formed channel 110 has the same potential and no electric field is generated. In the range l2 where the channel 110 is not formed, an electric field is generated due to the potential difference between the source and the drain. Therefore, channel hot electrons (CHE) are generated in this range l2, and electrons are trapped in the right program region 109. .

  When reading the bit data in the right program area 109, a read voltage Vgread is applied to the gate 107, and a voltage Vdread in the opposite direction to that in the program is applied between the source and drain. Note that the absolute voltage value at this time is lower than that at the time of programming, and is about Vdread = 1.5V and Vgread = 3V. At this time, when electrons are trapped in the right program region 109, a channel is not formed in the lower layer of the program region 109 due to the increase in threshold value due to this charge, and the source / drain is not turned on. On the other hand, when electrons are not trapped in the program region 109, a channel is formed between the source and the drain to turn on. As described above, by using the n-type region on the side of the program region 109 as a source and the opposite n-type region as a drain, the bits in the program region 109 can be read.

  Even if electrons are trapped in the program region 109, when a voltage is applied in the same direction as during programming, the source / drain is turned on due to depletion under the 109 region near the drain. The presence or absence of charge traps in the program area 109 does not affect the read operation.

  The program and bit data can be read into the left program area 108 in the same manner as described above, and as described above, the charge injection into the left and right program areas can be performed independently. In addition, since the presence or absence of charge trapping in the other program area does not affect the read operation for either one of the left and right program areas, 1-bit data is recorded in the left and right program areas in the one memory cell.・ Reading is possible.

  In the case of a program method in which electrons (negative charges) are injected into the program area 109 as described above, erasing (erasing) is performed by extracting electrons. Memory erasure is not performed for each cell, but for the entire chip or block (generally 512 bits). However, since there is variation in the characteristics of each memory cell, erasure processing is performed simultaneously. In such a case, variations occur in the progress of charge erasure. When the negative charge is extracted from the charge storage layer, the threshold voltage decreases. However, due to the variation, the negative charge is excessively erased and a positive charge is charged, resulting in a depletion memory cell (over erase). there were.

In order to cope with this problem and to improve the reliability of writing and erasing, holes (positive charge) are injected into the charge storage layer for programming, and electrons (negative charge) are injected for erasing. A non-volatile semiconductor memory cell has been proposed (Non-Patent Document 1).
US Pat. No. 5,768,192 0-7803-7463-X / 02 / $ 17.00 (C) 2002 IEEE

  According to the above non-patent literature, since the reliability of data retention characteristics is low when substrate hot electron injection is used as the erasing operation, it is proposed to perform erasing by electron injection through an FN (Fowler Nordheim) tunnel. However, the electron injection operation by the FN tunnel requires a high voltage (+12 V in Non-Patent Document 1 above), and a transistor handling such a high voltage requires a thick gate oxide film. Performance is inferior. In addition, there is a problem that the power consumed by the booster circuit for generating such a high voltage from a power supply voltage (for example, +3.3 V) supplied from the outside increases.

  The present invention provides a method for erasing a nonvolatile semiconductor memory device that uses substrate hot electron injection that can be operated at a lower voltage than electron injection through an FN tunnel and that can perform a highly reliable erase operation. For the purpose.

In the present invention, a pair of n-type diffusion layer regions formed on the surface of a p-type well at a predetermined interval and a channel region sandwiched between the pair of n-type diffusion layer regions are formed via a tunnel oxide film. A non-conductive charge trap layer and a gate electrode formed above the charge trap layer with an insulating film interposed therebetween,
A method of performing programming by trapping positive charges in the charge trapping layer and erasing by injecting negative charges by substrate hot electron injection,
At the time of the substrate hot electron injection, the potential difference between the gate electrode and the pair of n-type diffusion layer regions is determined so that the n is formed in the pair of n-type diffusion layer regions and the p-type well or adjacent to the p-type well. It is characterized in that it is set larger than the potential difference with the type emitter electrode.

  The present invention is characterized in that a bottom n-type well formed around and at the bottom of the p-type well is used as the emitter electrode.

  The present invention is characterized in that the potential of the bottom n-type well used as the emitter electrode is a ground potential.

  According to the present invention, the erase operation can be performed at a low operating voltage because the memory cell written by injecting the positive charge into the non-conductor charge trap layer can be erased by the injection of the substrate hot electrons. can do. At this time, since the pull-in voltage (potential difference between the n-type diffusion layer region (source and drain) and the gate electrode) is made larger than the acceleration voltage (potential difference between the n-type diffusion layer region and the emitter), reliability is improved. A high erase operation can be realized.

  Further, by using the bottom n-well as the emitter electrode, the whole can be erased uniformly.

  Further, in this case, since the bottom n-well is set to the ground potential, no current flows between the p-type substrate and the erasure efficiency, which is generally grounded.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a structural diagram of an N-channel MONOS memory cell according to an embodiment of the present invention. Double wells (bottom n-type well 11 and p-type well 12) are formed near the surface of p-type semiconductor substrate 10, and an n-type diffusion region is formed near the surface of p-type well 12 with a predetermined interval. 13 and 14 are formed. During operation (reading) of the memory cell, one of the n-type diffusion regions 13 and 14 functions as a source and the other functions as a drain. As will be described later, the memory cell is a program for writing bit data. Since there are two regions on the left and right, which one is responsible for the function of the source or drain changes depending on which one is read out.

  A region located between the two n-type diffusion regions 13 and 14 in the p-type well 12 is a channel region 20. A three-layer ONO film and a gate electrode 18 are formed above the channel region 20 so as to cover the channel region 20. The ONO film comprises a tunnel oxide film 15 made of silicon oxide, a charge trap layer 16 made of silicon nitride, which stores injected charges (electrons), and an insulating film 17 made of silicon oxide. Each of these three layers has a thickness of about 5 to 8 nm. The gate electrode 18 is made of polysilicon.

  When a memory cell array is constituted by the memory cells having this configuration, the gate electrodes 18 of the memory cells in the X direction are formed integrally to serve as a word line. For example, as shown in FIG. 2 or FIG. It becomes a composition.

  In the N-channel MONOS memory cell having the above structure, a nitride film is used as the charge trap layer 16. Since the nitride film has low electrical conductivity, the trapped charge does not move within the film and remains in the trapped position.

The operation of the N-channel MONOS memory cell having the above structure will be described.
Charge (electron) injection (writing: programming) into the charge trap layer 16 is performed by applying a positive and negative high voltage between the gate electrode 18 and one of the n-type diffusion regions 13 or 14. Band tunneling induced hot hole). In the BBHH injection, holes are injected into the charge trap layer 16 from the vicinity of the n-type diffusion region 13 or 14 and trapped in the left program region 16L or the right program region 16R in the charge trap layer 16. The trapped charge does not move to the other side.

  That is, depending on which n-type diffusion regions 13 and 14 are applied with a negative high voltage at the time of writing, it is possible to select which of the left and right program regions 16L and R is to be written. At the time of reading (as will be described later), it is possible to select which of the left and right program areas 16L and R is to be read depending on which of the n-type diffusion areas 13 and 14 functions as a source / drain.

  Therefore, the left and right program areas 16L and R function as independent program areas, respectively, whereby it is possible to store 2-bit data in one memory cell in this P-channel MONOS memory cell.

  Hereinafter, the writing and reading operations will be described in detail. Here, writing and reading operations to the left program area 16L will be described.

  Charge injection into the charge trap layer 16 is caused by applying a high negative voltage (Vgw) to the gate electrode 18 and a high electric field in the depletion layer when a positive high voltage (Vdw) is applied to the n-type diffusion region 13. BBHH (Band-to-Band tunneling induced Hot Hole) injection is used. At this time, the drain 14 is opened or grounded, and the n-type well 11 is grounded. Vgw is preferably about −10V and Vdw is preferably about 5V.

  With this potential arrangement, a depletion layer region 21 is generated at the junction surface between the n-type diffusion region 13 and the n-type well 11 as shown in FIG. 3, and band-to-band tunneling ( Holes (holes) due to BTBT are generated. This hole is accelerated by a strong electric field in the depletion layer region 21 and becomes a hot hole having high energy. Part of it is attracted to the negative voltage applied to the gate electrode 18, gets over the tunnel oxide film 15, and is injected into the charge trap layer 16.

This charge injection is performed in a state where the n-type diffusion regions 13/14, that is, the source / drain are turned off. Therefore, by applying an appropriate voltage (about 5 V) as Vdw, about 10 ⁻² is applied. Injection efficiency can be ensured.

  The charge due to the BBHH injection using the n-type diffusion region 13 is held in the left program region 16L of the charge trap layer 16.

  Here, the N-channel MONOS memory cell (FET) is turned on when a positive voltage is applied to the gate electrode, but positive charge is trapped in the charge trap layer between the gate electrode and the channel region (writing: programming). As a result, the threshold voltage Vth of the gate electrode apparently decreases as shown in FIG. Here, the threshold distribution of the bit (memory cell) to which writing has been performed is narrower than the threshold distribution of the bit to which erasing (erasing) has been performed, because writing is performed for each bit. Writing can be performed while finely adjusting the threshold value of each bit. However, since erasing is performed in the whole memory or in units of blocks, adjustment cannot be made for each bit, resulting in variations. Note that erasing is performed by injecting electrons (negative charges) into the charge trap layer 16, thereby increasing the threshold value of the memory cell.

  Thus, in the N-channel MONOS memory cell programmed by hole injection, erasing is performed in the direction in which the threshold value rises. Therefore, even if the threshold value varies, the phenomenon of over-erasing cannot occur.

  In the above configuration, the p-type well 12 and the bottom n-type well 11 are partitioned with about 512k memory cells as one block, and erasing is performed in units of this block.

  In order to read the left program area 16L written by the above operation, the n-type diffusion area 13 is grounded and Vdr is applied to the n-type diffusion area 14 as shown in FIG. Vdr is preferably about 1.5 to 2V. That is, at this time, the n-type diffusion region 13 functions as a source, and the n-type diffusion region 14 functions as a drain. In the following description of the read operation, the left n-type diffusion region 13 is referred to as a source, and the right n-type diffusion region 14 is referred to as a drain.

  In this state, a read voltage Vgr is applied to the gate electrode 18. The gate voltage Vgr is set to be a voltage between the threshold value Vth (e) at the time of erasing and the threshold value Vth (p) at the time of writing shown in FIG. Thereby, when a gate voltage is applied, ON / OFF between the source and the drain is determined depending on whether or not the left program region 16L is written. That is, it is possible to read bit data (left bit) indicating whether or not the left program area 16L is written depending on whether or not the source / drain is turned on.

  When the left program area 16L is written (when charge is trapped), the positive charge accumulated in the left program area 16L is added to the threshold when the read voltage Vgr is applied to the gate electrode 18. When the value voltage is exceeded, the source 13 side of the channel region 20 becomes a positive potential, a channel is formed, and the source / drain is conducted and turned on. The bit data at this time is set to “0”.

  On the other hand, when the left program region 16L is not written (when charge is not accumulated), the channel region 20 between the source and drain does not become a positive potential even if the read voltage Vgr is applied to the gate electrode. A channel is not formed in the region 20. For this reason, the source / drain is not conducted and remains off. The bit data at this time is “1”.

  In the read operation of the left program area 16L, if the right program area 16R is not written, it is natural that the read result (ON / OFF) of the left program area 16L is not affected. Even if the right side program region 16R is written, the channel region 20 on the drain side is depleted, so that conduction is maintained, and the reading result of the left side program region 16L is not affected.

  Next, an erase operation for removing charges from the charge trap layer 16 will be described. The erase operation is performed for the entire memory or for each block. Here, the erase operation for one memory cell will be described.

  Erasing is performed by substrate hot electron injection. FIG. 6 is a diagram for explaining an erasing operation by substrate hot electron injection. In this erasing operation, a high voltage (about 10 V) is applied to the gate electrode 18 so that a strong electric field is generated in the charge trap layer 16. As a result, electrons trapped in the shallow energy level of the charge trap layer 16 are extracted to the gate electrode 18 side, and the erase operation is performed only with the electrons trapped in the deep energy level.

In addition, this allows electrons to be accelerated and converted to hot electrons by the high voltage of the gate 18 without applying a very high voltage to the n-well 11 and the p-well 12. The potential distribution of the erase operation by the substrate hot electron injection is as follows. A negative positive voltage Vge of about 10 V is applied to the gate electrode 18, a positive voltage V _{2 of} about 3.3 V is applied to the source 13 and drain 14, and a positive potential V _B , n of about +1 V is applied to the p-type well 12. The potential V ₁ of the mold well 11 is 0V. Since the p-type substrate 10 is grounded to GND, this potential arrangement prevents a leak current from flowing from the emitter to the substrate side. And the relationship between each voltage is
| Vge−V ₂ | >> | V ₂ −V ₁ |
To be. By applying the voltage in this manner, the p-type well 11, the n-well 12 and the n-type diffusion regions (source / drain) 13, 14 function as npn bipolar transistors, and the n-type well 11 moves from the source 13 to the drain 14. Electrons are emitted toward it. On the other hand, since a positive high voltage is applied to the gate electrode 18, some of the electrons are attracted toward the gate electrode and pass through the tunnel oxide film 15 and enter the charge trap layer 16. The positive charge of the hole is canceled by the negative charge of the electrons, and as a result, the charge of the charge trap layer 16 is erased.

  This erase operation is performed in common for the write bit and the left bit in one block (512k) of memory cells.

  Here, voltage application conditions for left bit program, read, write bit program, read, and erase (erase) are collectively shown in FIG.

  Here, a memory cell array in which a plurality of the memory cells are arranged will be described with reference to FIGS. This memory cell array has a VGA (virtual ground array) type connection form. 8A is a cross-sectional perspective view of the memory cell array, FIG. 8B is a diagram showing the configuration of one of the memory cells, and FIG. 9 is an equivalent circuit thereof. In FIG. 8A, the broken line is a virtual line indicating the boundary of each memory cell. Further, the equivalent circuit of FIG. 10 shows the voltage applied to each word line and column line at the time of writing.

  A plurality of n-type linear regions 30 in the Y direction are formed in stripes at predetermined intervals on the surface of the p-type well 12. This n-type linear region 30 is formed across the boundary of the memory cell, and one n-type linear region 30 is n-type diffusion regions 13 and 14 (source, As well as the column line. This column line functions as both a bit line and a source line depending on the connection with the Y gate.

  The word line 31 is formed in a stripe shape in the X direction so as to be orthogonal to the n-type linear region 30 and also serves as the gate electrode 18 above the channel region 20 of each memory cell. An ONO film 32 is formed between the word line 31 and the semiconductor substrate (n-type diffusion regions 13 and 14 and channel region 20). The ONO film 32 is also formed continuously in the X direction, like the word line 31. Of the ONO film 32, the section above the channel region 20 functions as the tunnel oxide film 15, the charge trap layer 16 and the insulating film 17, and the section above the n-type diffusion regions 13 and 14 functions as an interlayer insulating film.

  In this embodiment, the ONO film 32 is formed in a stripe shape in the X direction like the word line 31. However, since the ONO film 32 is not a conductive film, it may be formed in the entire memory cell array. By doing so, the processing process for etching the ONO film 32 in a stripe shape can be omitted.

  Thus, in this memory cell array, one n-type linear region (column line) 30 serves as the n-type diffusion regions 13 and 14 of two memory cells adjacent in the X direction, so that the memory configuration is simplified. High integration is possible. Further, in the memory cell array having this configuration, the following processing is necessary when writing to each memory cell.

  At the time of writing to the left program area 16L (left bit) of the target memory cell, as shown in FIG. 3, Vgw is applied to the word line 30 (WLn) serving as the gate electrode 18 of the memory cell, and the memory cell BBHH implantation is performed by applying Vdw to the column line 31 that becomes the n-type diffusion region (source) 13 of the memory cell. As described above, the n-type diffusion region (source) 13 of the memory cell that performs this writing is Since the word line 31 to which the Vgw is applied is shared with the n-type diffusion region (drain) 14 of the adjacent memory cell, writing is performed in the left program region 16L of the target memory cell as it is. At the same time, writing is also performed in the right program area 16R (write bit) of the memory cell adjacent to the left.

  Therefore, in this embodiment, as shown in FIGS. 9 and 10, an n-type diffusion which is an n-type diffusion region facing the n-type diffusion region to which Vdw is applied in the memory cell on the left side of the memory cell to be written. A write blocking voltage is applied to the region 13 to prevent writing to the memory cell (the write bit) on the left side. In FIG. 10, a write inhibition voltage that is about half of the write voltage Vdw (Vdw / 2) is applied to the n-type diffusion region 13 of the memory cell on the left side.

  As a result, the lateral electric field of the left and right n-type diffusion regions 13 and 14 can be relaxed in the left adjacent memory cell, and the occurrence of BBHH can be suppressed, and the right program region 16R of the left adjacent memory cell can have BBHH. It is possible to prevent writing by injection.

  In the memory cell on the left side having the n-type diffusion region 14 shared with the n-type diffusion region 13 to which Vdw / 2 is applied, a depletion layer is formed near the boundary between the n-type diffusion region 14 and the channel region. Although it occurs, since the strength of the electric field is Vdw / 2, generation of BBHH is suppressed.

  In FIG. 10, a voltage of about Vdw / 2 is applied to the memory cell adjacent to the memory cell to be written, but the method of applying the write blocking voltage is not limited to this. For example, as shown in FIG. 11A, Vdw is applied to all the column lines on the program area side (left side in the figure) where the target memory cell is written to connect the depletion layer, resulting in BBHH. You may make it disappear.

  Further, as shown in FIG. 11B, a write inhibition voltage that gradually decreases may be applied to a plurality of column lines on the program area side (left side in the figure) in which the target memory cell is written. In the example shown in the figure, Vdw is applied to the target column line i, 2 Vdw / 3 is applied to the left column line i-1, and Vdw / 3 is applied to the left column line i-2. Applied. Thereby, the strength of the electric field generated in the memory cell on the left side of the column line i-2 can be reduced to Vdw / 3, and the generation of BBHH can be reliably prevented.

  In FIGS. 9 to 11, the case where data is written to the left program area 16 </ b> L (left bit) of the target memory cell has been described. However, when data is written to the right program area 16 </ b> R (right bit), the left and right are reversed. Similar processing is performed.

  FIG. 12 is a diagram showing a voltage application state to each word line and column line at the time of reading in the VGA type memory cell array. At the time of reading, as shown in FIG. 4, among the column lines (n-type linear regions) 30 serving as the gate / drain of the target memory cell, the column line on the side for reading bit data (left bit / right bit) ( Vdr (1.5 to 2 V) is applied to the drain), and the opposing column line (source) is grounded. Column lines other than the target memory cell are left open. In addition, a read voltage Vgr (5 V) is applied to the word line that becomes the gate electrode of the target memory cell. Bit data is read depending on whether the gate / drain is turned on in this state.

  8 to 12, a VGA (virtual ground array) type memory cell array in which the n-type diffusion region of the memory cell also serves as a column line has been described. In the following, the n-type diffusion region is formed in an island shape. The memory cell array connected to the metal column lines formed in the upper layer by contact plugs will be described. In this memory cell array, the column lines to be the bit lines and source lines are made of metal, so that the resistance can be reduced, and high-speed writing and high-speed reading are possible. Although the structure of each memory cell is different, the connection configuration of the memory cell array is the same VGA connection as that shown in FIGS.

  FIG. 13 is a plan view showing the structure of the memory cell array, and FIG. 14 is an X1-X1 sectional view, an X2-X2 sectional view, and a YY sectional view in the plan view. FIG. 17 is an equivalent circuit thereof. On the surface of the p-type well 40, an n-type diffusion region 41 having an island shape in plan view is formed in a matrix. The memory cell S is formed between two island-shaped n-type diffusion regions 41 adjacent in the Y direction (up and down), and a region between these is a channel region 42. Therefore, each n-type diffusion region 41 also serves as the n-type diffusion regions 13 and 14 (source and drain: see FIG. 1) of two memory cells S adjacent in the Y direction.

  An ONO film 43 and a word line 44 are formed so as to cover a plurality of channel regions 42 arranged in the X direction (left and right). A plurality of column lines 45 are formed in stripes at the same interval as the n-type diffusion region 41 in the Y direction. The column line 45 is formed in the upper layer, and is connected to the n-type diffusion region 41 through the lower intermediate wiring film 46. The column line 45 and the intermediate wiring film 46 are connected by a via hole 47, and the intermediate wiring film 46 and the n-type diffusion region 41 are connected by a contact plug 48. The n-type diffusion regions 41 in one row arranged in the Y direction are alternately connected to the left and right column lines in the row.

  When a memory cell having this structure is manufactured, a process of implanting n-type ions by self-alignment after forming a metal word line 44 is employed. At this time, an n-type diffusion region is connected in the X direction. In order to avoid this, stripe-shaped trench isolation layers 40 in the Y direction are formed in advance at a pitch in the X direction of the memory cells.

  In this embodiment, the ONO film 43 is formed in a stripe shape like the word lines 44, but the ONO film 43 may be formed in the entire memory cell array. The column line 45 is formed so as to pass through the center of the intermediate wiring film 46, but may not be in the center as long as it passes through the intermediate wiring film 46.

  Since one memory cell is composed of two n-type diffusion regions 41 adjacent in the Y direction as sources and drains as described above, a memory cell group in one column is selected by two continuous column lines. Further, by selecting one word line, one memory cell can be selected.

  In the memory cell arrays of FIGS. 13 and 14, the column line 45 and the island-shaped n-type diffusion region 41 are connected via the intermediate wiring film 46. FIG. 15 and FIG. An embodiment in which the contact plug 147 is directly lowered with respect to the n-type diffusion region 141 is shown.

  In FIG. 15, column lines 45 and word lines 46 are indicated by broken lines, and trench isolation 140, n-type diffusion region 141 and channel region 42 on the substrate are indicated by solid lines and hatching. In this embodiment, the n-type diffusion region 141 is formed to have a length of 3F in the X direction in the same manner as the intermediate wiring film 46 of FIG. 13, and the contact plug 147 directly from the column line 45 is formed in the center of the n-type diffusion region 141. Has been lowered.

  Even in the memory cell array of this shape, it is not necessary to form the column line 45 so as to pass through the center of the column line 45 as long as it is above the corresponding n-type diffusion region 141.

  In order to form the n-type diffusion region 141 having the above-described shape by self-alignment, the trench isolation 140 is not formed in the entire Y direction in parallel with the column line 45, but at the portion where the n-type diffusion region 141 is formed. 15 is formed in the shape of a broken brick as shown in FIG. 15 and a word line 44 is formed thereon, and then n-type impurities are implanted.

  Note that the memory cell array having this configuration also has an equivalent circuit as shown in FIG. 17, similar to those shown in FIGS.

  In the memory cell arrays shown in FIGS. 13 to 17, one column line 45 is connected to the word line direction (X direction) via the via hole 47, the intermediate wiring film 46, the contact plug 48, or the contact plug 147. ) Adjacent to the n-type diffusion region 41, when Vgw is applied to one word line 44 and Vdw is applied to one column line at the time of writing, it is adjacent to other than the target memory cell. Writing is also performed on the memory cell. Therefore, in order to prevent this, as in the memory cell of the first embodiment, a write blocking voltage is applied to the n-type diffusion region 41 (adjacent column line 45) on the opposite side of the adjacent memory cell. To do. The method of applying the write blocking voltage may be the same as the method of applying in the memory cell array shown in FIGS.

  Note that the application of the write inhibition voltage described in FIGS. 9 to 12 is a process necessary when both the left and right program areas 16L and R of each memory cell are used as storage areas. When 1 bit / cell is stored using only one program area, it is not necessary to apply the write block voltage. This is because, as described above, in the reading of the target program area, the program / unprogram in the opposite program area does not affect the read result.

  Even when both of the memory cell program areas 16L and R are used as storage areas, the column lines and n-type diffusion areas of the memory cells adjacent in the X direction are separated as shown in FIGS. By configuring the array, it is possible to eliminate the write blocking voltage.

  In the memory cell array of FIG. 18, each memory cell is formed obliquely as shown by a broken line in FIG. 18, and a left n-type diffusion region 41L, a right n-type diffusion region 41R, and a channel region 42 are formed in the memory cell. Is formed. The lower left n-type diffusion region 41 is connected to the left column line 45L with a contact plug 48, and the upper right n-type diffusion region 41R is connected to the right column line 45R with a contact plug 48. In this memory cell array, regions other than the memory cells indicated by broken lines in the figure are insulating layer regions. The n-type diffusion region and the column line are not shared on the surface of the semiconductor substrate and in the memory cells adjacent in the X direction, and a high voltage applied to the column line at the time of writing is also applied to the adjacent memory cell. There is nothing.

  In this embodiment, in the plan view of the memory cell array, each memory cell is laid out from the upper right to the lower left, but conversely, it may be formed from the upper left to the lower right.

  In the case of the memory cell array having the structure shown in FIG. 8, as shown in FIG. 20, n-type diffusion regions (n-type linear regions) 13 and 14 of adjacent memory cells are separately formed on the left and right sides. By isolating with the trench-like insulating film, the equivalent circuit becomes as shown in FIG. 19, and the write blocking voltage can be made unnecessary.

  In the memory cell array of each of the above embodiments, the word line is formed of a polysilicon film. However, the resistance can be further reduced by forming a cobalt film and forming a silicide.

  FIG. 21 shows an example in which the memory cell has a three-dimensional structure. The channel region 20 between the n-type linear regions 13 and 14 formed in a stripe shape is trench-etched to form a groove shape, and a word also serving as an ONO film 52 orthogonal to the trench (groove) and a gate electrode A line 53 is formed along the side wall and bottom surface of the trench. As a result, even if the distance between the n-type linear regions 13 and 14 is shortened, the channel region 20 is formed around the trench, so that high integration in the X direction can be achieved while ensuring the channel length.

  FIG. 22 is a diagram showing the structure of a memory cell array having a structure in which the trench etching of FIG. 21 is performed deeper and an n-type diffusion region is formed on the bottom of the trench. In this configuration, the n-type diffusion regions (source and drain) are formed on the surface of the semiconductor substrate and the bottom surface of the trench, and the channels are formed above and below the semiconductor substrate 11, so that the degree of integration in the X direction is extremely high. It becomes possible.

The figure which shows the basic structure of the p channel MONOS memory cell which is 1st Embodiment The figure which shows an example of the processed shape of the p channel MONOS memory cell The figure explaining the write-in operation by BBHH injection | pouring in the p channel MONOS memory cell FIG. 10 is a diagram showing a threshold distribution during programming / unprogramming of the p-channel MONOS memory cell. The figure explaining the read-out operation in the same p-channel MONOS memory cell The figure explaining the erase operation in the same p channel MONOS memory cell The figure explaining the voltage application conditions at the time of writing, reading, and erasing in the same p-channel MONOS memory cell The figure which shows the structure of the VGA type memory cell array using the same p channel MONOS memory cell The figure which shows the equivalent circuit of the same VGA type memory cell array, and the voltage application system at the time of writing The figure which shows the voltage application system at the time of writing of the same VGA type memory cell array, and the formation state of a depletion layer The figure which shows other embodiment of the voltage application system at the time of the writing of the same VGA type memory cell array The figure which shows the voltage application system at the time of reading of the same VGA type memory cell array The figure which shows the structure of the VGA type | mold memory cell array using the said p channel MONOS memory cell. Sectional view showing a vertical structure of the same VGA type memory cell array The figure which shows the structure of the other VGA type | mold memory cell array using the said p channel MONOS memory cell. Sectional view showing the vertical structure of another VGA type memory cell array The figure which shows the equivalent circuit of the same NOR type memory cell array FIG. 3 is a diagram showing the structure of a completely isolated memory cell array using the p-channel MONOS memory cell. The figure which shows the equivalent circuit of the completely separate memory cell array The figure which shows the structure of an n-type linear area | region at the time of making the said complete isolation type memory cell array contactless Structure diagram of p-channel MONOS memory cell array according to another embodiment of the present invention Structure diagram of p-channel MONOS memory cell array according to another embodiment of the present invention The figure which shows the structure of the conventional n channel MONOS memory cell

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... P-type semiconductor substrate, 11 ... Bottom n-type well, 12 ... P-type well, 13, 14 ... N-type diffusion region, 15 ... Tunnel oxide film, 16 ... Charge trap layer, 17 ... Insulating film, 18 ... Gate electrode ,

Claims (3)

A pair of n-type diffusion layer regions formed at predetermined intervals on the p-type well surface and a nonconductor formed above the channel region sandwiched between the pair of n-type diffusion layer regions via a tunnel oxide film A memory cell including a charge trap layer and a gate electrode formed above the charge trap layer via an insulating film,
A method of performing programming by trapping positive charges in the charge trapping layer and erasing by injecting negative charges by substrate hot electron injection,
At the time of the substrate hot electron injection, the potential difference between the gate electrode and the pair of n-type diffusion layer regions is determined so that the n is formed in the pair of n-type diffusion layer regions and the p-type well or adjacent to the p-type well. A method for erasing a nonvolatile semiconductor memory device, characterized in that the potential difference is set to be larger than a potential difference with a type emitter electrode.   2. The method for erasing a nonvolatile semiconductor memory device according to claim 1, wherein a bottom n-type well formed around and at the bottom of the p-type well is used as the emitter electrode.   3. The method for erasing a nonvolatile semiconductor memory device according to claim 2, wherein the potential of the bottom n-type well used as the emitter electrode is a ground potential.

Images