JP2005062725A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of preventing a display defect in a emission-line state with high reliability. <P>SOLUTION: The display device comprises a plurality of gate lines Y, a plurality of signal lines X crossing those gate lines Y, a plurality of display pixels PX which are arranged nearby intersections of the plurality of gate lines Y and the plurality of signal lines X, a gate line driving circuit 15 which selectively drives the plurality of gate lines Y, a plurality of switch parts S1, S2, ..., which output an external video signal to the plurality of signal lines X, a plurality of thin-film transistors 13 which are driven through corresponding gate lines Y to supply video signals on the corresponding signal lines X to corresponding display pixels PX, and a protecting circuit 36 which removes undesirable reverse bias high voltages applied to the plurality of switching element parts S1, S2, ..., through the plurality of signal lines X. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to a display device in which a plurality of display pixels are commonly connected to a single switching element, and in particular, a display device adjacent to a wiring in which these display pixels are set to a higher voltage than the output voltage of the switching element. About.

  In recent years, along with improvements in computer operation systems or applications, liquid crystal display devices are required to be able to display a large amount of information such as videos handled by multimedia and the Internet. Further, depending on the application, portability that allows easy movement to an office, home, or other places is also required. For this reason, liquid crystal display devices are vigorously reduced in thickness, weight, screen size, and resolution.

  A liquid crystal display device generally has a structure in which a liquid crystal layer is sandwiched between an array substrate and a counter substrate. For example, in an active matrix liquid crystal display device, an array substrate is arranged along a plurality of pixel electrodes arranged in a matrix, a plurality of gate lines arranged along the row of these pixel electrodes, and a column of these pixel electrodes. It includes a plurality of signal lines and a plurality of pixel switching elements arranged in the vicinity of the intersection positions of these scanning lines and signal lines. The counter substrate includes a single counter electrode that faces the plurality of pixel electrodes. The liquid crystal layer forms a plurality of display pixels that display an image corresponding to a potential difference between the electrodes in cooperation with the plurality of pixel electrodes and the counter electrode. Each pixel switching element is constituted by a thin film transistor (TFT) using, for example, an amorphous silicon or polysilicon thin film, and takes in a video signal from a signal line and applies it to a pixel electrode under control from each gate line.

  Recently, when the pixel switching element is a polysilicon thin film transistor, a part of or all of the gate line driving circuit and the signal line driving circuit are formed as an array substrate using the polysilicon thin film transistor formed by the same process as the pixel switching element. It is attempted to integrate them (for example, see Patent Document 1). Such a configuration can reduce the total number of components, the number of connection wirings between the array substrate and the external unit, and the like as compared with the case where the gate line driving circuit and the signal line driving circuit are provided as external units connected to the array substrate.

By the way, these drive circuits must be arranged in a small space provided around the image display area on the array substrate. In addition, the performance of polysilicon thin film transistors is superior to that of amorphous silicon thin film transistors, but is far inferior to that of single crystal transistors. Normally, when a thin film transistor is incorporated in a signal line driver circuit, this thin film transistor may have a withstand voltage of 2 V to 5 V, which is equivalent to the thin film transistor of the pixel switching element. It is necessary to perform a switching operation at an extremely high speed so that the setting of the signal line potential is completed within an extremely short time divided by the number. On the other hand, when the thin film transistor is incorporated in the gate line driving circuit, this thin film transistor requires a withstand voltage of 15 to 20 V, which is 4 to 5 times that of the thin film transistor incorporated in the signal line driving circuit. A switching operation may be performed at a rate of about once. Therefore, it is relatively easy to integrate the entire gate line driving circuit with the array substrate, but the signal line driving circuit is not as easy as the gate line driving circuit. For this reason, in the signal line driving circuit, active switching drivers such as thin film transistor groups connected to a plurality of signal lines as switching elements are arranged on the array substrate, for example, a digital-analog conversion circuit (DAC). It is practical to dispose the remaining drive section of the signal line drive circuit in an external unit connected to the array substrate.
JP 2001-134238 A

  By the way, in the liquid crystal display device in which the active switching driver is arranged on the array substrate, a linear display defect occurs without any abnormality in appearance such as disconnection or short circuit of the wiring. When we investigated the failed liquid crystal display device, it was confirmed that display failure occurred at a rate of about 1% of the whole as described above. For example, the bright line-like display defect is generally caused by the disconnection of the signal line, but may be caused by the operation stop of the signal line switching element. When an operation reliability test was performed at high temperatures, the frequency of occurrence was low, but a pixel display defect (point defect) at the initial stage was a signal line switching after 90 hours had passed since the start of the test. It has been found that the device does not operate normally, resulting in a defective bright line display. Such bright line display defects result in a significant loss of screen quality.

  An object of the present invention is to provide a display device that can prevent bright line-like display defects with high reliability.

  According to the present invention, a plurality of gate lines, a plurality of signal lines intersecting with the gate lines, a plurality of display pixels arranged in the vicinity of the intersection positions of the plurality of gate lines and the plurality of signal lines, A gate line driving circuit that selectively drives the gate lines, a plurality of switching element units that output external video signals to the plurality of signal lines, and video signals on the corresponding signal lines that are driven through the corresponding gate lines, respectively. A display device is provided that includes a plurality of thin film transistors that supply a corresponding display pixel and a protection circuit that removes an undesired reverse bias high voltage applied to a plurality of switching element portions via a plurality of signal lines.

  In this display device, the protection circuit removes an undesired reverse bias high voltage applied to the plurality of switching element portions via the plurality of signal lines. For example, the reverse bias high voltage is removed by the protection circuit even if the switching element is reverse-biased through the signal line due to foreign matter adhering to the display pixel due to a high voltage from the gate line or other adjacent wiring or a wiring defect in the pixel. Therefore, the characteristics of the switching element section are not deteriorated by continuous application of the reverse bias high voltage. Therefore, the bright line-like display defect due to the operation stop of the switching element portion can be prevented with high reliability.

  ADVANTAGE OF THE INVENTION According to this invention, the display apparatus which can prevent a bright line-like display defect with high reliability can be provided.

  Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to the drawings. This liquid crystal display device has a light transmissive effective display area set to a size of, for example, 15 inches diagonal, and is configured using a polysilicon thin film transistor.

  1 schematically shows a planar structure of the liquid crystal display device, FIG. 2 partially shows an internal structure of the liquid crystal display device shown in FIG. 1, and FIG. 3 shows a circuit on the array substrate shown in FIGS. The configuration is shown.

  As shown in FIG. 1, the liquid crystal display device includes an array substrate AR, a counter substrate CT arranged to face the array substrate AR at a predetermined interval, and the array substrate AR and the counter substrate CT. And a liquid crystal layer LQ that is sandwiched through an alignment film. The array substrate AR and the counter substrate CT are bonded to each other by a sealing material disposed at the outer peripheral end portions thereof.

  The array substrate AR includes m × n pixel electrodes 11 arranged in a matrix, and m gate lines Y (Y1, Y2, Y3,... Ym) arranged along the rows of the pixel electrodes 11. , N signal lines X (X1, X2, X3,... Xn) arranged along the columns of the pixel electrodes 11 and mx arranged near the intersections of the gate lines Y and the signal lines X. and n pixel switching elements 13. The counter substrate CT is formed on the color filters CF of red (R), green (G), and blue (B) formed for the pixel electrodes 11 in the corresponding columns, and m × n pieces of the color filters CF. A counter electrode 10 facing the pixel electrode 11 is included. In the array substrate AR, each pixel electrode 11 constitutes a display pixel PX in cooperation with the counter electrode 10 on the counter substrate CT side, the color filter CF, and the liquid crystal layer LQ in a region surrounded by the gate line Y and the signal line X. To do.

  Each pixel switching element 13 is composed of a polysilicon thin film transistor using a polysilicon semiconductor thin film. The thin film transistor has a gate electrode connected to the corresponding gate line Y, a source electrode connected to the corresponding signal line X, and a drain electrode connected to the corresponding pixel electrode 11. The pixel electrode 11 constitutes a counter electrode CT and a liquid crystal capacitor via the liquid crystal layer LQ.

  This liquid crystal display device includes a gate line driving circuit 15 for driving m, for example, 768 gate lines Y, a signal line driving circuit 16 for driving n, for example, 1024 × 3 signal lines X, and gate line driving. A printed circuit board PCB for controlling the circuit 15 and the signal line driving circuit 16 is provided. The gate line driving circuit 15 is configured by combining polysilicon thin film transistors integrally formed on the array substrate AR by the same process as the pixel switching element 13. The signal line driving circuit 16 includes a selection circuit 17 configured by combining polysilicon thin film transistors formed on the array substrate AR in the same process as the pixel switching element 13, and a driver IC 18 mounted on the flexible wiring substrate as an external unit. The tape carrier packages TCP1 to TPC6 connected to the array substrate 11 are configured.

  The selection circuit 17 sequentially selects the first and second signal line blocks obtained by dividing the n signal lines X so as to include half of the signal lines X in the effective video period included in each horizontal scanning period. This is an active switching driver that sequentially outputs video signals for one signal line block obtained from the TCP 6 to half the signal lines X corresponding to the selected signal line block.

  The tape carrier packages TCP1 to TCP6 are fixed side by side along one side of the array substrate AR, and further connected to the printed circuit board PCB.

  This printed circuit board PCB receives an external digital video signal, vertical synchronizing signal, and horizontal synchronizing signal, generates various control signals based on the vertical synchronizing signal and horizontal synchronizing signal, and outputs them together with the video signal DATA. A control IC 20 and a power supply circuit 21 that outputs the gradation reference voltage VREF and the like are mounted. Various control signals include a horizontal start signal STH, a horizontal clock signal CKH, a vertical start signal STV, a vertical clock signal CKV, a load signal LOAD, a block selection signal SEL1, a block selection signal SEL2, and the like. The horizontal start signal STH is a pulse generated for each of the first and second signal line blocks in one horizontal scanning period (1H), and the horizontal clock signal CKH is equal to the number of signal lines in each signal line block in each horizontal scanning period. The vertical start signal STV is a pulse generated every one vertical scanning period, the vertical clock signal CHV is a pulse generated by the number of scanning lines in each vertical scanning period, and the load signal LOAD is This signal is set to a low level at the start timing of the first half and the latter half of the effective video period in one horizontal scanning period, and is set to a high level at the timing of the first half and the second half of the effective video period.

  The block selection signal SEL1 is set to a low level and a high level in the first half and the second half of the effective video period in the first horizontal scanning period, respectively, and the effective video period in the second horizontal scanning period following the first horizontal scanning period. Are signals set to a high level and a low level in the first half and second half, respectively. The block selection signal SEL2 is set to a high level and a low level in the first half and the second half of the effective video period in the first horizontal scanning period, respectively, and the effective video period in the second horizontal scanning period following the first horizontal scanning period. Are signals set to a low level and a high level in the first half and second half, respectively. This level relationship is repeated every two horizontal scanning periods.

  As shown in FIG. 3, each of the tape carrier packages TCP1 to TCP6 includes a circuit board side pad PD1 connected to a connection terminal on a connection wiring formed on the printed circuit board PCB, and a connection formed on the array substrate AR. An array substrate-side pad PD2 connected to a connection terminal on the wiring and various wirings for connecting these pads are provided. The circuit board side pad PD1 and the array board side pad PD2 are electrically connected to the printed circuit board PCB and the array board AR, respectively, via an anisotropic conductive film (ACF).

  Control signals such as the vertical start signal STV and the vertical clock signal CKV are supplied from the printed circuit board PCB to the gate line driving circuit 15, and the horizontal start signal STH, the horizontal clock signal CKH, the block selection signal SEL1, the block selection signal SEL2, and the load The control signal such as the signal LOAD, the digital video signal DATA, and the gradation reference voltage are supplied from the VREF printed circuit board PCB to the signal line driving circuit 16. The gate line driving circuit 15 selects a gate driving voltage for sequentially selecting m gate lines Y during the effective video period of the horizontal scanning period by shifting the vertical start signal STV in synchronization with the vertical clock signal CKV. Supply to the gate line Y. The signal line driving circuit 16 sequentially selects the signal lines X of the respective signal line blocks by shifting the horizontal start signal STH in synchronization with the horizontal clock signal CKH, and generates the video signal DATA supplied to these signal lines X. Based on this, the signal line X of the corresponding signal line block is driven.

Each driver IC 18 of the signal line driving circuit 16 includes a shift register 30, a data register 31, a D / A converter 32, and an output buffer circuit 33 as shown in FIG. The shift register 30 shifts the horizontal start signal STH in synchronization with the horizontal clock signal CKH. The data register 31 sequentially captures and holds the digital video signal DATA under the control of the shift register 521 after the load signal LOAD falls. The D / A converter 32 generates a predetermined number of gradation voltages by dividing the gradation reference voltage VREF, and selectively outputs these gradation voltages corresponding to the video signal DATA held in the data register 31. Thus, D / A conversion is performed. The output buffer circuit 33 is set to a high impedance state as the load signal LOAD rises, and the analog video signal from the D / A converter 32 is horizontally applied to the selection circuit 17 on the array substrate AR as the load signal LOAD falls. The signal is output during the effective video period of the scanning period, and during the blanking period, it is electrically disconnected from the selection circuit 17 again by the output buffer switch and set to high impedance.
The selection circuit 17 converts the video signals from the output terminals OUT1, OUT2,... Of the six drive ICs 18 arranged on the tape carrier package TCP1 to TCP6 side into two adjacent signal lines X1, X2, X3, X4, X5, X6,. Are provided with n / 2 switch units S1, S2, S3,... Distributed in the first half of the effective video period in the horizontal scanning period. Each of the switch sections S1, S2, S3,... Corresponds to the corresponding one of the output terminals OUT1, OUT2,... Under the control of the block selection signals SEL1, SEL2. Are connected to one of the switching elements ASW1 and corresponding adjacent signal lines X1 and X2, X3 and X4, X5 and X6.

  These switching elements ASW1 and ASW2 are composed of, for example, P-channel polysilicon thin film transistors. Here, n / 2 signal lines X1, X3, X5, X7,... Are assigned as first signal line blocks to the first switching element ASW1 of the switch units S1, S2, S3,. Lines X2, X4, X6, X8... Are assigned to the second switching element ASW2 of the switch units S1, S2, S3,.

  For example, when the block selection signal SEL1 is set to a low level and the first switching elements ASW1 of the switch units S1, S2, S3,... Are turned on, the video signals output from the output terminals OUT1, OUT2,. Are supplied to the signal lines X1, X3, X5, X7... Of the first signal line block in the first half of the effective video period. Further, when the block selection signal SEL2 is set to a low level in place of the block selection signal SEL1, and the first switching elements ASW2 of the switch sections S1, S2, S3,... Are turned on, they are output from the output terminals OUT1, OUT2,. Video signals are supplied to the signal lines X2, X4, X6, X8... Of the second signal line block in the first half of the effective video period in the horizontal scanning period.

  The array substrate AR further includes a first protection circuit 35 connected to the input terminals of all the switch units S1, S2, S3,... That receive video signals from all the output terminals OUT1, OUT2, OUT3,. A second protection circuit 36 connected to the signal lines X1, X2, X3, X4,.

  The first protection circuit 35 has n / 2 protection diode portions 35D for removing the reverse bias high voltage applied to the switching elements ASW1 and ASW2 of the switch portions S1, S2, S3,. . Each protection diode unit 35D includes two polysilicon thin film transistors reverse-biased between the reference potential terminal VSS and the input terminal, and a power supply potential terminal VDD and an input terminal that are set to a potential higher than the reference potential terminal VSS. It consists of two polysilicon thin film transistors connected in reverse bias between each other. Here, in the protection diode portion 35D for the odd-numbered switch portions S1, S3,..., All four polysilicon thin film transistors are N-channel type. Further, in the protection diode portion 35D for the even-numbered switch portions S2, S4,..., All four polysilicon thin film transistors are configured as a P-channel type.

  The second protection circuit 36 has n protection diode portions 36D for removing the reverse bias high voltage applied to the switching elements ASW1 and ASW2 of the switch portions S1, S2, S3,. Each protection diode portion 36D includes one polysilicon thin film transistor reverse-biased between the reference potential terminal VSS and the signal line X, and a power supply potential terminal VDD and a signal line set to a potential higher than the reference potential terminal VSS. It consists of one polysilicon thin film transistor connected in reverse bias with X. Here, in each of the pair of protective diode portions 36D for the odd-numbered switch portions S1, S3,..., Two polysilicon thin film transistors are configured as an N-channel type. Further, in each of the pair of protective diode portions 35D for the even-numbered switch portions S2, S4,..., Two polysilicon thin film transistors are configured as a P-channel type.

  In the liquid crystal display device according to the present embodiment, the first and second signal line blocks obtained by dividing the signal line driving circuit 16 so that each of the n signal lines X includes n / 2 lines are effective for the video signal DATA. A selection circuit 17 that sequentially selects in the first half and the second half of the video period, and six signal line drive ICs 18 as drive units that drive n / 2 signal lines X included in the signal line block selected by the selection circuit 17. Including. Therefore, the number of connection wirings can be reduced in increasing the definition of the display screen, and a sufficient pitch can be secured between these connection wirings. Further, the reduction in the number of connection wirings can alleviate the deterioration of the video signal depending on the wiring length routed on the array substrate AR as the display screen becomes larger.

  In addition, the protection circuit 35 protects the selection circuit 17 when an undesirably high voltage due to static electricity or the like is applied to the input terminal of the selection circuit 17 from the outside of the array substrate AR. Specifically, the current due to the high voltage flows through the protection diode portion 35D. Thereby, destruction of the switching elements ASW1 and ASW2 of the selection circuit 17 can be prevented.

  Further, for example, the signal line X and the gate line Y are short-circuited due to foreign matters or wiring defects attached to the display pixel PX, and a high voltage from the gate line Y is applied to the selection circuit 17 via the signal line X to be selected. The protection circuit 36 protects the selection circuit 17 when the switching elements ASW1 and ASW2 are reverse-biased. Specifically, a current due to the high voltage flows to the reference potential terminal VSS side via the protection diode portion 36D. As a result, the switching elements ASW1 and ASW2 of the selection circuit 17 are not maintained in a reverse biased state, and an operation failure due to characteristic deterioration of the switching element ASW1 or ASW2 can be prevented. Therefore, the screen quality is not significantly impaired by the bright line-like display defect in which all the display pixels PX for one column connected to the malfunctioning switching element ASW1 or ASW2 via the signal line X are not lit. If such bright line-like display defects occur in the initial stage before shipment, it becomes a fatal problem that reduces the yield of products. Moreover, even if it occurs at the use stage after shipment, it becomes a fatal problem that lowers the reliability of the product.

  Incidentally, depending on the product, the storage capacitor line may be formed along the display pixel PX of each row in order to reduce the potential fluctuation of the pixel electrode 11. In this case, the storage capacitor line and the signal line are short-circuited due to foreign matters or wiring defects attached to the display pixel PX, and as a result, a high voltage from the storage capacitor line is applied to the selection circuit 17 via the signal line X and selected. There is a possibility that the switching elements ASW1 and ASW2 of the circuit 17 are reverse-biased. However, if the above-described protection circuit 36 is provided, this high voltage current flows to the reference potential terminal VDD side via the protection diode portion 36D. Therefore, as in the case where the gate line Y and the signal line X are short-circuited, the switching elements ASW1 and ASW2 of the selection circuit 17 are not maintained in the reverse biased state, and the operation due to the characteristic deterioration of the switching element ASW1 or ASW2 Defects can be prevented.

  Further, the above-described protection circuits 35 and 36 are configured using a thin film transistor formed by a process similar to that of the pixel switching element 13 and do not require an increase in the manufacturing process, thereby preventing an increase in manufacturing cost. It is.

  In addition, this invention is not limited to the above-mentioned embodiment, It can deform | transform variously in the range which does not deviate from the summary.

  In the above-described embodiment, the n signal lines are divided into the first and second signal line blocks. However, in order to reduce the number of connection lines between the array substrate AR and the outside, the number of signal line blocks is further increased. Also good.

It is a figure which shows roughly the planar structure of the liquid crystal display device which concerns on one Embodiment of this invention. It is a figure which shows partially the internal structure of the liquid crystal display device shown in FIG. It is a figure which shows the circuit structure on the array board | substrate shown in FIG. 1 and FIG.

Explanation of symbols

  AR ... array substrate, CT ... counter substrate, LQ ... liquid crystal layer, PX ... display pixel, 11 ... pixel electrode, 13 ... pixel switching element, 15 ... gate line drive circuit, 16 ... signal line drive circuit, 17 ... selection circuit, 18 ... Driver IC, 35 ... First protection circuit, 35D ... Protection diode part, 36 ... Second protection circuit, 36D ... Protection diode part.

Claims (4)

  A plurality of gate lines; a plurality of signal lines intersecting with the plurality of gate lines; a plurality of display pixels disposed near intersections of the plurality of gate lines and the plurality of signal lines; and the plurality of gates. A gate line driving circuit for selectively driving the lines, a plurality of switching element units for outputting external video signals to the plurality of signal lines, and video signals on the corresponding signal lines driven through the corresponding gate lines, respectively. Including a plurality of thin film transistors for supplying a corresponding display pixel, and a protection circuit for removing an undesired reverse bias high voltage applied to the plurality of switching element portions via the plurality of signal lines. Display device.   The display device according to claim 1, further comprising a protection circuit that removes an undesired reverse bias high voltage applied to the plurality of switching elements through an input terminal of a video signal.   The display device according to claim 1, wherein each switching element unit includes a plurality of thin film transistors that are respectively connected to at least two adjacent signal lines and selectively conductive.   The protection circuit includes at least one thin film transistor reverse-biased between a reference potential terminal and the signal line, and a power supply potential terminal set to a potential higher than the reference potential terminal and the signal line. The display device according to claim 1, further comprising: a protection diode unit including at least one thin film transistor connected in reverse bias.

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