JP2005012107A - Intermediate substrate with built-in capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an intermediate substrate with a built-in capacitor that has rigidity capable of sufficiently withstanding thermal stresses and can easily secure the electrostatic capacitance required for a decoupling capacitor. <P>SOLUTION: The intermediate substrate 1 with the built-in capacitor has a laminated ceramic capacitor substrate 60 in which class 1 baked electrode conductor layers 57 and class 2 baked electrode conductor layers 54 are alternately laminated upon baked ceramic dielectric layers 52. On the first principal surface of the ceramic capacitor substrate 60, class 1 electrode conductor layers 14, class 2 electrode conductor layers 17, and high polymer laminated capacitor sections 10 alternately laminated upon high polymer dielectric layers 13 are formed. In addition, a first terminal array 5 composed of class 1 terminals 5a and class 2 terminals 5b respectively connected electrically to the class 1 and 2 electrode conductor layers 14 and 17 are formed. On the second principal surface of the substrate 60, a second terminal array 7 composed of class 1 substrate-side terminals 7a and class 2 substrate-side terminals 7b is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an intermediate substrate with a built-in capacitor.
[0002]
[Prior art]
[Patent Document 1]
JP 2003-142624 A
[0003]
In an integrated circuit device such as a CPU or other LSI that operates at high speed, power lines are allocated to a plurality of circuit blocks in the integrated circuit so as to branch from a common power source. When the elements are simultaneously switched at a high speed, a large current is drawn from the power supply at once, and there is a problem that fluctuations in the power supply voltage become a kind of noise and propagate to each circuit block through the power supply line. Therefore, providing a decoupling capacitor for reducing the power supply impedance for each circuit block is effective in suppressing noise propagation between blocks due to power supply voltage fluctuations. Further, a bypass capacitor (commonly referred to as “pass capacitor”) that removes external noise such as surge noise in an AC filtering manner may be provided in the same connection form.
[0004]
By the way, in the case of a large-scale integrated circuit such as a CPU, the number of circuit blocks to be built is large, the number of power supply terminals and ground terminals tends to increase, and the distance between terminals is also decreasing. Decoupling capacitors need to be connected to each power supply line going to each circuit block, and it is not only difficult to mount capacitors individually in an integrated circuit where many terminals are densely packed, but also miniaturization, etc. Go backwards in the flow.
[0005]
Therefore, Patent Document 1 discloses an intermediate substrate type decoupling capacitor using a thin film capacitor. As a result, decoupling capacitors used in a large number of circuit blocks can be collected in the intermediate substrate. In addition, in the high frequency region (especially 100 MHz or more) where the noise problem due to power supply voltage fluctuation at the time of high-speed switching is particularly likely to appear, the specific gravity of the inductive reactance term in the power supply impedance becomes large. Therefore, by directly connecting a capacitor functioning as a decoupling capacitor (or bypass capacitor) to a semiconductor element in the form of an intermediate substrate, the decoupling capacitor can be brought closer to the semiconductor element, and the wiring length between the power supply terminal and the decoupling capacitor Can be shortened. As a result, the inductance of the capacitor terminal can be reduced, which contributes to lowering the impedance of the decoupling capacitor.
[0006]
[Problems to be solved by the invention]
However, the above-described Patent Document 1 has a configuration in which a thin film capacitor is independently formed as an intermediate substrate. In this configuration, since the rigidity of the thin film capacitor is not so high, the main board that is the connection destination is mainly made of a polymer material such as a mother board or an organic package board that forms the second intermediate board. If a thermal history such as solder reflow is applied, the thermal stress may lead to defects such as solder peeling and damage to the thin film capacitor itself due to insufficient rigidity.
[0007]
An object of the present invention is to provide a rigidity sufficient to withstand thermal stress due to a difference in coefficient of linear expansion between a semiconductor element and a main substrate even when a thermal history such as solder reflow is applied, and a decoupling capacitor The object is to provide an intermediate substrate with a built-in capacitor that can easily secure the capacitance necessary for realizing the function.
[0008]
[Means for solving the problems and actions / effects]
In order to solve the above problem, the intermediate substrate with a built-in capacitor of the present invention is
A multilayer ceramic capacitor substrate in which first-type fired electrode conductor layers and second-type fired electrode conductor layers separated from each other in direct current are alternately laminated with fired ceramic dielectric layers fired simultaneously with the fired electrode conductors; ,
A first type electrode conductor layer provided on the first main surface of the multilayer ceramic capacitor substrate and conducting to the first type sintered electrode conductor layer; and a second type electrode conductor layer conducting to the second type sintered electrode conductor layer. A polymer multilayer capacitor portion alternately laminated with polymer dielectric layers in a form separated from each other in a direct current manner,
On the first main surface of the polymer multilayer capacitor, a first terminal array comprising a first type terminal and a second type terminal respectively conducting to the first type electrode conductor layer and the second type electrode conductor layer is formed,
A second terminal comprising a first-type substrate-side terminal and a second-type substrate-side terminal that are electrically connected to the first-type sintered electrode conductor layer and the second-type sintered electrode conductor layer on the second main surface of the multilayer ceramic capacitor substrate. An array is formed.
[0009]
In the above-described intermediate substrate with built-in capacitor, the polymer multilayer capacitor is integrated on the multilayer ceramic capacitor substrate. The first terminal array formed on the first main surface of the polymer multilayer capacitor can be solder-connected to the power supply terminal and the ground terminal on the semiconductor element side made of a silicon integrated circuit chip or the like. A power terminal and a ground terminal can be connected to the second terminal array formed on the second main surface of the multilayer ceramic capacitor substrate. Therefore, the capacitor having the structure can be functioned as an intermediate substrate that is located between the semiconductor element and the main substrate and mediates the connection between the two. A polymer multilayer capacitor uses a polymer material with a relatively low dielectric constant as a dielectric, so that a large capacitance cannot be expected and rigidity is low, but a multilayer ceramic capacitor using a ceramic with a high dielectric constant is used as the base. As a composite, it is possible to simultaneously improve the capacitance and the rigidity of the intermediate substrate. As a result, even when a thermal history such as solder reflow is added, it has sufficient rigidity to withstand thermal stress due to the difference in coefficient of linear expansion between the semiconductor element and the main board, and it is static for decoupling capacitors. An intermediate substrate with a built-in capacitor that can easily secure the capacitance is realized.
[0010]
Naturally, a capacitor that functions as a decoupling capacitor (or a bypass capacitor) is directly connected to the semiconductor element in the form of an intermediate board incorporating the capacitor, so that the decoupling capacitor can be brought closer to the semiconductor element, and the power supply terminal and the decoupling capacitor The wiring length can be shortened. As a result, the inductance of the capacitor terminal can be reduced, which contributes to lowering the impedance of the decoupling capacitor. Further, since the decoupling capacitor is incorporated in the intermediate board, it is not necessary to arrange the decoupling capacitor as a separate element on the back side of the main board, and the number of parts can be reduced or the apparatus can be downsized. From the viewpoint of improving rigidity, it is more advantageous that the multilayer ceramic capacitor substrate is formed thicker than the polymer multilayer capacitor having low rigidity.
[0011]
Since the dielectric constant of the ceramic dielectric is generally higher than the dielectric constant of the polymer material, it is very easy to set the capacitance of the multilayer ceramic capacitor substrate to be larger than the capacitance of the polymer multilayer capacitor. As a result, the multilayer ceramic capacitor substrate naturally has the effect of supplementing the electrostatic capacitance of the polymer multilayer capacitor, and also has a parallel combination of a relatively large capacitor and a smaller capacitor. In some cases, the impedance reduction effect can be secured in a wider frequency band.
[0012]
When the dielectric layer used for the multilayer ceramic capacitor substrate is made of a high dielectric constant ceramic (defined as a ceramic having a relative dielectric constant of 50 or more: for example, a ferroelectric ceramic), its capacitance can be greatly increased. As a result, the shortage of the capacitance of the polymer multilayer capacitor can be compensated more effectively. Further, from the viewpoint of obtaining a capacitor having the same capacity, the electrode area can be reduced, which is advantageous from the viewpoint of reducing the size of the intermediate substrate. Further, as the high dielectric constant ceramic, a composite oxide having a perovskite type crystal structure, for example, one composed of one or more of barium titanate, strontium titanate and lead titanate is particularly high dielectric constant. And can be suitably used in the present invention.
[0013]
On the other hand, depending on the frequency band for impedance reduction, there is a case where the capacitance on the multilayer ceramic capacitor substrate side does not need to be increased so much. In this case, the ceramic used has a low coefficient of linear expansion, while the rigidity ( A material with a high Young's modulus) is preferable. This reduces the difference in expansion coefficient between the semiconductor element (for example, silicon) and the intermediate substrate, and between the intermediate substrate and the main substrate mainly composed of a polymer material, and thus is formed on both surfaces of the intermediate substrate during solder reflow. It is possible to reduce the level of thermal shear stress applied to each of the terminals, and to prevent the solder from peeling off at the terminals.
[0014]
The linear expansion coefficient of silicon from room temperature to around 300 ° C used for solder reflow is as low as 2-3 ppm / ° C. Conversely, polymer materials such as epoxy resins that constitute the main substrate (motherboard or organic package substrate) are It is as high as 17 to 20 ppm / ° C. Since the dielectric layer of the polymer multilayer capacitor is also composed of a polymer material having a high linear expansion coefficient such as a photosensitive epoxy resin, the plate-like substrate is composed of a ceramic material having a low linear expansion coefficient as much as possible. This is effective by reducing the difference between the linear expansion coefficients and reducing the shear stress acting on the terminal. As such a ceramic material, alumina (7 to 8 ppm / ° C.), glass ceramic obtained by adding 40 to 60 parts by weight of an inorganic ceramic filler such as alumina to borosilicate glass or lead borosilicate glass can be used. As other ceramic materials, aluminum nitride, silicon nitride, mullite, silicon dioxide, magnesium oxide, and the like can also be used.
[0015]
Next, in Patent Document 1, as shown in FIG. 2, in addition to the capacitor electrode, a lead wiring portion (reference numeral 32: third conductor layer) for terminal interval conversion is positioned at the uppermost layer position. Not only does the manufacturing process become longer due to the increased number of layers, but also the long lead-out wiring part is formed at the position directly connected to the terminal part of the semiconductor element. It is difficult to achieve impedance and wide bandwidth.
[0016]
In order to solve this problem, on the first main surface of the polymer multilayer capacitor part, the first type terminal and the second type terminal forming the first terminal array are closest to the first main surface. It is effective to employ a structure in which the conductor layer and the second-type electrode conductor layer are coupled in the stacking direction directly or via an auxiliary via conductor. According to this structure, the conductor portion directly connected to the terminal is the electrode conductor layer that forms the capacitor or the auxiliary via conductor in the stacking direction that conducts to the electrode conductor layer. As a result, it is possible to effectively eliminate the lead-out wiring portion as in Patent Document 1 that causes an increase in inductance, and thus it is possible to reduce the impedance of the capacitor and increase the bandwidth. Further, since it is not necessary to provide a lead wiring portion separately from the electrode conductor layer, the structure is simplified and the manufacturing process can be simplified.
[0017]
Next, in the intermediate substrate with a built-in capacitor according to the present invention, the terminal arrangement interval of the second terminal array can be set wider than the terminal arrangement interval of the first terminal array. In recent years, the interval between terminals of an integrated circuit element to be connected to a capacitor tends to become narrower due to the miniaturization and higher density of the integrated circuit element. On the other hand, the terminal interval on the main board side may not be narrowed from the viewpoint of manufacturing cost. In this case, the terminal interval of the integrated circuit element and the terminal interval on the main board side may not match. However, as described above, in the capacitor built-in intermediate substrate, the terminals of the second terminal array formed on the second main surface of the plate-like substrate rather than the first terminal array formed on the first main surface of the polymer multilayer capacitor. If the arrangement interval is set wide, even if the above-described terminal interval mismatch occurs on the front and back sides of the capacitor forming the intermediate substrate, both can be connected without any problem.
[0018]
In the polymer multilayer capacitor having the above configuration, at least one of the electrode conductor layers has via conductor portions (via conductor portions of the polymer multilayer capacitor) arranged from the first terminal array side to the electrode conductor layer at the first arrangement interval. Are connected to the electrode conductor layer from the second terminal array side at a second arrangement interval wider than the first arrangement interval, either via conductor portion of polymer multilayer capacitor or substrate side coupling conductor portion. ) Is connected to the interval conversion layer. In this specification, the first arrangement interval and the second arrangement interval are both defined as meaning the average interval of the via conductor portions. By changing the positions of the corresponding via conductor portions connected to the upper and lower sides of the interval conversion layer, the terminal interval can be converted very easily.
[0019]
In this case, in the polymer multilayer capacitor, at least one layer of the first-type electrode conductor layer and at least one layer of the second-type electrode conductor layer can be used as an interval conversion layer, respectively. Thereby, it is possible to easily convert the terminal interval independently while maintaining the DC separation state of the first type terminal and the second type terminal. In other words, the first type electrode conductor layer is used for expanding the interval of the via conductor portion conducting to the first type terminal, and the second type electrode conductor layer is used for expanding the interval of the via conductor portion conducting to the second type terminal. Thus, the intervals between the various types of terminals can be expanded and converted at different positions in the stacking direction.
[0020]
If spacing between different types of terminals is to be performed at the same position in the stacking direction, a through hole is formed in the electrode conductor layer of the first polarity (one of the first type and the second type), and the first hole is inserted into the through hole. Bipolar (the other of the first type and the second type) conductor layers must be arranged in a relatively large area in order to expand the terminal spacing, separated by a dielectric. Since the second polarity conductor layer has the same polarity as the conductor layer adjacent to the polymer dielectric layer, it hardly contributes to the formation of capacitance. On the other hand, the first polarity electrode conductor layer has a different polarity from the adjacent conductor layer across the polymer dielectric layer. In this case, the through hole must be formed large, so that the effective area of the electrode is reduced and the capacitance is reduced.
[0021]
However, if the distance between the various terminals is extended and converted at different positions in the stacking direction, the first polarity conductor layer must be mixed with the second polarity conductor layer at the same position in the stacking direction. Therefore, the capacitance can be prevented from decreasing. More specifically, the first-type electrode conductor layer and the second-type electrode conductor layer define the same type of electrode conductor layer closest to the first terminal array side with respect to the interval conversion layer as the pre-conversion layer. When the same type of electrode conductor layer closest to the second terminal array side is defined as a post-conversion layer, each via between the pre-conversion layer and the interval conversion layer and between the interval conversion layer and the post-conversion layer Two positions where the coupling positions of the conductor portions coincide with each other in the in-plane direction, and are located between the pre-conversion layer and the interval conversion layer and between the interval conversion layer and the post-conversion layer, respectively. The second through hole for passing the via conductor portion may be formed in another electrode conductor layer with a positional relationship shifted from each other. Accordingly, the through hole formed in the first-type electrode conductor layer and the second-type electrode conductor layer suffices with the minimum necessary area for passing the via conductor portion, although the terminal interval conversion is performed. The influence of the decrease in capacitance can be eliminated as much as possible.
[0022]
When performing an extended conversion of the terminal spacing as described above, a first-type electrode conductor arranged on the second main surface side of the polymer multilayer capacitor using the area difference between the first terminal array and the second terminal array A part of the set of the layer and the second type electrode conductor layer may have a larger area than the set of the first type electrode conductor layer and the second type electrode conductor layer arranged on the first main surface side. it can. As a result, the capacitance of the capacitor can be further increased.
[0023]
Also, a structure similar to the above can be adopted in the multilayer ceramic capacitor substrate, and the same effect can be achieved. That is, in the multilayer ceramic capacitor substrate, at least one layer of the fired electrode conductor layer is connected from the first terminal array side to the fired electrode conductor layer with via conductor portions at the first arrangement interval, while the second terminal array side is concerned. It can be set as the space | interval conversion layer which a via conductor part connects to a baking electrode conductor layer by the 2nd arrangement space wider than a 1st arrangement space. In this case, at least one layer of the first-type fired electrode conductor layer and at least one layer of the second-type fired electrode conductor layer can be used as the interval conversion layer, respectively.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example in which a capacitor built-in intermediate substrate (hereinafter also simply referred to as an intermediate substrate) 1 constituting an embodiment of the present invention is configured as an intermediate substrate disposed between a semiconductor integrated circuit element 2 and a main substrate 3. It is. In the present embodiment, the first main surface of the plate-like member is a surface appearing on the upper side in the drawing, and the second main surface is a surface appearing on the lower side.
[0025]
The semiconductor integrated circuit element 2 has an element side terminal array 4 including a plurality of signal terminals, a power supply terminal, and a ground terminal on the second main surface, and a first terminal array 5 formed on the first main surface of the intermediate substrate 1. On the other hand, it is flip-chip connected via the solder connection portion 6. On the other hand, the main substrate 3 is a mother board or an organic laminated package substrate forming a second-stage intermediate substrate, each of which is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers. The main board side terminal array 8 made of metal pins is connected to the second terminal array 7 formed on the second main surface of the intermediate board 1 via the solder connection portion 6. As shown in FIG. 2, the capacitor-embedded intermediate substrate 1 serving as the intermediate substrate functions as a decoupling capacitor connected in parallel to the power supply line of the semiconductor integrated circuit element 2. In the equivalent circuit of FIG. 2, it is drawn that an independent decoupling capacitor is provided for each power supply line, but these decoupling capacitors are all connected in parallel between the power supply line of the same voltage and the ground. Therefore, in the following embodiments, the decoupling capacitor will be described by being representatively represented by a configuration in which the power supply line is shared as a single capacitor (however, the present invention is not limited to this).
[0026]
As shown in FIG. 3, the capacitor-embedded intermediate substrate 1 has a structure in which a multilayer ceramic capacitor substrate 60 and a polymer multilayer capacitor portion 10 are bonded to the first main surface of the multilayer ceramic capacitor substrate 60. On the first main surface of the polymer multilayer capacitor portion 10, a first-type terminal 5a and a second-type terminal 5b, one of which is used as a power supply terminal and the other as a ground terminal, may have a staggered lattice shape (or a staggered shape). ) To form a first terminal array 5. Also, on the second main surface of the multilayer ceramic capacitor substrate 60, there are a first type substrate side terminal 7a and a second type substrate side terminal 7b, one of which is used as a power supply terminal and the other as a ground terminal. The second terminal array 7 is formed in an alternating grid pattern (or a zigzag pattern) corresponding to the five terminal arrays. Each of the arrays 5 and 7 has a plurality of signal terminals 5s and a signal base-side terminal 7s in a form surrounding a grid-like arrangement of power supply terminals and ground terminals.
[0027]
FIG. 4 shows a detailed structure of the intermediate substrate 1.
The polymer multilayer capacitor unit 10 is formed by alternately laminating a plurality of polymer dielectric layers 13 and a plurality of electrode conductor layers 14 and 17. The electrode conductor layers 14 and 17 are composed of a first dielectric electrode conductor layer 14 conducting to the first kind terminal 5 a and a second dielectric electrode conductor layer 17 conducting to the second kind terminal 5 b by the polymer dielectric layer 13. They are arranged alternately in the stacking direction in a separated form. And, as partially enlarged, one of the same kind of electrode conductor layers (here, the second kind of electrode conductor layer) 17 (A) adjacent to the stacking direction and the other of the same kind of electrode conductor layer 17 (B) Between the first polymer dielectric layer 13 (A), the other type electrode conductor layer (here, the first type electrode conductor layer) 14, and the second polymer dielectric layer 13 (B). Arranged in this order. The first through hole 13h (A) formed in the first polymer dielectric layer 13 (A) and the second through hole 16 formed in the other-type electrode conductor layer 14 overlap with each other by in-plane projection. And the second through hole 16 and the third through hole 13h (B) formed in the second polymer dielectric layer 13 (B) are overlapped by in-plane projection (illustrated) In part, these through-holes are arranged coaxially with a circular cross-section).
[0028]
The first through-hole 13h (A) and the third through-hole 13h (B) are filled, respectively, so that one homogeneous electrode conductor layer 17 (A) and the other identical electrode conductor layer 17 (B) A via conductor portion 19 is formed to couple the two. Here, a so-called stacked via configuration in which vias individually formed in the two polymer dielectric layers 13 and 13 are coupled to each other is adopted. Then, in the second through-hole 16, the dielectric hole filling portion integrated (coupled) with the first polymer dielectric layer 13 (A) and the second polymer dielectric layer 13 (B), respectively. 13v separates the outer peripheral surface of the via conductor portion 19 and the inner peripheral surface of the second through hole 16 in a direct current manner. In the above structure, a structure portion in which the first electrode conductor layer 14 and the second electrode conductor layer 17 are inverted is also formed in the same manner.
In FIG. 4, the electrode conductor layers 14 and 17 appear to be divided in the in-plane direction along with the illustration of the through holes 16 and 18, but actually, the portions other than the through holes 16 and 18 as shown in FIG. 5. Then, a continuous layer is formed in the in-plane direction. The same applies to the polymer dielectric layer 13.
[0029]
The polymer multilayer capacitor portion 10 having the above structure is formed by a well-known build-up method, and the polymer dielectric layer 13 has a thickness as a build-up layer made of a resin composition such as an epoxy resin. For example, it is formed to 20 μm or more and 50 μm or less. In this embodiment, the polymer dielectric layer 13 is composed of an epoxy resin, and SiO. ₂ A dielectric filler composed of 10% by mass to 30% by mass is adjusted, and the relative dielectric constant ε is adjusted to 2 to 4 (for example, about 3). On the other hand, a high dielectric constant ceramic (specifically, a complex oxide having a perovskite crystal structure, for example, one or more of barium titanate, strontium titanate, and lead titanate for further improvement of the dielectric constant) It is also possible to use a filler made of
[0030]
The electrode conductor layers 14 and 17 are formed in a thickness of, for example, 10 μm or more and 20 μm or less as a pattern plating layer (for example, an electrolytic Cu plating layer) on the buildup layer. The via conductor portions 15 and 19 are formed on the polymer dielectric layer 13 by a photo via process (the polymer dielectric layer 13 is made of a photosensitive resin composition, for example, an ultraviolet curable epoxy resin), or a laser drilling via process. A via hole is formed by a known method such as (the polymer dielectric layer 13 is made of a non-photosensitive resin composition), and the inside thereof is filled or covered with a via conductor such as plating. In addition, the 1st main surface of the polymer multilayer capacitor | condenser part 10 is covered with the soldering resist layer 11 which consists of a photosensitive resin composition in the form which exposes the 1st type terminal 5a and the 2nd type terminal 5b. .
[0031]
Next, the same kind of electrode conductor layer 14 (17) coupled by the via conductor portion 15 (19) is disposed on the same main surface side for each electrode conductor layer 14 (17) in order to prevent an increase in DC resistance. A plurality of via conductor portions 15 (19) that are electrically connected to the electrode conductor layer 14 (17) are formed. Specifically, the via conductor portions 15 ( 19) is formed in a dispersed manner.
[0032]
In addition, the first type terminal 5a and the second type terminal 5b in the first terminal array 5 are respectively in the first type electrode conductor layer 14 and the second type electrode conductor layer 17 closest to the first main surface. Directly (in this embodiment, the first-type electrode conductor layer 14 side) or an auxiliary via conductor portion 19 ′ (in this embodiment, the second-type electrode conductor layer 17 side) is coupled in the layer thickness direction. Yes.
[0033]
Next, the basic structure of the multilayer ceramic capacitor substrate 60 is substantially the same as that of the polymer multilayer capacitor unit 10, and the first-type sintered electrode conductor layer 57 and the second-type sintered electrode conductor layer 54 ( In any case, the thickness is, for example, 0.5 μm or more and 5 μm or less) and the fired ceramic dielectric layers 52 (thickness: for example, 1 μm or more and 10 μm or less) that are co-fired with the fired electrode conductor layers 57 and 54 are alternately laminated. Has a structured. Such a multilayer ceramic capacitor substrate 60 can be manufactured using a known ceramic green sheet containing a raw material powder of a constituent ceramic, and the patterns of the fired electrode conductor layers 57 and 54 can be formed by printing and applying a metal paste. it can. The via conductor portions 59 and 55 are formed by filling a metal powder paste into a via hole formed by punching or laser drilling in a ceramic green sheet and firing it. The electrode conductor layers 57 or 54 having the same polarity are connected in the stacking direction by via conductor portions 59 and 55, and the electrode conductor layers 57 and 54 and the via conductor portions 59 and 55 having different polarities are printed with a metal paste. At the time of patterning, the through holes 58 and 56 formed in the electrode conductor layers 57 and 54 are separated in a direct current manner.
[0034]
The first-type substrate-side terminal 7 a and the second-type substrate-side terminal 7 b in the second terminal array 7 are the first-type fired electrode conductor layer 57 and the second type that are closest to the second main surface of the multilayer ceramic capacitor substrate 60. It has a structure in which it is coupled to the fired electrode conductor layer 54 in the layer thickness direction via via conductor portions 55 and 59. The via conductors 59 and 55 on the multilayer ceramic capacitor substrate 60 side are on the polymer multilayer capacitor unit 10 side on the second main surface of the polymer multilayer capacitor unit 10 (first main surface of the multilayer ceramic capacitor substrate 60). The electrode conductor layers 14 and 17 having the corresponding polarities are connected directly or via via conductor portions 15 ″.
[0035]
The sintered dielectric layer 52 used for the multilayer ceramic capacitor substrate 60 is made of a high dielectric constant ceramic, for example, one or more of barium titanate, strontium titanate, and lead titanate, in order to prioritize the improvement of capacitance. The perovskite type oxide layer is preferable. On the other hand, if priority is given to the effect of lowering the linear expansion coefficient of the entire intermediate substrate 1 and increasing the rigidity, the fired dielectric layer 52 can be made of a paraelectric ceramic such as alumina or glass ceramic. is there.
[0036]
Next, in the capacitor (intermediate substrate) 1 of the present embodiment, the terminal arrangement interval of the second terminal array 7 is set wider than the terminal arrangement interval of the first terminal array 5. On the first main surface of the multilayer ceramic capacitor substrate 60, a first-type substrate-side coupling conductor portion 51a that conducts to the first-type substrate-side terminal 7a and a second-type substrate-side coupling that conducts to the second-type substrate-side terminal 7b. Each end with the conductor 51b is arranged at a larger interval (in average value) than the terminal interval of the first terminal array 5. In this case, in order to adjust the narrow terminal interval on the first terminal array 5 side to the terminal arrangement of the wide second terminal array 7, it is necessary to convert the terminal interval inside the intermediate substrate 1 with built-in capacitor.
[0037]
Next, at least one of the electrode conductor layers 14 and 17 is a spacing conversion layer LT. In the distance conversion layer LT, via conductor portions 15 (B) (19 (B)) are connected to the electrode conductor layers 14 and 17 from the first terminal array 5 side at the first arrangement interval d1. From the two-terminal array 7 side, via conductor portions 15 ″ (55) are connected at a second arrangement interval d2 wider than the first arrangement interval d1. That is, the interval conversion layer LT is connected to the upper and lower sides thereof. The terminal conductors are converted by changing the connection positions of the via conductors, and the via conductors 15 (B) (19 (B)) and 15 connected to the upper and lower sides of the interval conversion layer LT. The arrangement interval of (55) can be designed on the basis of, for example, an equidistant arrangement. However, the arrangement interval may be locally changed in order to avoid interference with a via conductor portion having a different polarity. The intervals are not necessarily equal. The first arrangement interval d1 and the second arrangement interval d2 are expressed by an average value of the intervals between the edges of the plurality of via conductor portions in consideration of such a case.
[0038]
In the intermediate substrate 1 with a built-in capacitor according to the present embodiment, the terminal interval expansion conversion is performed as described above, and the array area of the second terminal array 7 is larger than that of the first terminal array 5. Therefore, using the difference in area, a part of the set of the first-type electrode conductor layer 14 and the second-type electrode conductor layer 17 arranged on the second main surface side of the polymer multilayer capacitor unit 10, Here, the lowermost two layers 14 (W) and 17 (W) have a larger area than the combination of the first-type electrode conductor layer 14 and the second-type electrode conductor layer 17 arranged on the first main surface side. . Thereby, the electrostatic capacitance of the intermediate substrate 1 with a built-in capacitor can be further increased.
[0039]
Further, both the first-type electrode conductor layer 14 and the second-type electrode conductor layer 17 are used as the interval conversion layer LT, and the first-type electrode conductor layer 14 is a via conductor that is electrically connected to the first-type terminal 5a. The second type electrode conductor layer 17 is used for expanding the interval of the via conductor portion 19 that is electrically connected to the second type terminal 5b. Specifically, since it is possible to secure a large distance conversion amount, a set of the first-type electrode conductor layer 14 and the second-type electrode conductor layer 17 whose area is expanded as compared with other films (that is, the lowermost two layers 14). (W) and 17 (W)) are used as the interval conversion layers LT and LT (however, all the electrode conductor layers 14 and 17 except the uppermost layer may be used as the interval conversion layers LT).
[0040]
Next, in addition to the first type terminal 5a and the second type terminal 5b, the signal terminal described above is assigned to the first main surface of the polymer multilayer capacitor unit 10 in addition to the outer peripheral region of the first terminal array 5. A plurality of 5s are formed. These signal terminals 5 s are not electrically connected to the electrode conductor layers 14 and 17 in the polymer multilayer capacitor portion 10 with respect to the signal base-side terminals 7 s formed on the second main surface of the multilayer ceramic capacitor base 60. (In this embodiment, the electrode conductor layers 14 and 17 are detoured outwardly in the in-plane direction), the signal via conductor portion 22 in the polymer multilayer capacitor portion 10 and the signal via in the multilayer ceramic capacitor substrate 60. The conductors 51s are connected to each other.
[0041]
In the embodiment of FIG. 4, the first terminal array 5 is formed so as to be included in the second terminal array 7 in a projection relationship, and the terminals located on the outer side of the array are arranged as the arrangement interval increases. There is a large amount of misalignment between corresponding terminals. Accordingly, the signal terminals 5 s arranged in the outer peripheral area of the first terminal array 5 are routed in the in-plane direction formed in the polymer multilayer capacitor portion 10 in order to connect to the corresponding signal base-side terminals 7 s. It is necessary to secure the wiring part 21 for a long time. In this embodiment, since the terminal interval conversion amount from the first terminal array 5 to the second terminal array 7 is set to be relatively large, the routing wiring portion 21 of the signal terminal 5s located on the inner side is connected to the outer signal. In order to avoid interference in the in-plane direction with the routing wiring portion 21 of the terminal 5s, both wiring portions 21 and 21 are formed in different layers. However, when the terminal interval conversion amount is not so large, it is possible to form the routing wiring portion 21 of the inner and outer signal terminals 5s in the same layer. In the above embodiment, the signal terminal 5s is formed so as to allocate the outer peripheral area of the first terminal array 5. However, in order to improve the shielding property of the signal line and to suppress the crosstalk, the signal terminal It is also possible to surround 5s (and a signal line that conducts to it) with a ground terminal (and a ground line that conducts to it).
[0042]
Hereinafter, modified examples of the intermediate substrate with a built-in capacitor according to the present invention will be described.
In the intermediate substrate 100 of FIG. 6, the connection positions of the upper and lower via conductor portions 59 and 55 are different between the fired electrode conductor layers 57 and 54 in the multilayer ceramic capacitor substrate 60 in the same manner as the distance conversion thin film LT in the thin film capacitor 10. A terminal interval conversion layer LT ′ is used, and the terminal interval conversion is performed by the multilayer ceramic capacitor substrate 60. Here, a thin film LT for distance conversion is also provided in the thin film capacitor 10 to widen the arrangement interval of the via conductor portions 15 and 19 to an appropriate distance, and further, by the terminal space conversion layer LT ′ in the multilayer ceramic capacitor substrate 60, The terminal interval conversion is performed in two stages by widening the arrangement interval of the substrate-side coupling conductor portions 59 and 55 (of course, the terminal interval conversion may be performed only in the multilayer ceramic capacitor substrate 60). .
[0043]
Further, in the intermediate substrate 100 of FIG. 7, the terminal arrangement interval between the first terminal array 5 and the second terminal array 7 is set to be the same. In this case, as shown in FIG. 8, the interval conversion layers LT and LT are not formed.
[Brief description of the drawings]
FIG. 1 is a schematic side view showing an example in which a capacitor of the present invention is configured as an intermediate substrate.
FIG. 2 is an equivalent circuit diagram illustrating an example of a usage pattern of a decoupling capacitor for an integrated circuit.
FIGS. 3A and 3B are a plan view and a side cross-sectional schematic view showing the capacitor of the present invention in FIG.
4 is a cross-sectional view showing a detailed structure of the capacitor of FIG. 3;
FIG. 5 is a schematic view illustrating a planar form of an electrode conductor layer.
6 is a cross-sectional view showing a first modification of the capacitor of FIG. 4;
FIG. 7 is a plan view and a side cross-sectional schematic view showing a second modified example.
8 is a schematic enlarged cross-sectional view of the main part of FIG.
[Explanation of symbols]
1,100,200 Intermediate board with built-in capacitor
5 First terminal array
5a Type 1 terminal
5b Type 2 terminal
5s signal terminal
7 Second terminal array
7a Type 1 substrate side terminal
7b Type 2 substrate side terminal
7s Signal base terminal
10 Polymer multilayer capacitors
13 Polymer dielectric layer
13h Through hole
13v Dielectric hole filling part
14 First kind electrode conductor layer
15, 19 Via conductor
17 Second-class electrode conductor layer
16, 18 through hole
57 First-class fired electrode conductor layer
54 Second-class fired electrode conductor layer
59, 55 Via conductor
60 Multilayer ceramic capacitor substrate
LT, LT 'interval conversion layer

Claims (8)

A multilayer ceramic capacitor substrate in which first-type fired electrode conductor layers and second-type fired electrode conductor layers separated from each other in direct current are alternately laminated with fired ceramic dielectric layers fired simultaneously with the fired electrode conductors; ,
The first-type electrode conductor layer provided on the first main surface of the multilayer ceramic capacitor substrate and conducting to the first-type fired electrode conductor layer; and the second-type electrode conducting to the second-type fired electrode conductor layer A conductor layer and a polymer multilayer capacitor portion alternately laminated with polymer dielectric layers in a form separated from each other in a direct current manner;
On the first main surface of the polymer multilayer capacitor, a first terminal array comprising a first type terminal and a second type terminal respectively conducting to the first type electrode conductor layer and the second type electrode conductor layer is formed. ,
A second main surface of the multilayer ceramic capacitor substrate is provided with a first-type substrate-side terminal and a second-type substrate-side terminal respectively connected to the first-type sintered electrode conductor layer and the second-type sintered electrode conductor layer. An intermediate substrate with a built-in capacitor, wherein a two-terminal array is formed. The intermediate substrate with a built-in capacitor according to claim 1, wherein the fired ceramic dielectric layer is made of a high dielectric constant ceramic. 3. The capacitor built-in intermediate substrate according to claim 2, wherein the high dielectric constant ceramic is made of one or more of barium titanate, strontium titanate and lead titanate. The intermediate substrate with a built-in capacitor according to claim 1, wherein the fired ceramic dielectric layer is made of any one of alumina, glass ceramic, aluminum nitride, silicon nitride, mullite, silicon dioxide, and magnesium oxide. In the first main surface of the polymer multilayer capacitor portion, the first type electrode conductor layer and the first type terminal forming the first terminal array and the second type terminal are closest to the first main surface, and 5. The capacitor built-in intermediate substrate according to claim 1, wherein the intermediate substrate is built-in according to claim 1, wherein the intermediate substrate is coupled to the second-type electrode conductor layer directly or via an auxiliary via conductor in the stacking direction. 6. The capacitor built-in intermediate substrate according to claim 1, wherein a terminal arrangement interval of the second terminal array is set wider than a terminal arrangement interval of the first terminal array. In the polymer multilayer capacitor portion, a plurality of the first type electrode conductor layers and a plurality of the second type electrode conductor layers are alternately stacked via the polymer dielectric layers, and a plurality of the first type electrode conductor layers are stacked. The electrode conductor layers and the plurality of second-type electrode conductor layers are respectively coupled in the laminating direction at the via conductor portions,
At least one of the electrode conductor layers is connected to the electrode conductor layer from the first terminal array side to the electrode conductor layer at a first arrangement interval, while the first conductor array layer side is connected to the electrode conductor layer from the second terminal array side. The intermediate substrate with a built-in capacitor according to claim 6, wherein the intermediate layer is an interval conversion layer to which the via conductor portions are connected at a second arrangement interval wider than one arrangement interval. In the multilayer ceramic capacitor substrate, a plurality of the first-type fired electrode conductor layers and a plurality of the second-type fired electrode conductor layers are alternately laminated via the fired ceramic dielectric layers, Seed-fired electrode conductor layers and a plurality of the second-type fired electrode conductor layers are bonded to each other in the laminating direction at via conductor portions,
At least one layer of the fired electrode conductor layer is connected to the fired electrode conductor layer from the first terminal array side to the fired electrode conductor layer at a first arrangement interval, while the fired electrode conductor layer is connected from the second terminal array side. 8. The capacitor built-in intermediate substrate according to claim 6, wherein the via conductor portions are connected to each other at a second array interval wider than the first array interval.

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