JP2004535062A5

JP2004535062A5 -

Info

Publication number: JP2004535062A5
Application number: JP2003505987A
Authority: JP
Filing date: 2001-06-14
Publication date: 2005-05-26

Claims

Silicon substrate wafer,
A barrier comprising at least one insulating layer and / or a semiconductor layer sandwiched between epitaxial silicon layers deposited on the silicon substrate wafer;
With
Each of the insulating layers and / or semiconductor layers includes a single layer of deposited oxygen or less than a single layer of oxygen so that epitaxial silicon can be deposited on the layer of oxygen. ,
The top layer of epitaxial silicon is sufficiently thick so that the top layer of epitaxial silicon is of device quality,
SOI (silicon on insulator) wafer useful in the manufacture of semiconductor devices.

The resistance of the barrier layer is equal that of 10 ⁴ times higher epitaxial silicon thickness,
The wafer according to claim 1.

The total amount of oxygen deposited to form the insulating layer and / or semiconductor layer is varied to control the dielectric constant and capacitance of the insulating layer and / or semiconductor layer;
The wafer according to claim 1.

The total amount of oxygen deposited to form the insulating layer and / or the semiconductor layer is varied to control the barrier height of the barrier layer of the insulating layer and / or the semiconductor layer;
The wafer according to claim 1.

The wafer of claim 1 wherein the thickness of the top layer of silicon is 4 to 7 microns.

A wafer useful in the manufacture of semiconductor devices including silicon substrate wafers,
Silicon substrate wafer,
A barrier comprising at least one insulating layer and / or a semiconductor layer sandwiched between epitaxial silicon layers deposited on said silicon substrate wafer;
With
Each insulating layer and / or semiconductor layer includes at least one additional element deposited such that device quality epitaxial silicon can be deposited on the deposited element;
The additional element is selected from the group consisting of carbon, nitrogen, phosphorus, sulfur, hydrogen, antimony, and arsenic, and combinations thereof;
Wafer.

An insulating layer closest to the substrate is deposited directly on the silicon substrate wafer;
The wafer according to claim 1 or 6.

At least one layer of epitaxial silicon or oxygen is deposited by chemical vapor deposition,
The wafer according to claim 1, 6 or 7.

A defect reflection layer or at least one strain lattice barrier is between the top of the epitaxial silicon layer and the insulating and / or semiconductor layer closest to the top layer. Deposited on the
The wafer according to claim 1 or 6.

An insulating layer and / or a semiconductor layer consisting of silicon deposited on single crystal silicon and at least one additional element;
By providing
The insulating layer and / or semiconductor layer is substantially defect free, and epitaxial silicon that is substantially defect free, i.e. device quality, is deposited on the insulating layer and / or semiconductor layer. obtain,
A useful barrier composite for semiconductor devices.

The additional element is selected from the group consisting of oxygen, carbon, nitrogen, phosphorus, sulfur, hydrogen, antimony, and arsenic, and combinations thereof;
The barrier composite according to claim 10.

The additional element is oxygen, the deposited layer consists of SiOx, 0 <x <2.0,
The barrier composite according to claim 10.

The dielectric constant of the insulating layer and / or semiconductor layer is varied by changing the oxygen density in the insulating layer and / or semiconductor layer;
The barrier composite according to claim 12.

The barrier of claim 12, wherein oxygen and silicon are deposited simultaneously.

Sandwiched between single crystal silicon,
At least one insulating layer and / or semiconductor layer barrier or SiOx (0 <x <2.0) deposited layer adsorbed on silicon, monolayer or less than monolayer, oxygen layer Comprising at least one insulating layer and / or barrier of the semiconductor layer,
The semiconductor device includes a resonant tunneling device, a single electron field transistor, a quantum well device, a metal oxide semiconductor field effect transistor, and an integrated circuit device. With a structure selected from the containing group,
Semiconductor element.

The barrier is used, at least in part, to replace a layer of SiO ₂ between the device's metal contacts and silicon;
The metal oxide semiconductor field effect transistor according to claim 15.

A semiconductor element sandwiched between single crystal silicon,
At least one insulating layer and / or semiconductor layer barrier adsorbed on silicon, monolayer or less than monolayer, oxygen layer, or SiOx (0 <x <2.0) Comprising at least one insulating layer and / or a semiconductor layer barrier of the deposited layer of
The semiconductor element comprises more than one element layer, wherein the element layer is at least partially separated by the barrier;
Semiconductor element.

A method for forming a barrier layer useful for a semiconductor device on a silicon substrate, comprising:
Depositing an epitaxial layer of silicon on the substrate;
Next, depositing an adsorbed layer on which at least one additional element is adsorbed on the layer of epitaxial silicon.
By including steps
The deposited layer is substantially defect free in the sense that epitaxial silicon of device quality can be deposited on the deposited layer;
At least one of the layer containing at least one additional element or the layer of epitaxial silicon is deposited using chemical vapor deposition,
Method.

By depositing a layer on the substrate wherein at least one additional element is adsorbed on the silicon substrate,
The deposited layer is substantially defect free in the sense that device quality epitaxial silicon can be deposited on the deposited layer; and
At least one of the layers comprising at least one additional element, or the epitaxial silicon is deposited using chemical vapor deposition,
A method for forming a barrier layer useful for semiconductor devices on a silicon substrate.

A plurality of insulating layers and / or semiconductor layers are deposited;
Forming a barrier comprising a plurality of insulating layers and / or semiconductor layers sandwiched between single crystal silicon layers;
20. A method according to claim 18 or 19.

The additional element is selected from the group consisting of oxygen, carbon, nitrogen, phosphorus, sulfur, hydrogen, antimony, and arsenic, and combinations thereof;
21. A method according to claim 18, 19 or 20.

The method of claim 21, wherein the additional element in at least one layer is oxygen deposited as a single layer or less than a single layer.

The additional element in at least one layer is oxygen combined with silicon and deposited as SiOx (0 <x <2.0);
The method of claim 21.