JP2004363187A - Semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a thermal stress imposed on the surface of a semiconductor chip in a ball grid array semiconductor package so as to prevent the circuit element of the semiconductor chip from malfunctioning. <P>SOLUTION: The semiconductor chip 13 is mounted on the one surface of a board 11, a dummy chip 16 formed of a semiconductor wafer whose coefficient of thermal expansion is approximate to that of the semiconductor chip 13 is superposed on the semiconductor chip 13, and a metal plate 18 having a coefficient of thermal expansion approximate to the one possessed by the board 11 is provided on the dummy chip 16. The one surface of the board 11 is sealed up together with the semiconductor chip 13 and the dummy chip 16 with a molding resin layer 20, and the metal plate 18 is embedded in the molding resin layer 20 so as to expose its one surface to the outside. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which heat dissipation is improved and thermal stress of a semiconductor chip is reduced.
[0002]
[Prior art]
In response to demands for smaller and lighter electronic devices, miniaturization and higher integration of semiconductor chips have been attempted. A semiconductor chip is usually sealed with a resin to form a package, and mounted on a printed wiring board or the like. However, as the size of the semiconductor chip has been reduced in size and density as in recent years, the amount of heat generated by the semiconductor chip increases, and natural heat radiation from the semiconductor package cannot cope with the problem, causing a failure of the semiconductor chip.
[0003]
Therefore, conventionally, in order to improve the heat dissipation of the semiconductor package, a structure in which a metal plate having excellent heat conductivity is bonded to the surface of the semiconductor chip to dissipate heat has been proposed (for example, Patent Documents 1 and 2). ). This structure is effective as a measure against heat because heat can be directly radiated from the surface of the semiconductor chip via the metal plate. However, due to the difference in the coefficient of thermal expansion between the semiconductor chip and the metal plate, thermal stress may act on the surface of the semiconductor chip and cause a malfunction. This is caused by a change in electrical characteristics such as a resistance value of a specific circuit element due to, for example, a piezoresistance effect under the influence of thermal stress acting on the surface of the semiconductor chip.
[0004]
Further, when applying a heat dissipation structure using the above-mentioned metal plate to a ball grid array (hereinafter abbreviated as BGA) type semiconductor package which has recently become mainstream due to a demand for a thinner semiconductor package, a BGA type semiconductor package has been developed. The half-mold structure, that is, a structure in which a semiconductor chip is mounted on one surface of a substrate and one surface is sealed together with the semiconductor chip by a mold resin layer, the stress of the entire package cannot be balanced, and warpage may occur. A problem arises in that it cannot be put to practical use.
[0005]
As shown in FIG. 4, a metal plate 4 having a coefficient of thermal expansion similar to that of the substrate 1 is provided on the surface of the mold resin layer 3 at a distance from the semiconductor chip 2 on the substrate 1 to prevent the warpage of the BGA type semiconductor package. 5, a metal plate 8 having a smaller coefficient of thermal expansion than a mold resin layer 7 is attached to a semiconductor chip 6 on a substrate 5 as shown in FIG. (For example, Patent Document 4).
[0006]
[Patent Document 1]
JP-A-5-82672
[Patent Document 2]
JP-A-7-107921
[Patent Document 3]
Japanese Patent Application Laid-Open No. 10-116936
[Patent Document 4]
JP 2000-31343 A
[Problems to be solved by the invention]
However, in the structure of FIG. 4, even though a certain effect is exhibited for reducing the warpage, the heat dissipation effect cannot be expected so much because the mold resin 3 enters between the semiconductor chip 2 and the metal plate 4. The allowable power consumption of the chip 2 is restricted. In the structure shown in FIG. 5, since the metal plates 8 having different coefficients of thermal expansion are attached to the surface of the semiconductor chip 6, there is a possibility that a thermal stress acts on the semiconductor chip 6 to cause a malfunction.
[0011]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a ball grid array type semiconductor package capable of reducing thermal stress acting on the surface of a semiconductor chip and preventing malfunction of circuit elements of the semiconductor chip. Is to do.
[0012]
[Means for Solving the Problems]
The present invention provides a dummy layer having a coefficient of thermal expansion close to that of a semiconductor chip mounted on a semiconductor chip mounted on one surface of a substrate, and a metal layer having a coefficient of thermal expansion close to that of the substrate stacked on the dummy layer. The semiconductor device is characterized in that one surface of the substrate is sealed by the mold resin layer together with the semiconductor chip and the dummy layer by the mold resin layer, and the metal layer is embedded in the mold resin layer so that the one surface is exposed to the outside.
In this case, the dummy layer can be composed of a semiconductor wafer.
[0013]
According to the present invention having this configuration, since the coefficient of thermal expansion of the dummy layer superimposed on the semiconductor chip is close to that of the semiconductor chip, thermal stress acting on the surface of the semiconductor chip can be reduced, and malfunction can be prevented. Can be. In addition, since the coefficient of thermal expansion of the metal layer on the side opposite to the substrate is close to that of the substrate, the semiconductor package as a whole can be balanced in stress, and can have a low stress structure without warpage or deformation. Further, since the dummy layer and the metal layer are sequentially stacked on the semiconductor chip, and at least one surface of the metal layer is exposed to the outside, the structure has excellent heat dissipation, and the allowable power consumption of the semiconductor chip is increased. Can be.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment in which the present invention is applied to a ball grid array type semiconductor package will be described with reference to FIG.
FIG. 1 is a cross-sectional view of a ball grid array type semiconductor package. In FIG. 1, a substrate 11 is made of a printed wiring board such as a glass epoxy resin substrate or a polyimide resin substrate having a thickness of 0.5 to 0.7 mm. A large number of connection terminals and a wiring pattern (both not shown) connecting these connection terminals are formed on the surface, which is one surface thereof, by printing means. A ball grid array type terminal electrically connected to required connection terminals among the connection terminals formed on the front surface, for example, through through holes (not shown), That is, a large number of balls 12 made of solder are arranged in a grid.
[0015]
On the surface of the substrate 11, a semiconductor chip 13 is fixed by an adhesive or an adhesive sheet. The semiconductor chip 13 is connected to connection terminals of the substrate 1 by bonding wires 15. This bonding wire 15 is made of a thin wire such as Au, Al, or Cu.
[0016]
A dummy chip 16 as a dummy layer is fixed by an adhesive sheet 17 in a region where the circuit elements are formed on the surface of the semiconductor chip 13 except for a wire bond pad. The dummy chip 16 has a coefficient of thermal expansion similar to that of the semiconductor chip 13, and in this embodiment, the same base material as the semiconductor chip 13, ie, the same material as the semiconductor chip 13 if the semiconductor chip 13 is a Si wafer. Is formed from. The dummy chip 16 is obtained by merely processing a wafer to a predetermined thickness (0.1 to 0.4 mm), and has no circuit element formed on the surface thereof.
[0017]
The fixing of the dummy chip 16 is performed by a commonly used stack method. That is, an adhesive sheet 17 having a thermosetting resin such as epoxy or polyimide as a base resin is adhered to the entire surface of the dummy chip 16, and is smaller in size than the semiconductor chip 13 (for example, 4 mm in the case of a 5 mm square semiconductor chip). A dicing process is performed on the (corner), picked up by a die mount, and mounted at the center of the surface of the semiconductor chip 13.
[0018]
On the surface of the dummy chip 16, a metal plate 18 as a metal layer is fixed by an adhesive sheet 19. The fixing of the metal plate 18 is also performed by the same stack method as that of the dummy chip 16. The metal plate 18 is made of, for example, a Ni alloy, an Fe alloy, an Au alloy, or the like, whose thermal expansion coefficient is close to that of the substrate 11 in order to balance thermal expansion.
[0019]
The thickness of the metal plate 18 is substantially the same as that of the substrate 11, and the size is such that it occupies almost the entire surface (upper surface) of the package when completed as a package. For example, when the surface size of the package is 10 mm square, the metal plate 18 is 9 mm square.
The thickness of the adhesive sheets 14, 17, 19 is preferably about 20 μm.
[0020]
The surface of the substrate 11 is sealed by the mold resin layer 20 together with the semiconductor chip 13 and the dummy chip 16. The metal plate 18 is further embedded in the mold resin layer 20 so that the upper surface, which is one surface thereof, is exposed to the outside. The mold resin layer 20 is based on a thermosetting resin such as an epoxy resin, and after a semiconductor chip 13, a dummy chip 16, and a metal plate 18 are sequentially stacked and fixed on a substrate 11, a molding die (not shown) is used. )).
[0021]
According to the semiconductor package having the above-described configuration, the dummy chip 16 is fixed to the surface of the semiconductor chip 13 on which the circuit elements are formed, and the coefficient of thermal expansion of the dummy chip 16 is similar to that of the semiconductor package 13. Since the thermal expansion coefficient is substantially the same as that of the semiconductor chip 13 by being formed from the same Si wafer as above, the thermal stress acting on the surface of the semiconductor lip 13 can be reduced. Therefore, it is possible to prevent the influence on the circuit element formed on the surface of the semiconductor chip 13, for example, the fluctuation of the resistance value.
[0022]
Further, the heat conductivity of the Si wafer, which is the material of the dummy chip 16, is 100 times or more higher than that of the epoxy, which is the material of the mold resin layer 23. be able to. Further, the metal plate 18 is fixed on the dummy chip 16, and the upper surface of the metal plate 18 is exposed to the outside, so that the heat transmitted from the semiconductor chip 13 to the dummy chip 16 is outside the metal plate 18. It can be efficiently released into the atmosphere. As described above, in the present embodiment, a semiconductor package having excellent heat dissipation, which can secure a heat dissipation path having excellent heat conductivity for dissipating the heat of the semiconductor chip 13 to the outside, can be obtained.
[0023]
Further, in this embodiment, the metal plate 18 is fixed not to the semiconductor chip 13 but to the dummy chip 16 on which no circuit element is formed, so that the metal plate 18 can be made larger than the dummy chip 16. Moreover, since the dummy chip 16 is a mere Si plate having no circuit elements, there is no problem even if thermal stress acts on the dummy chip 16.
Further, since the coefficient of thermal expansion of the metal plate 18 is approximated to that of the substrate 11, the stress of the entire semiconductor package can be balanced, and the warpage and deformation of the semiconductor package can be reduced.
[0024]
FIG. 2 and FIG. 3 show second and third embodiments of the present invention. The second embodiment of FIG. 2 is different from the first embodiment in that a plurality of, for example, two, semiconductor chips 21 and 22 are mounted on the substrate 11 one above the other, and the surface of the upper semiconductor chip 22 is formed. At the place where the dummy chip 16 is fixed.
The third embodiment of FIG. 3 differs from the first embodiment in that the semiconductor chip 23 is face-down bonded.
[0025]
The present invention is not limited to the embodiment described above and shown in the drawings.
Dummy chips are not limited to those formed from a wafer as long as the coefficient of thermal expansion is similar to that of a semiconductor chip.
The present invention is not limited to a ball grid array type semiconductor package, and can be widely applied to a semiconductor device having a terminal for external connection on the back surface of a substrate.
[Brief description of the drawings]
FIG. 1 is a sectional view of a semiconductor package showing a first embodiment of the present invention; FIG. 2 is a diagram corresponding to FIG. 1 showing a second embodiment of the present invention; FIG. 3 is a diagram showing a third embodiment of the present invention; FIG. 4 is an equivalent view of FIG. 1 showing an example of the related art. FIG. 5 is an equivalent view of FIG. 1 showing another example of the related art.
In the figure, 11 is a substrate, 12 is a ball (ball grid array type terminal), 13 is a semiconductor chip, 16 is a dummy chip (dummy layer), 18 is a metal plate (metal layer), 20 is a mold resin layer, 21 to 21. 23 is a semiconductor chip.

Claims (2)

A substrate provided with connection terminals on one side,
A semiconductor chip mounted on the one surface of the substrate while being electrically connected to the connection terminal;
A dummy layer provided on the semiconductor chip and having a coefficient of thermal expansion similar to that of the semiconductor chip;
A metal layer provided on the dummy layer and having a coefficient of thermal expansion similar to that of the substrate;
A mold resin layer sealing the one surface of the substrate together with the semiconductor chip and the dummy layer and embedding the metal layer so that one surface thereof is exposed to the outside;
A semiconductor package comprising: a terminal provided on the other surface of the substrate so as to be electrically connected to the connection terminal on the one surface. 2. The semiconductor package according to claim 1, wherein said dummy layer is made of a semiconductor wafer.

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