JP2004342724A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make elements in an element region stable in characteristics so as to restrain the elements from varying in characteristics. <P>SOLUTION: A semiconductor device is equipped with the element region 11 positioned between element isolating regions 12 formed in a semiconductor substrate 10; a gate electrode G, a source region S, and a drain region D provided corresponding to the element region 11; a first insulating film 21 formed on the element region 11 and the element isolating regions 12 so as to cover the gate electrodes G; a contact hole electrode C1 formed penetrating through the first insulating film 21 so as to be electrically connected to the source region S and the drain region D in the element region 11, respectively; and a dummy contact DC provided at a position nearly symmetrical to that of the contact hole electrode C1 in the element region 11 about the gate electrode G through the first insulating film 21. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to the arrangement and formation of contact holes in a MIS (Metal Insulator Semiconductor) transistor provided on a semiconductor substrate.
[0002]
[Prior art]
Conventionally, in a device using a semiconductor substrate such as silicon, usually after forming a MIS transistor, SiN (silicon nitride) is used as an etching stopper layer for preventing excessive etching of a contact hole and a stopper layer for hydrogen and moisture from above. ) was formed to a thickness of 30 to 50 nm, a technique for forming SiO ₂ can take the SiN etch selectivity thereon (silicon oxide) as the insulating layer of the MIS transistor and the first metal layers is common.
[0003]
Here, SiO ₂ generally has a compressive stress, and SiN becomes a film having a compressive stress or a tensile stress depending on the method of forming the film. It is known that the stress applied to the channel portion of the MIS transistor depends on the stress of the SiN film (see Non-Patent Documents 1 and 2).
[0004]
[Non-patent document 1]
S. Ito et al. , "Mechanical Stress Effect of Etch-Stop Nitride and it's Impact on Deep Sub-micron Transistor Design", IEEE, 2000.
[Non-patent document 2]
F. Ootsuka et al. , "A Highly Dense, High-Performance 130 nm node CMOS Technology for Large Scale System-On-a-Chip Applications", IEEE, 2000.
[0005]
[Problems to be solved by the invention]
As described above, since the stress applied to the channel portion of the MIS transistor affects the mobility of carriers, there arises a problem that the capability of the MIS transistor varies. The stress of the channel portion depends on the magnitude of the stress of the SiN film and the size of the SiN flat portion around the MIS transistor, that is, the peripheral layout. For this reason, there arises a problem that the capability of the MIS transistor in the same chip varies depending on the layout, and variation occurs.
[0006]
[Means for Solving the Problems]
The present invention has been made to solve such a problem. That is, the present invention provides an element region provided between element isolation regions formed on a semiconductor substrate, a gate electrode formed corresponding to the element region, a source region, a drain region, and an element for covering the gate electrode. An insulating film formed on the region and the element isolation region, a contact hole electrode provided through the insulating film to be electrically connected to the source region and the drain region in the element region, and a gate electrode in the element region. And a dummy contact provided through the insulating film at a position substantially symmetric to the position of the contact hole electrode.
[0007]
A step of forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region; and forming an element region and an element for covering the gate electrode. Forming an insulating film on the isolation region; forming a dummy contact at a position corresponding to the source region and the drain region in the element region so as to penetrate the insulating film; and forming another insulating film so as to cover at least the dummy contact. A method of manufacturing a semiconductor device, comprising: a step of forming a film; and a step of forming a contact hole electrode in a device region, penetrating an insulating film at a position substantially symmetric to a position of a dummy contact with respect to a gate electrode. is there.
[0008]
A step of forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region; and forming an element region and an element for covering the gate electrode. Forming an insulating film on the isolation region, forming a contact hole electrode in a position corresponding to the source region and the drain region in the element region so as to penetrate the insulating film, and forming a contact with the gate electrode in the element region. Forming a dummy contact so as to penetrate the insulating film at a position substantially symmetric to the position of the hole electrode; forming another insulating film so as to cover the contact hole electrode and the dummy contact; Forming a connection electrode that penetrates the other insulating film and conducts to the contact hole electrode at the position of the contact hole electrode in It is a manufacturing method of a semiconductor device and a degree.
[0009]
A step of forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region; and forming an element region and an element for covering the gate electrode. Forming an insulating film on the isolation region, forming a dummy contact made of an insulating material in a state corresponding to the source region and the drain region in the element region, and penetrating the insulating film; Forming a contact hole electrode so as to penetrate the insulating film at a position substantially symmetric to the position of the dummy contact with respect to the gate electrode.
[0010]
In the present invention, since the dummy contact is provided in the element region at a position substantially symmetrical to the position of the contact hole electrode with respect to the gate electrode while penetrating the insulating film, the gate electrode is centered. The portions penetrating the insulating film are arranged almost uniformly around the periphery, and the characteristics of the element can be stabilized by making the stress applied from the insulating film to the channel uniform.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the present embodiment, and (a) to (c) show respective forms. That is, in the semiconductor device of the present embodiment, the device region 11 provided between the device isolation regions 12 formed on the semiconductor substrate 10, the gate electrode G formed corresponding to the device region 11, the source region S, The first insulating film 21 formed on the element region 11 and the element isolation region 12 for covering the drain region D and the gate electrode G, and the first insulating film 21 for electrically connecting with the source region S and the drain region D in the element region 11 respectively. A contact hole electrode C1 provided through the first insulating film 21; and a first insulating film 21 provided through the element region 11 at a position substantially symmetrical to the position of the contact hole electrode C1 with respect to the gate electrode G in the element region 11. Dummy contact DC.
[0012]
The configurations of the semiconductor devices shown in FIGS. 1A to 1C are different from each other due to the manufacturing process or the material. The dummy contact DC used in these semiconductor devices is provided so as to penetrate the first insulating film 21 similarly to the contact hole electrode C1, but does not conduct electrical connection with the outside.
[0013]
That is, the dummy contact DC is provided in order to eliminate unevenness in stress applied from the first insulating film 21 to the channel portion (below the gate electrode G) of the element region 11 due to the provision of the contact hole electrode C1. Therefore, the dummy contact DC is arranged at a position substantially symmetrical with the position of the contact hole electrode C1 with respect to the gate electrode G in the element region 11 (a position where the distance t from the center of the gate electrode G is substantially equal). Accordingly, the position of the contact hole penetrating through the first insulating film 21 is substantially symmetrical with respect to the position of the gate electrode G, and the stress applied from the first insulating film 21 to the channel can be made uniform.
[0014]
In the semiconductor device shown in FIG. 1A, a second insulating film 22 is stacked on a first insulating film 21 covering a gate electrode G and is flattened. The dummy contact DC is formed penetrating the first insulating film 21 and the second insulating film 22, and is insulated from the upper layer by a third insulating film 23 laminated thereon. On the other hand, the contact hole electrode C1 is provided penetrating the first insulating film 21, the second insulating film 22, and the third insulating film 23, and is electrically connected to the metal layer M provided in the fourth insulating film 24.
[0015]
In the semiconductor device shown in FIG. 1B, a second insulating film 22 is laminated and planarized on a first insulating film 21 covering a gate electrode G, and the first insulating film 21 and the second insulating film 22 are formed. Are provided so as to penetrate through the dummy contact DC and the contact hole electrode C1. In addition, while the third insulating film 23 laminated on the second insulating film 22 is insulated from the upper layer of the dummy contact DC, the connection electrode C2 is located at a position corresponding to the contact hole electrode C1 of the third insulating film 23. Is formed, and conduction with the metal layer M provided on the fourth insulating film 24 is achieved.
[0016]
In the semiconductor device shown in FIG. 1C, a second insulating film 22 is laminated on the first insulating film 21 covering the gate electrode G and flattened, and the first insulating film 21 and the second insulating film 22 are formed. Are provided so as to penetrate through the dummy contact DC and the contact hole electrode C1. Further, in this example, the dummy contact DC is made of an insulating material, and is insulated from the metal layer M immediately above. Accordingly, another insulating film for insulating the dummy contact DC from the upper layer is not required, and the metal layer M is provided on the second insulating film 22 to achieve conduction with the contact hole electrode C1.
[0017]
Next, the difference between the planar layout of the semiconductor device of the present embodiment and the conventional example will be described. 2A and 2B are schematic plan views illustrating a planar layout of a semiconductor device, wherein FIG. 2A is the present embodiment and FIG. 2B is a conventional example. That is, in the semiconductor device according to the present embodiment, the dummy contact DC is provided at a position substantially symmetrical to the contact hole electrode C1 with respect to the gate electrode G, whereas in the conventional semiconductor device, the gate electrode G is The contact hole electrode C1 is arranged asymmetrically as the center.
[0018]
As in the present embodiment, by opening the first insulating film 21 (see FIG. 1) serving as a stopper layer with the dummy contact DC, the stress applied to the channel portion from the first insulating film 21 can be reduced. Therefore, by providing the dummy contact DC and the contact hole electrode C1 symmetrically with respect to the gate electrode G, the stress applied to the channel portion from the first insulating film 21 becomes uniform, and the element characteristics can be stabilized.
[0019]
When a plurality of gate electrodes G are provided in the element region 11, the positional relationship between the contact hole electrode C1 and the dummy contact DC with respect to the gate electrode G and the positional relationship between the contact hole electrode C1 and the dummy contact DC with respect to the other gate electrodes G. Are made substantially equal, the stress from the first insulating film 21 to the channel portion corresponding to each gate electrode G can be made uniform, and variations in the characteristics of each element can be suppressed. .
[0020]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. 3 and 4 are schematic cross-sectional views for sequentially explaining a method for manufacturing the semiconductor device shown in FIG. First, the element region 11 and the element isolation region 12 and the MIS transistor are formed using a normal MIS transistor manufacturing method, and a first insulating film (stopper layer, for example, SiN) 21 and a second insulating film (SiN) are formed on the gate electrode G. An insulating layer, for example, SiO ₂ ) 22 is formed (see FIG. 3A).
[0021]
Next, using a normal photolithography technique and a dry etching technique, a contact hole is formed at the position of the dummy contact DC on the element region 11, and a conductor (for example, tungsten) is embedded. Thereby, a dummy contact DC penetrating the first insulating film 21 and the second insulating film 22 is formed (see FIG. 3B). Note that a dummy contact DC may be formed on the element isolation region 12 as necessary.
[0022]
Next, a third insulating film (an insulating layer, for example, SiO ₂ ) 23 is formed on the second insulating film 22 (see FIG. 3C). Thereby, the dummy contact DC is insulated from the upper layer.
[0023]
Next, using a normal photolithography technique and a dry etching technique, a contact hole is formed at a position to be the contact hole electrode C1, and a conductor (for example, tungsten) is embedded. Thus, a contact hole electrode C1 penetrating through the first insulating film 21, the second insulating film 22, and the third insulating film 23 is formed (see FIG. 4A).
[0024]
Thereafter, the fourth insulating film 24 and the metal layer M are formed by using a normal semiconductor manufacturing method, and conduction with the contact hole electrode C1 is obtained (see FIG. 4B). That is, after forming the fourth insulating film 24, the pattern of the metal layer M is dug into the fourth insulating film 24 to form a groove by using a normal photolithography technique and a dry etching technique, and a conductor (for example, , Cu) and by performing CMP (Chemical Mechanical Polishing) to bury the groove with a conductor to form the metal layer M.
[0025]
As a result, a dummy contact DC made of the same material as the contact hole electrode C1 is formed at a position substantially symmetrical with respect to the gate electrode G with respect to the contact hole electrode C1, and uniform mechanical stress is applied to a channel portion corresponding to the gate electrode G. Can be achieved.
[0026]
5 to 6 are schematic sectional views for sequentially explaining a method for manufacturing the semiconductor device shown in FIG. 1B. First, the element region 11 and the element isolation region 12 and the MIS transistor are formed using a normal MIS transistor manufacturing method, and a first insulating film (stopper layer, for example, SiN) 21 and a second insulating film (SiN) are formed on the gate electrode G. An insulating layer (for example, SiO ₂ ) 22 is formed (see FIG. 5A).
[0027]
Next, a contact hole is formed at the position of the contact hole electrode C1 and the dummy contact DC on the element region 11 using a normal photolithography technique and a dry etching technique, and a conductor (for example, tungsten) is embedded. As a result, a contact hole electrode C1 and a dummy contact DC penetrating the first insulating film 21 and the second insulating film 22 are formed (see FIG. 5B). Note that a contact hole electrode C1 and a dummy contact DC may be formed on the element isolation region 12 as necessary.
[0028]
Next, a third insulating film (insulating layer, for example, SiO ₂ ) 23 is laminated on the second insulating film 22, and a contact hole is formed at a position corresponding to the contact hole electrode C1 (see FIG. 5C). Then, a conductor (tungsten) is buried in the contact hole. Thus, the connection electrode C2 is formed on the contact hole electrode C1 (see FIG. 6A).
[0029]
Thereafter, the fourth insulating film 24 and the metal layer M are formed by using a normal semiconductor manufacturing method, and conduction with the contact hole electrode C1 and the connection electrode C2 is obtained (FIG. 6B). That is, after forming the fourth insulating film 24, the pattern of the metal layer M is dug into the fourth insulating film 24 to form a groove by using a normal photolithography technique and a dry etching technique, and a conductor (for example, , Cu), and the metal layer M is formed by filling the groove with a conductor by performing CMP.
[0030]
As a result, a dummy contact DC made of the same material as the contact hole electrode C1 is formed at a position substantially symmetrical with respect to the gate electrode G with respect to the contact hole electrode C1, and uniform mechanical stress is applied to a channel portion corresponding to the gate electrode G. Can be achieved.
[0031]
7 and 8 are schematic cross-sectional views for sequentially explaining a method for manufacturing the semiconductor device shown in FIG. First, the element region 11 and the element isolation region 12 and the MIS transistor are formed using a normal MIS transistor manufacturing method, and a first insulating film (stopper layer, for example, SiN) 21 and a second insulating film (SiN) are formed on the gate electrode G. An insulating layer (for example, SiO ₂ ) 22 is formed (see FIG. 7A).
[0032]
Next, using a normal photolithography technique and a dry etching technique, a contact hole is formed at the position of the dummy contact DC on the element region 11, and a conductor (insulating layer, for example, SiO ₂ ) is embedded. As a result, a dummy contact DC made of an insulating material penetrating the first insulating film 21 and the second insulating film 22 is formed (see FIG. 7B). Note that a dummy contact DC may be formed on the element isolation region 12 as necessary.
[0033]
Next, using a normal photolithography technique and a dry etching technique, a contact hole is formed at a position to be the contact hole electrode C1, and a conductor (for example, tungsten) is embedded. Thus, a contact hole electrode C1 penetrating the first insulating film 21, the second insulating film 22, and the third insulating film 23 is formed (see FIG. 8A).
[0034]
Thereafter, a fourth insulating film 24 is laminated on the second insulating film 22 by using a normal semiconductor manufacturing method, a metal layer M is formed, and conduction with the contact hole electrode C1 is obtained (FIG. 8B). . That is, after forming the fourth insulating film 24 on the second insulating film 22, the pattern of the metal layer M is dug into the fourth insulating film 24 to form a groove by using a normal photolithography technique and a dry etching technique. The metal layer M is formed by plating a conductor (for example, Cu) in the groove and performing CMP (Chemical Mechanical Polishing) to fill the groove with the conductor.
[0035]
In such a semiconductor device, since the dummy contact DC is made of an insulating material, it is not necessary to form an insulating film for insulating the metal layer M after the dummy contact DC is formed, and the metal layer M is formed directly. be able to. Therefore, it is possible to manufacture the semiconductor device in fewer steps as compared with other semiconductor devices.
[0036]
In the above-described embodiment, an example in which Si (silicon) is mainly used as a semiconductor substrate has been described. However, the present invention can be applied to another semiconductor substrate such as a compound semiconductor.
[0037]
【The invention's effect】
As described above, the present invention has the following effects. That is, the stress applied from the first insulating film covering the gate electrode to the channel portion can be made uniform, and the element characteristics of the MIS transistor and the like can be obtained. In addition, by arranging the dummy contacts without largely changing the contact layout, it is possible to suppress variations in the characteristics of the elements, and to improve the performance of the semiconductor device. In particular, if there is a large variation in performance due to the layout of elements such as MIS transistors, it is necessary to provide a wide margin for this variation during design. Designing with a large margin degrades device performance. Therefore, high-performance (eg, high-speed) devices can be designed and manufactured by using elements having small characteristic fluctuations.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view illustrating a semiconductor device according to an embodiment.
FIG. 2 is a schematic plan view illustrating a planar layout of a semiconductor device.
FIG. 3 is a schematic cross-sectional view (part 1) illustrating a method for manufacturing the semiconductor device shown in FIG. 1 (a).
FIG. 4 is a schematic cross-sectional view (part 2) for explaining the method for manufacturing the semiconductor device shown in FIG.
FIG. 5 is a schematic cross-sectional view (part 1) illustrating a method for manufacturing the semiconductor device shown in FIG. 1 (b).
FIG. 6 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device shown in FIG. 1B.
FIG. 7 is a schematic cross-sectional view (part 1) illustrating a method for manufacturing the semiconductor device shown in FIG. 1 (c).
FIG. 8 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device shown in FIG. 1 (c).
[Explanation of symbols]
Reference Signs List 10: semiconductor substrate, 11: element region, 12: element isolation region, 21: first insulating film, 22: second insulating film, 23: third insulating film, 24: fourth insulating film, C1: contact hole electrode C2: connection electrode, D: drain region, DC: dummy contact, G: gate electrode, M: metal layer, S: source region

Claims (7)

An element region provided between element isolation regions formed on the semiconductor substrate,
A gate electrode formed corresponding to the element region, a source region, a drain region,
An insulating film formed on the device region and the device isolation region to cover the gate electrode;
A contact hole electrode provided through the insulating film to be electrically connected to the source region and the drain region in the element region,
A semiconductor device, comprising: a dummy contact provided through the insulating film at a position substantially symmetrical to a position of the contact hole electrode with respect to the gate electrode in the element region. 2. The semiconductor device according to claim 1, wherein the dummy contact is made of the same material as the contact hole electrode. 2. The semiconductor device according to claim 1, wherein said dummy contact is made of an insulating material. When a plurality of the gate electrodes are provided, a positional relationship between the contact hole electrode and the dummy contact with respect to one gate electrode is substantially equal to a positional relationship between the contact hole electrode and the dummy contact with respect to another gate electrode. The semiconductor device according to claim 1, wherein: Forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region;
Forming an insulating film on the device region and the device isolation region to cover the gate electrode;
Forming a dummy contact at a position corresponding to the source region and the drain region in the element region so as to penetrate the insulating film, and forming another insulating film so as to cover at least the dummy contact;
Forming a contact hole electrode in the element region at a position substantially symmetrical to a position of the dummy contact with respect to the gate electrode so as to penetrate the insulating film. Method. Forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region;
Forming an insulating film on the device region and the device isolation region to cover the gate electrode;
A contact hole electrode is formed at a position corresponding to the source region and the drain region in the element region so as to penetrate the insulating film. Forming a dummy contact at a symmetrical position so as to penetrate the insulating film;
Forming another insulating film to cover the contact hole electrode and the dummy contact;
Forming a connection electrode at a position of the contact hole electrode in the other insulating film, the connection electrode penetrating the other insulating film and conducting to the contact hole electrode. Forming an element region separated by an element isolation region on a semiconductor substrate, forming a gate electrode, a source region, and a drain region corresponding to the element region;
Forming an insulating film on the device region and the device isolation region to cover the gate electrode;
Forming a dummy contact made of an insulating material so as to penetrate the insulating film at a position corresponding to the source region and the drain region in the element region;
Forming a contact hole electrode in the element region at a position substantially symmetrical to a position of the dummy contact with respect to the gate electrode so as to penetrate the insulating film. Method.

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