JP2004334956A - Threshold level write-in method of multi-level memory circuit - Google Patents

Threshold level write-in method of multi-level memory circuit Download PDF

Info

Publication number
JP2004334956A
JP2004334956A JP2003127705A JP2003127705A JP2004334956A JP 2004334956 A JP2004334956 A JP 2004334956A JP 2003127705 A JP2003127705 A JP 2003127705A JP 2003127705 A JP2003127705 A JP 2003127705A JP 2004334956 A JP2004334956 A JP 2004334956A
Authority
JP
Japan
Prior art keywords
threshold
threshold value
set
distribution
range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003127705A
Other languages
Japanese (ja)
Inventor
Shunji Nakada
俊司 中田
Original Assignee
Nippon Telegr & Teleph Corp <Ntt>
日本電信電話株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegr & Teleph Corp <Ntt>, 日本電信電話株式会社 filed Critical Nippon Telegr & Teleph Corp <Ntt>
Priority to JP2003127705A priority Critical patent/JP2004334956A/en
Publication of JP2004334956A publication Critical patent/JP2004334956A/en
Application status is Pending legal-status Critical

Links

Images

Abstract

An object of the present invention is to enable high-speed writing of a multi-valued threshold value to a memory cell.
A threshold value is set in one of an upper region and a lower region in accordance with a threshold value corresponding to write data, and in a next step, a narrower upper region or a lower region is set. The threshold is set to one of the threshold distribution ranges, and the same steps are repeated thereafter to quickly set the threshold corresponding to the write data.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method of writing a threshold value in a multi-level memory circuit, which can write a desired threshold value at a high speed.
[0002]
[Prior art]
The operation of a conventionally known binary flash memory and multi-level flash memory will be described. A flash memory has a control gate and a floating gate, and is a nonvolatile memory element that can be electrically erased in a batch.The charge is injected into the floating gate using a tunnel current or using hot electrons. In "writing", electrons are injected into the floating gate to set the threshold to a high voltage value, and in "erasing", electrons are emitted from the floating gate to set the threshold to a low voltage value.
[0003]
FIG. 6A shows a threshold distribution set in a memory cell of a normal binary flash memory. When the voltage of the word line (not shown) is 0 V, a current flows through the memory cell if the threshold is "1", and no current flows if the threshold is "0". Thus, the threshold value of “1” and “0” of the memory cell is determined depending on whether the current flows or not. Therefore, one memory cell stores 1-bit data.
[0004]
Next, FIG. 6B shows a multi-valued threshold distribution in which two bits of data are stored in one memory cell. This is an example of a threshold distribution corresponding to four data (four values) of “11”, “10”, “01”, and “00”. FIG. 6C shows a multi-valued threshold distribution in which one memory cell stores 3-bit data. This is an example of a threshold distribution corresponding to eight data (eight values).
[0005]
Next, a method of writing a threshold value corresponding to data will be described. FIG. 7A shows a threshold distribution in a case where the threshold value is written five times without performing the verify operation. The upper arrow 71 shows how the threshold value changes as a function of the number of times of writing for the fastest writing (highest charge injection efficiency) memory cell. On the other hand, the lower arrow 72 indicates a similar characteristic in the case of a memory cell in which writing is the slowest (charge injection efficiency is the slowest). As described above, when the number of times of writing is the same, the threshold value becomes higher in a memory cell in which writing is fast, and becomes lower in a memory cell in which writing is slow, so that a distribution of a target threshold value is expanded in a plurality of memory cells.
[0006]
Next, the write characteristics in the case where the verification is performed will be described with reference to FIG. The memory cell to which writing is the fastest reaches the target threshold voltage Vref after three writings (arrow 71), so that writing is not performed thereafter. The memory cell with the slowest writing reaches the target threshold voltage Vref with five writings (arrow 72), so that writing is not performed thereafter. In this manner, by performing the verification for each memory cell, it is possible to suppress an increase in the width of the threshold value distribution of the multi-valued memory circuit due to variations in the characteristics of each memory cell.
[0007]
As described above, by finely performing the verification, the width of the threshold distribution can be reduced, and a larger multi-valued memory cell can be realized. FIG. 8 schematically shows a state of a threshold value distribution of a multi-valued memory circuit in which 16 thresholds (F0, F1,..., F15) are provided per memory cell by such verification. (Refer to Patent Document 1 as a similar method). F0 is a threshold value in the erased state. In order to finely write from the erase threshold F0 to the threshold shown on the right, usually, first, the threshold of F1 is set for a memory cell to be set to the threshold of F1 or higher, and then the threshold of F2 is set. A threshold value F2 is set for a memory cell where a threshold value or more is set, and a threshold value F3 is set for a memory cell where a threshold value or more is set. Is repeated, and finally the threshold value of F15 is written to the memory cell for which the threshold value of F15 is to be set.
[0008]
[Patent Document] Japanese Patent No. 2844393.
[0009]
[Problems to be solved by the invention]
FIG. 9 shows this by an algorithm. In FIG. 9, "program of F0" means erasing, "program of F1" means setting of a threshold value of F1 for executing verify, and "program of F2" means F2 for executing verify. Means setting of the threshold. As described above, there is a problem that the writing time increases when trying to realize multi-valued data.
[0010]
SUMMARY OF THE INVENTION An object of the present invention is to provide a threshold value writing method for a multi-valued memory that enables high-speed writing and shortens the writing time.
[0011]
[Means for Solving the Problems]
According to a first aspect of the present invention, in the threshold value writing method for a multi-valued memory circuit, the threshold value is set in accordance with a threshold value corresponding to the write data by a threshold distribution range of either an upper region or a lower region. , And in the next step, the threshold distribution range of either the narrower upper region or the lower region is set. Thereafter, the same steps are repeated to rapidly set the threshold value corresponding to the write data. A method for writing a threshold value of a multi-valued memory circuit is characterized in that.
[0012]
According to a second aspect of the present invention, there is provided a method of writing a threshold value of 2 n (n ≧ 2) into a memory cell of a multi-level memory circuit, wherein the threshold value is set within a minimum threshold distribution width. And a threshold value corresponding to the threshold value corresponding to the write data, and a threshold value that is larger by the minimum threshold distribution width than the maximum value of the threshold distribution including the threshold value set in the previous step. A threshold value is set with a target between a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by の of the minimum threshold value distribution width. Or a second step of setting a threshold in a range in which the threshold distribution width including the threshold set in the previous step is narrowed, and a second step of setting a threshold corresponding to the write data, The threshold set in the step The threshold value larger than the maximum value of the threshold distribution by half of the minimum threshold distribution width and the maximum value of the threshold distribution including the threshold value set in the previous step. A threshold value is set with a target between a threshold value which is larger by 1/2 2 of the minimum threshold value distribution width, or a threshold value distribution width including the threshold value set in the previous step. A third step of setting a threshold value in a range in which the threshold value is narrowed, and in accordance with a threshold value corresponding to the write data, a threshold distribution including the threshold value set in the previous step is included. The lower limit than the maximum value of the threshold distribution including the threshold value larger than the maximum value by 1/2 n-1 of the minimum threshold distribution width and the threshold value set in the previous step. Between the threshold value that is larger by 1 / 2n of the threshold distribution width. Setting a threshold value as a target, or setting the threshold value in a range in which a threshold distribution width including the threshold value set in the previous step is narrowed, and an (n + 1) th step. The threshold value writing method for the multi-valued memory circuit is described below.
[0013]
According to a third aspect of the present invention, in the threshold value writing method for a multi-valued memory circuit according to the first or second aspect, the verifying is performed so as to narrow the threshold distribution range by 1/2 each time the number of steps increases. And a threshold value writing method for a multilevel memory circuit.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present embodiment, when writing a 16-level threshold value to a memory cell of a multi-level memory circuit, the threshold value is set within the minimum threshold value distribution width in step A,
In step B, according to the threshold value corresponding to the write data, a threshold value larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by the minimum threshold value distribution width. A threshold value is set with a target between a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by の of the minimum threshold value distribution width. Or, set the threshold in a range where the threshold distribution width including the threshold set in the previous step is narrowed,
In step C, in accordance with the threshold value corresponding to the write data, the threshold value set in the previous step is equal to the minimum threshold value distribution width that is 1 / of the minimum threshold value distribution width larger than the maximum value of the threshold value distribution. Target between a large threshold value and a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by 1/4 of the minimum threshold value distribution width. Set a threshold value or set a threshold value in a range where the threshold distribution width including the threshold value set in the previous step is narrowed,
In step D, according to the threshold value corresponding to the write data, only 1 / of the minimum threshold distribution width smaller than the maximum value of the threshold distribution including the threshold value set in the previous step. Target between a large threshold value and a threshold value which is larger than the maximum value of the threshold distribution including the threshold value set in the previous step by 1/8 of the minimum threshold distribution width. Set a threshold value or set a threshold value in a range where the threshold distribution width including the threshold value set in the previous step is narrowed,
In step E, according to the threshold value corresponding to the write data, only 1/8 of the minimum threshold distribution width smaller than the maximum value of the threshold distribution including the threshold value set in the previous step. Target between a large threshold value and a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by 1/16 of the minimum threshold value distribution width. A threshold value is set, or a threshold value is set in a range in which the threshold distribution width including the threshold value set in the previous step is narrowed, and the threshold value corresponding to the write data is written as described above. The details will be described below.
[0015]
FIG. 1 is an explanatory diagram of an embodiment of a threshold value writing method for a multi-level memory circuit, which is an example in which 16-level threshold values included in any one range of threshold value distributions F0 to F15 are written. is there. A to E are threshold value writing steps, and the processing of each step is sequentially performed as shown in FIG.
[0016]
f0 to f14 indicate threshold distributions during processing. The difference between the thresholds of f1 and f2 is の of the maximum threshold F15, the pitch of each of the thresholds f3 to f6 is 1 / of the maximum threshold F15, and each of the thresholds of f7 to f14. The threshold pitch is 1/8 of the maximum threshold F15, and each threshold pitch of F0 to F15 is 1/16 of the maximum threshold F15.
[0017]
The width of the threshold distributions f1 and f2 is の of the threshold distribution f0, and the width of the threshold distributions f3 to f6 is の of the threshold distributions f1 and f2. The distribution width of f7 to f14 is 1/2 of the threshold distributions f3 to f6, and the distribution width of the threshold distributions F0 to F15 is half of the threshold distribution width of f7 to f14.
[0018]
The upper thresholds of the threshold distributions f0, f1, f3, f7 and F0 are common to each other, the upper thresholds of the threshold distributions f8 and F2 are also common to each other, and the upper thresholds of the threshold distributions f4, f9 and F4 are common. The upper thresholds are also common to each other, the upper thresholds of the threshold distributions f10 and F6 are also common to each other, the upper thresholds of the threshold distributions f2, f5, f11 and F8 are also common to each other, and the threshold distributions f12 and F12 are The upper threshold of F10 is also common to each other, the upper thresholds of threshold distributions f6, f13, and F12 are also common to each other, and the upper thresholds of threshold distributions f4 and F14 are also common to each other.
[0019]
Step A is executed by a program for setting a threshold value with a target of the lowest threshold distribution f0 range (erasing range). Step B is performed from the threshold distribution f0 range to the threshold distribution f1 or f2 range. This is executed by a program that sets a threshold value with a target of.
[0020]
In step C, a threshold is set with the target of the range of the threshold distribution f3 or f4 from the range of the threshold distribution f1, or the target of the range of the threshold distribution f5 or f6 is set from the range of the threshold distribution f2. This is executed by a program that sets a threshold value.
[0021]
In step D, a threshold is set with the target of the range of the threshold distribution f7 or f8 from the range of the threshold distribution f3, or the range of the threshold distribution f9 or f10 is set from the range of the threshold distribution f4. Is set, or a threshold is set with the target of the range of the threshold distribution f11 or f12 from the range of the threshold distribution f5, or the threshold distribution f13 is set from the range of the threshold distribution f6. Alternatively, it is executed by a program that sets a threshold value with the range of f14 as a target.
[0022]
Further, in step E, a threshold is set with the target of the range of the threshold distribution F0 or F1 from the range of the threshold distribution f7, or the range of the threshold distribution F2 or F3 is set from the range of the threshold distribution f8. Is set as a target, or a threshold is set from a range of the threshold distribution f9 to a range of the threshold distribution F4 or F5, or a threshold is set from a range of the threshold distribution f10. A threshold is set with the target of the range of the distribution F6 or F7, or a threshold is set with the target of the range of the threshold distribution F8 or F9 from the range of the threshold distribution f11, or the threshold distribution f12 is set. The threshold value is set with the target of the range of the threshold distribution F10 or F11 from the range of, or the range of the threshold distribution F12 or F13 is set from the range of the threshold distribution f13. It is performed by a program to set a threshold, or to set a threshold range of the threshold distributions F14 or F15 as the target from a range of threshold distribution f14 and.
[0023]
I indicates a transition process from step A to B, II, III, and IV indicate a transition process from B to C, C to D, and D to E, respectively. The tunnel charge amount of f0 to f2 in the transition process I Let Q be Q / 2, as shown in FIG. 3A, Q / 2 for f1 → f4, f2 → f6 in transition process II, and f3 → f8, f4 → f11, f5 → f13, f6 → f14 in transition process III. In the transition process IV, it is Q / 4, and in the transition process IV, it is Q / 8 in f7 → F1, f8 → F3, f9 → F5, f10 → F7, f11 → F9, f12 → F11, f13 → F13, and f14 → F15.
[0024]
Now, when setting the threshold value with the target of the range of the threshold value distribution F0, as shown in steps A → B → C → D → E, the value of F0 is verified by verification as f0 → f1 → f3 → f7 → F0. Write by narrowing the threshold to the range.
[0025]
When the threshold value is set with the target of the range of the threshold distribution F1, the steps A → B → C → D → E make the range of F1 by verification as f0 → f1 → f3 → f7 → F1. Writing is performed with the threshold value narrowed down. In this case, a charge amount of Q / 8 is injected in a transition IV from D to E.
[0026]
When the threshold value is set with the target of the range of the threshold distribution F2, the range is set to F2 by the verification such as f0 → f1 → f3 → f8 → F2 by steps A → B → C → D → E. Writing is performed with the threshold value narrowed down. In this case, a charge amount of Q / 4 is injected in transition III of C → D.
[0027]
When the threshold value is set with the target of the range of the threshold distribution F3, the range is set to F3 by the verification such as f0 → f1 → f3 → f8 → F3 by steps A → B → C → D → E. Writing is performed with the threshold value narrowed down. In this case, a charge amount of Q / 4 is injected in transition III of C → D, and a charge amount of Q / 8 is injected in transition IV of D → E.
[0028]
Similarly, when the threshold value is set targeting the range of the threshold distributions F4 to F14, and finally the threshold value is set targeting the range of the threshold distribution F15, steps A → B → C From D → E, the threshold is narrowed down to the range of F15 by verification, such as f0 → f2 → f6 → f14 → F15. In this case, the charge amount of Q is injected at the transition I of A → B. , A charge amount of Q / 2 is injected at transition II of B → C, a charge amount of Q / 4 is injected at transition III of C → D, and a charge amount of Q / 8 is injected at transition IV of D → E. I do.
[0029]
FIG. 3B is an enlarged view of a portion surrounded by a square broken line in FIG. Assuming that the charge amount at transition f7 → F1 of transition IV is 3Qa, the charge amount at transition F0 → F1 is 2Qa. According to this ratio, as described above, the charge amount of transition IV is Q / 8, and the charge amount in F0 → F1 is Q / 12. For comparison, the electric charge amount at one transition V in the conventional writing is also shown on the rightmost side of FIG. As described above, in the present embodiment, the charge amount at the minimum transition IV is also larger than the charge amount at the transition V of one step in the conventional writing described with reference to FIG.
[0030]
FIG. 4 is a diagram illustrating a comparison between the case according to the present invention and the case using the conventional method when setting a threshold value with the target of the range of the threshold value distribution F15. The conventional method sets the threshold value of the threshold distribution F1 in 8 steps starting from the erased state, and sets the threshold value in the range of the threshold distribution F15 in 14 steps, that is, 22 steps in total. On the other hand, in the present invention, setting of the threshold value in the range of the threshold value distribution F15 is completed by four steps (f2 → f16 → f14 → F15 in FIG. 1) starting from the erased state. Therefore, as shown in FIG. 5, which shows a comparison between the conventional method and the present invention with respect to the write time, the present invention can greatly reduce the write time to 4/22 compared to the conventional method.
[0031]
【The invention's effect】
As described above, according to the writing method of the present invention, the number of steps required for writing can be significantly reduced, and there is an advantage that high-speed writing can be performed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of threshold writing according to one embodiment of the present invention.
FIG. 2 is an explanatory diagram of processing of steps A to E in FIG. 1;
3A is a characteristic diagram of a tunnel charge amount in each transition, and FIG. 3B is an enlarged view of a portion indicated by a dotted line in FIG.
FIG. 4 is an explanatory diagram of a comparison between a conventional method and a case according to the present invention when a threshold value is written targeting a range of a threshold distribution F15.
FIG. 5 is an explanatory diagram of a comparison between a conventional method and a write time according to the present invention.
6A is an explanatory diagram of a threshold distribution of a memory cell having a binary threshold, FIG. 6B is an explanatory diagram of a threshold distribution of a memory cell having a quaternary threshold, FIG. 4C is an explanatory diagram of a threshold distribution of a memory cell having an eight-level threshold.
7A is an explanatory diagram of a threshold distribution when a threshold is written without performing verification, and FIG. 7B is an explanatory diagram of a threshold distribution when a threshold is written without performing verification. It is.
FIG. 8 is an explanatory diagram of conventional threshold value writing.
FIG. 9 is an explanatory diagram of a threshold value writing process of FIG. 8;
[Explanation of symbols]
A to E: threshold writing steps I to V: threshold transition f0 to f14, F0 to F15: threshold distribution

Claims (3)

  1. In a method of writing a threshold value of a multilevel memory circuit,
    According to the threshold value corresponding to the write data, the threshold value is set to the threshold distribution range of either the upper region or the lower region, and in the next step, the narrower upper region or the lower region is selected. A threshold value writing method for a multi-valued memory circuit, wherein a threshold value distribution range is set, and the same steps are repeated thereafter to rapidly set a threshold value corresponding to the write data.
  2. In a method of writing a 2 n (n ≧ 2) value threshold value to a memory cell of a multi-valued memory circuit,
    A first step of setting a threshold within the minimum threshold distribution width;
    According to the threshold value corresponding to the write data, the threshold value larger than the maximum value of the threshold distribution including the threshold value set in the previous step by the minimum threshold distribution width and the previous step Setting the threshold value between a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set by だ け of the minimum threshold value distribution width, or A second step of setting a threshold in a range in which the threshold distribution width including the threshold set in the previous step is narrowed;
    According to a threshold value corresponding to the write data, a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by の of the minimum threshold value distribution width. A threshold value between a threshold value and a threshold value which is larger than the maximum value of the threshold distribution including the threshold value set in the previous step by 1/2 2 of the minimum threshold distribution width. Or a third step of setting a threshold value in a range in which the threshold distribution width including the threshold value set in the previous step is narrowed:
    :
    In accordance with the threshold value corresponding to the write data, only 1/2 n-1 of the minimum threshold distribution width smaller than the maximum value of the threshold distribution including the threshold value set in the previous step. Target between a large threshold value and a threshold value which is larger than the maximum value of the threshold value distribution including the threshold value set in the previous step by 1/2 n of the minimum threshold value distribution width. An (n + 1) th step of setting a threshold or setting a threshold in a range in which the threshold distribution width including the threshold set in the previous step is included;
    A threshold value writing method for a multilevel memory circuit, comprising:
  3. 3. The method for writing a threshold value of a multi-valued memory circuit according to claim 1 or 2,
    A threshold writing method for a multi-valued memory circuit, wherein verification is performed so as to narrow the threshold distribution range by 1/2 each time the number of steps increases.
JP2003127705A 2003-05-06 2003-05-06 Threshold level write-in method of multi-level memory circuit Pending JP2004334956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003127705A JP2004334956A (en) 2003-05-06 2003-05-06 Threshold level write-in method of multi-level memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003127705A JP2004334956A (en) 2003-05-06 2003-05-06 Threshold level write-in method of multi-level memory circuit

Publications (1)

Publication Number Publication Date
JP2004334956A true JP2004334956A (en) 2004-11-25

Family

ID=33504109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003127705A Pending JP2004334956A (en) 2003-05-06 2003-05-06 Threshold level write-in method of multi-level memory circuit

Country Status (1)

Country Link
JP (1) JP2004334956A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006139864A (en) * 2004-11-12 2006-06-01 Toshiba Corp Semiconductor memory
US7782666B2 (en) 2007-10-25 2010-08-24 Samsung Electronics Co., Ltd. Apparatus and method of multi-bit programming

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006139864A (en) * 2004-11-12 2006-06-01 Toshiba Corp Semiconductor memory
US7813171B2 (en) 2004-11-12 2010-10-12 Kabushiki Kaisha Toshiba Semiconductor memory device
JP4713873B2 (en) * 2004-11-12 2011-06-29 株式会社東芝 Semiconductor memory device
US7782666B2 (en) 2007-10-25 2010-08-24 Samsung Electronics Co., Ltd. Apparatus and method of multi-bit programming

Similar Documents

Publication Publication Date Title
US9508442B2 (en) Non-volatile semiconductor storage device
US8958249B2 (en) Partitioned erase and erase verification in non-volatile memory
KR101854927B1 (en) Multibit programming method in a non-volatile memory allowing a number of data state - fails and data recovery method in case of programming fail
EP2954529B1 (en) Programming select gate transistors and memory cells using dynamic verify level
US9208887B2 (en) Nonvolatile semiconductor memory device
US20130223154A1 (en) Sequential programming of sets of non-volatile elements to improve boost voltage clamping
KR101697271B1 (en) Programming non-volatile memory with reduced number of verify operations
US7486564B2 (en) Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells
US7352628B2 (en) Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in a non-volatile memory
US7675782B2 (en) Method, system and circuit for programming a non-volatile memory array
JP4653738B2 (en) Method of operating flash memory cell and flash memory device
CN102138182B (en) Programming and selectively erasing non-volatile storage
US8611148B2 (en) Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory
KR101017321B1 (en) Smart verify for multi-state memories
US7447068B2 (en) Method for programming a multilevel memory
JP4477352B2 (en) Method and system for performing programming and inhibition of multi-level non-volatile memory cells
KR100865830B1 (en) Method of reading a memory device
US7042766B1 (en) Method of programming a flash memory device using multilevel charge storage
US8274838B2 (en) Programming non-volatile memory with bit line voltage step up
US8730736B2 (en) NAND step up voltage switching method
KR100885914B1 (en) Non-volatile Memory Device having improved read operation and Driving Method for the same
KR100851853B1 (en) Flash memory device and program and verify method thereof
JP4640660B2 (en) A method for programming a flash memory with a voltage level optimized according to the number of bits detected to have failed programming.
KR100953045B1 (en) Programming method of non volatile memory device
US6330192B1 (en) Nonvolatile semiconductor memory device and method of erasing data of nonvolatile semiconductor memory device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050803

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071127

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080415