JP2004312275A - Time code conversion device and video conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a time code conversion device in which responsiveness of conversion of a time code is improved, and provide a video conversion device provided with the time code conversion device. <P>SOLUTION: A pattern detector 9 detects a phase difference pattern between time information added to a first video signal (30FPS signal) and time information serving as a reference at the time of converting a second video signal (24FPS signal). The time converter 7 reads a conversion table corresponding to the detected phase difference pattern from a storage unit 10, and converts a first time code (TC<SB>30</SB>) and a second time code (TC<SB>24</SB>) based on the conversion table which is read from the storage unit 10. Thus, a point can be set where the first time code and the second time code are synchronized at an interval shorter than timing when synchronization of a synchronizing signal of the first video signal and a synchronizing signal of the second video signal is matched. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
According to the present invention, when converting a first video signal having a first frame rate into a second video signal having a second frame rate different from the first frame rate, the first video signal The present invention relates to a time code conversion device for converting a first time code corresponding to the above to a second time code corresponding to the second video signal, and a video conversion device provided with this time code conversion device.
[0002]
[Prior art]
Conventionally, when converting a video signal in a 30 frame / second format (hereinafter referred to as a 30 FPS signal) into a video signal in a 24 frame / second format (hereinafter referred to as a 24 FPS signal), 30 counts / second added to the 30 FPS signal Time code (hereinafter TC₃₀) Is converted to a 24 count / second time code (hereinafter, TC₂₄Various time code conversion devices have been considered. (For example, see Patent Document 1)
[0003]
[Patent Document 1]
JP-A-5-91467
[0004]
[Problems to be solved by the invention]
However, in a conventional time code conversion apparatus, unless the timing of synchronization is the same between the 30 Hz synchronization signal as the synchronization signal of the 30 FPS signal before conversion and the 24 Hz synchronization signal as the synchronization signal at the time of 24 FPS signal conversion, TC₂₄To TC₃₀Can not set a point to synchronize with₃₀→ TC₂₄However, there is a problem that the response of the time code conversion is not good. Specifically, the timing at which the synchronization coincides between the 30 Hz synchronization signal and the 24 Hz synchronization signal is a 6 Hz cycle. Therefore, TC₃₀→ TC₂₄At the time of the time code conversion, the synchronization point could be set only at a period of 6 Hz, and the synchronization point could not be set at shorter intervals.
[0005]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention converts a first video signal having a first frame rate into a second video signal having a second frame rate different from the first frame rate. In doing so, a time code conversion device that converts a first time code corresponding to the first video signal into a second time code corresponding to the second video signal is configured as follows.
[0006]
The present invention provides a pattern detector for detecting a phase difference pattern between time information added to the first video signal and time information serving as a reference at the time of conversion to the second video signal.
A storage unit that sets and stores a conversion table for converting the first time code into the second time code for each of the phase difference patterns;
A time code converter that reads a conversion table corresponding to the phase difference pattern detected by the pattern detector from the storage device, and converts the first time code into the second time code based on the read conversion table; When,
Having.
[0007]
Since the time information added to the first video signal and the time information serving as a reference when converting the second video signal have different phases from each other, there are a plurality of phase difference patterns. The present invention includes a conversion table for converting a first time code into a second time code for each of these phase difference patterns. Therefore, the present invention provides the first time code and the first time code at an interval shorter than the timing when the synchronization between the synchronization signal of the first video signal before conversion and the synchronization signal of the second video signal after conversion coincides with each other. It is possible to set a point for synchronizing with the second time code. This improves the responsiveness when converting the first time code to the second time code.
[0008]
The following is a specific configuration of the pattern detector. That is, after setting the greatest common divisor frequency between the first synchronization signal added to the first video signal and the second synchronization signal used at the time of conversion of the second video signal, the set greatest common divisor is set. The first and second synchronization signals are frequency-divided so as to have several frequencies to generate a first synchronization frequency-divided signal and a second synchronization frequency-divided signal, respectively. A configuration for detecting a phase difference pattern between two synchronous frequency-divided signals is given as an example.
[0009]
The first video signal is, for example, a video signal of a 30 frame / second format. An example of the second video signal is a video signal in a 24 frame / second format.
[0010]
When the first and second video signals are set as described above, it is preferable to further configure as follows. That is, the pattern detector is configured to output a first 6-Hz synchronous frequency-divided signal corresponding to the 5-frequency-divided signal of the 30-Hz synchronous signal added to the first video signal, and a 24-Hz synchronous signal used in the conversion of the 24 FPS signal. It is preferable to generate a second 6 Hz synchronous frequency-divided signal corresponding to the frequency-divided signal, and then detect a phase difference pattern between the generated first and second 6 Hz synchronous frequency-divided signals. .
[0011]
With this configuration, it is possible to set a synchronization point according to the phase difference pattern between the first and second 6 Hz synchronization frequency-divided signals.
[0012]
Further, the pattern detector generates numerical data which repeats count-up at a 6 Hz cycle as the first and second 6 Hz synchronous frequency-divided signals, and compares the generated numerical data with each other for an enhancement pattern. Preferably, the phase difference pattern is detected. Then, the phase difference pattern can be detected by digital processing, and accordingly, the present invention has a configuration suitable for processing a digital video signal.
[0013]
Further, the pattern detector generates a first 6-Hz synchronization frequency-divided signal converted into the numerical data from a remainder obtained by dividing the first time code by an integer 5, and divides the 24-Hz synchronization signal by four. It is preferable that the second 6-Hz synchronous frequency-divided signal converted into the numerical data is generated by repeating count-up based on the 30-Hz synchronous signal at the cycle of the generated second 6-Hz synchronous frequency-divided signal. . This makes it possible to relatively easily form the digitized first and second 6 Hz synchronous frequency-divided signals.
[0014]
Further, a speed detector for detecting a reproduction speed of the first video signal when converting the first video signal into the second video signal;
A state detector for detecting a video progress state of the first video signal when the first video signal is reproduced;
Is further provided,
The storage device further sets and stores the conversion table corresponding to a video lapse state at the time of slow-speed reproduction of the first video signal,
The time code converter stores the conversion table according to the video state detected by the state detector when the speed detector determines that the reproduction speed of the first video signal is slow reproduction. And converting the first time code into the second time code based on the read conversion table;
When judging that the reproduction speed is other than the low-speed reproduction, the conversion table set for each of the phase difference patterns is read from the storage device, and the first time code is converted to the second time code based on the read conversion table. It is preferable to convert the time code.
[0015]
In practicing the present invention, when the first video signal is reproduced at a very low speed, the above-described phase difference pattern does not hold. In such a case, as described above, a conversion table corresponding to the video state may be set, and at the time of low-speed playback, time code conversion may be performed based on the conversion table corresponding to the video state. By doing so, according to the present invention, time code conversion can be performed with high accuracy even during low-speed reproduction.
[0016]
When the first video signal is an interlaced video signal, a field position of the first video signal can be given as an example of the video state.
[0017]
The slow reproduction speed of the first video signal at which the above-mentioned phase difference pattern does not hold can be less than 0.5 times speed.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a block diagram illustrating a configuration of a video conversion device in which a time code conversion device according to an embodiment of the present invention is incorporated. The video converter 1 converts a first video signal (hereinafter, referred to as a 30 FPS signal) having a frame rate of 30 frames / sec into a frame rate of 24 frames / sec, which is a frame rate different from the 30 FPS signal. To a second video signal (hereinafter, referred to as a 24 FPS signal) and a 30 count / second first time code (hereinafter, referred to as TC) added to the 30 FPS signal.₃₀) Is converted to a second time code of 24 counts / second corresponding to a 24 FPS video signal (hereinafter referred to as TC₂₄Device).
[0019]
The video converter 1 includes a 30 Hz sync signal generator 2, a 24 Hz sync signal generator 3, a tape running device 4, a reproducing device 5, a sampling device 6, a time code converter 7, a video converter 8, , A pattern detector 9, a storage device 10, a field detector 11, and a speed detector 12.
[0020]
The 24 Hz synchronization signal generator 3 performs video conversion (30 FPS signal → 24 FPS signal) and time code conversion (TCC).₃₀→ TC₂₄) Is generated and supplied to the sampler 6, the pattern detector 9 and the 30Hz synchronization signal generator 2. The 30 Hz synchronization signal generator 2 generates a 30 Hz synchronization signal, which is a reference synchronization signal for reproducing a 30 FPS signal, based on the 24 Hz synchronization signal supplied from the 24 Hz synchronization signal generator 3, and forms a pattern with the tape drive 4. To the detector 9. Specifically, a 30 Hz synchronization signal is generated by subjecting the 24 Hz synchronization signal to a 30/24 multiplication process. The reproducer 5 reproduces a digital video signal (including time code information) from the digital video tape V on which the 30 FPS signal is recorded. When the reproducing device 5 reproduces the digital video tape V, the tape traveling device 4 causes the digital video tape V to travel relatively to the reproducing head H of the reproducing device 5. The sampler 6 has a TC included in the 30 FPS signal reproduced by the reproducer 5.₃₀Is read out at the timing synchronized with the 24 Hz synchronization signal, thereby reading TC₃₀Generate The storage device 10 has a read TC₃₀To TC₂₄The conversion table to be converted is recorded. The storage 10 records a plurality of conversion tables. The plurality of conversion tables are set for each phase difference pattern between the synchronization timing (time information) of the 30 FPS signal and the synchronization timing (time information) serving as a reference when converting the 24 FPS signal. The pattern detector 9 detects a phase difference pattern between the synchronization timing (time information) of the 30 FPS signal and the synchronization timing (time information) serving as a reference when converting the 24 FPS signal. The time code converter 7 includes a converter main body 7A and a selector 7B. The selector 7B reads from the storage 10 a conversion table corresponding to the detection results of the pattern detector 9 and the speed detector 12. The converter body 7A reads TC based on the conversion table selected by the selector 7B.₃₀To TC₂₄Convert to The video converter 8 converts a 30 FPS signal included in the digital video signal reproduced by the reproducer 5 into a 24 FPS signal. The field detector 11 detects a field position, which is video progress state information of a 30 FPS signal (digital video signal) being reproduced by the reproducer 5, and supplies the field position information to the converter body 7A. The speed detector 12 detects the speed information of the digital video tape V that is playing and running from the tape running unit 4 and supplies it to the selector 7B. In the present embodiment, a state detector configured to detect an image progress state from the field detector 11 is configured.
[0021]
In the video conversion device 1, a time code conversion device is configured from a configuration other than the video converter 8.
[0022]
Hereinafter, the details of the time code conversion operation by the video conversion device 1 will be described with reference to FIGS.
[0023]
The time corresponding to 5 frames of the 30 FPS signal (5/30 seconds = 1/6 second) and the time of 4 frames of the 24 FPS signal (4/24 seconds = 1/6 second) are the same. Therefore, the 30 FPS signal and the 24 FPS signal are synchronized at a 1/6 second cycle. TC, which is implemented simultaneously when converting a 30 FPS signal into a 24 FPS signal₃₀→ TC₂₄In the time code conversion operation of₃₀To TC₂₄There is a 1/6 second cycle in the operation of converting to.
[0024]
Specifically, TC₃₀1/6 second time code (30_A), (30_B), (30_C), (30_D), (30_E) Is TC₂₄Time code for 1/6 second (24_a), (24_b), (24_c), (24_d). Where TC₃₀Indicates a time code number 5x, B indicates 5x + 1, C indicates 5x + 2, D indicates 5x + 3, and E indicates 5x + 4. On the other hand, TC₂₄Indicates a time code number 4x, b indicates 4x + 1, C indicates 4x + 2, and d indicates 4x + 3. Here, x represents an integer of 0 to 5.
[0025]
In such a time code conversion, TC is counted up five times at 1/6 second intervals.₃₀(30_{A ~ E}TC) that counts up four times at 1/6 second intervals by thinning out one time code from₂₄(24_{a ~ d}) Is generated.
[0026]
Such a time code conversion operation is specifically performed as shown in FIGS. First, a reproduction TC synchronized with a synchronization signal (30 Hz synchronization signal) of a 30 FPS signal.₃₀Is read out at an arbitrary timing cycle (for example, falling timing) of the synchronization signal (24 Hz synchronization signal) of the 24FPS signal. TC to be read₃₀Is discontinuous data in which time code data is thinned out at a predetermined cycle. At the time of time code conversion, the video conversion device 1 performs the discontinuous read TC₃₀To the continuous TC₂₄Is stored in the storage device 10. Details of the conversion table are shown in FIG. The time code converter 7 reads the discontinuous TC₃₀Is read from the storage device 10 and read out based on the conversion table.₃₀To TC₂₄Convert to Converted TC₂₄Is output at an arbitrary timing cycle (for example, a rising cycle) of the synchronization signal (24 Hz synchronization signal) of the 24FPS signal.
[0027]
TC₃₀There is periodicity in the time code thinning-out process performed when reading the data, and the following five thinning-out patterns exist depending on the periodicity.
-Pattern 1: Time code 30_DIs a pattern that is thinned out.
-Pattern 2: Time code 30_EIs a pattern that is thinned out.
-Pattern 3: Time code 30_AIs a pattern that is thinned out.
-Pattern 4: Time code 30_BIs a pattern that is thinned out.
-Pattern 5: Time code 30_CIs a pattern that is thinned out.
[0028]
FIGS. 3 to 7 show the conversion operation for each of these patterns 1 to 5. 3 to 7, TC₂₄Time code 24_{a ~ d}Is the output TC₂₄Shown as phase. TC₃₀Time code 30_{A ~ E}Is the playback TC₃₀Shown as phase. Note that the timing indicated as a synchronization point in each drawing indicates the timing at which the synchronization between the images is synchronized when the 30 FPS signal is converted to the 24 FPS signal.
[0029]
Play TC₃₀Phase and output TC₂₄The following can be understood from the phase difference pattern from the phase in detail.
・ Reproduction TC₃₀Phase is output TC₂₄In the case of a phase difference pattern that temporally precedes the phase by 1/30 second, the above-described pattern 1 is used.
・ Reproduction TC₃₀Phase is output TC₂₄In the case of a phase difference pattern that temporally precedes the phase by 2/30 seconds, the above-described pattern 2 is used.
・ Reproduction TC₃₀Phase is output TC₂₄In the case of a phase difference pattern that temporally precedes the phase by 3/30 seconds, the above-described pattern 3 is used.
・ Reproduction TC₃₀Phase is output TC₂₄In the case of a phase difference pattern that temporally precedes the phase by 4/30 seconds, the above-described pattern 4 is used.
・ Reproduction TC₃₀Phase is output TC₂₄In the case of a phase difference pattern that coincides with the phase, the above-described pattern 5 is used.
[0030]
Thus, the playback TC₃₀Phase and output TC₂₄If a phase difference pattern between phases is detected, TC₃₀, A thinning pattern in a time code thinning process performed at the time of reading can be recognized. In the video conversion apparatus 1, as shown in FIG. 2, a conversion table is set for each thinning pattern and stored in the storage device 10. Specifically, in the conversion table corresponding to pattern 1, the time code 30_DAssuming that (D = 5x + 3) has been thinned out, the read discontinuous TC₃₀Continuous TC₂₄The conversion table is configured to be converted into.
[0031]
In the conversion table corresponding to pattern 2, the time code 30_EAssuming that (D = 5x + 4) has been thinned out, the read discontinuous TC₃₀Continuous TC₂₄The conversion table is configured to be converted into.
[0032]
In the conversion table corresponding to pattern 3, the time code 30_AAssuming that (D = 5x) has been thinned out, the read discontinuous TC₃₀Continuous TC₂₄The conversion table is configured to be converted into.
[0033]
In the conversion table corresponding to pattern 4, the time code 30_BAssuming that (D = 5x + 1) has been thinned out, the read discontinuous TC₃₀Continuous TC₂₄The conversion table is configured to be converted into.
[0034]
In the conversion table corresponding to pattern 5, the time code 30_CAssuming that (D = 5x + 2) has been thinned out, the read discontinuous TC₃₀Continuous TC₂₄The conversion table is configured to be converted into.
[0035]
When recognizing the thinning pattern, the video conversion device 1 reads a conversion table corresponding to the recognized thinning pattern from the storage device 10, and based on the read conversion table, the read TC that has become discontinuous due to the thinning.₃₀Continuous TC₂₄Convert to Thus, even if the synchronization points are set at 1/30 second intervals, the video conversion device 1 reads the conversion table corresponding to the set synchronization points from the storage device 10 and reads the conversion table from the TC.₃₀Exactly TC₂₄Can be converted to
[0036]
The video converter 1 (specifically, the pattern detector 9) performs the reproduction TC as follows.₃₀Phase and output TC₂₄A phase difference pattern between phases is detected.
[0037]
First, the greatest common divisor frequency between the 24 Hz synchronization signal and the 30 Hz synchronization signal is set. In this case, the greatest common divisor frequency is 6 Hz. After setting the greatest common divisor frequency, play TC₃₀Is detected as follows. First, play TC₃₀The remainder obtained by dividing the time code value of by 5 is calculated. Hereinafter, the calculated reproduction TC₃₀The remaining data is the playback TC₃₀It is called a count value. Play TC₃₀The count value has a data configuration of a 6 Hz cycle (the greatest common divisor frequency cycle) in which values 0, 1, 2, 3, and 4 are repeated at 1/30 second intervals. Play TC₃₀The count value is the reproduction TC₃₀This is data obtained by digitizing the phase. In the present embodiment, the reproduction TC₃₀The time information added to the 30 FPS signal from the count value, the first synchronous frequency-divided signal having the greatest common divisor frequency cycle, and the first 6 Hz synchronous frequency-divided signal are configured.
[0038]
On the other hand, a 6 Hz synchronous frequency-divided signal is generated by dividing the frequency of the 24 Hz synchronous signal used for 24 FPS signal conversion by four. Then, the (0, 1) data of the 6-Hz synchronization frequency-divided signal is read out at a predetermined timing (for example, a rising timing) of the 30-Hz synchronization signal. The read data has a data configuration of a 6-Hz cycle (the greatest common frequency cycle) in which values of 1,1,1,0,0 are repeated at intervals of 30 Hz. Next, in the read data, the value is cleared to 0 at a timing when the value changes from 0 to 1, and thereafter, the data is counted up and output every 1/30 second specified by the 30 Hz synchronization signal. Hereinafter, the count value thus calculated is referred to as an internal 6 Hz count value. The internal 6 Hz count value has a data configuration of a 6 Hz cycle (the greatest common divisor frequency cycle) in which values of 0, 1, 2, 3, and 4 are repeated at intervals of 30 Hz. Internal 6 Hz count value is output TC₂₄This is data obtained by digitizing the phase. In the present embodiment, time information serving as a reference at the time of 24 FPS signal conversion from an internal 6 Hz count value, a second synchronous frequency-divided signal having the greatest common divisor frequency cycle, and a second 6 Hz synchronous frequency-divided signal are configured. .
[0039]
Next, play TC₃₀A phase difference pattern between the count value, the data configuration, and the numerical data of the internal 6 Hz count value is detected. For the internal 6 Hz count value (0, 1, 2, 3, 4), the reproduction TC₃₀When the count values (1, 2, 3, 4, 0) correspond, it is determined to be the above-described pattern 1. For the internal 6 Hz count value (0, 1, 2, 3, 4), the reproduction TC₃₀When the count values (2, 3, 4, 0, 1) correspond, it is determined that the above-described pattern 2 is used. For the internal 6 Hz count value (0, 1, 2, 3, 4), the reproduction TC₃₀When the count values (3, 4, 0, 1, 2) correspond, it is determined to be the above-described pattern 3. For the internal 6 Hz count value (0, 1, 2, 3, 4), the reproduction TC₃₀When the count values (4, 0, 1, 2, 3) correspond, it is determined that the above-mentioned pattern 4 is set. For the internal 6 Hz count value (0, 1, 2, 3, 4), the reproduction TC₃₀If the count values (0, 1, 2, 3, 4) correspond, it is determined that the above-described pattern 5 is used.
[0040]
Then, a conversion table corresponding to the determined pattern is read from the storage device 10, and the read TC is read based on the read conversion table.₃₀To TC₂₄Convert to
[0041]
The outline of the time code conversion operation in the video conversion device 1 has been described above. Next, details of the time code conversion operation of the video conversion device 1 will be described with reference to FIGS.
[0042]
First, a synchronization point is set. The synchronization point is time point information on the video signal indicating which frame position on the 30 FPS signal is synchronized with a predetermined frame position on the 24 FPS signal. A 30 Hz synchronization signal used as a synchronization signal when reproducing a 30 FPS signal and a 24 Hz synchronization signal used as a synchronization signal when converting a 30 FPS signal into a 24 FPS signal have a signal form synchronized with a synchronization point. In the video conversion device 1, the synchronization points are set at 1/30 second intervals. Even if the synchronization points are set at such minute time intervals, the video conversion device 1 can perform time code conversion with high accuracy.
[0043]
When the synchronization point is set, the digital video tape V is run by the tape running device 4 so that the relative position of the digital video tape V with respect to the reproducing head H matches the synchronization point. At this time, the digital video tape V is preliminarily reproduced by the reproducer 5. The reproduction is performed in a state synchronized with the 30 Hz synchronization signal generated by the 30 Hz synchronization signal generator 2. The reproduced digital video signal is supplied to a sampler 6, a video converter 8, a pattern detector 9, and a field detector 11. The sampler 6 converts the digital video signal into TC₃₀And supply it to the converter body 7A.
[0044]
The pattern detector 9 has TC₃₀In addition, a 30 Hz synchronization signal and a 24 Hz synchronization signal are supplied from the 30 Hz synchronization signal generator 2 and the 24 Hz synchronization signal generator 3, respectively.
[0045]
The pattern detector 9 divides the frequency of the 24 Hz synchronization signal supplied from the 24 Hz synchronization signal generator 3 by 4 to generate a 6 Hz synchronization frequency divided signal. Further, the pattern detector 9 reads the (0, 1) data of the 6 Hz synchronous frequency-divided signal at the rising timing of the 30 Hz synchronous signal. The read data has a data configuration in which values of 1,1,1,0,0 are repeated at intervals of 30 Hz with a cycle of 6 Hz. Next, the pattern detector 9 clears the read data to 0 at the timing when the value changes from 0 to 1, and thereafter counts up every 1/30 second specified by the 30 Hz synchronization signal. Generates an internal 6 Hz count value.
[0046]
Further, the pattern detector 9 detects the TC supplied from the sampler 6₃₀TC consisting of the remainder of dividing the value of₃₀Generate a count value.
[0047]
Next, the pattern detector 9 sets the reproduction TC₃₀A phase difference pattern between the numerical data of the count value and the numerical data of the internal 6 Hz count value is detected. Details of the pattern to be detected are as follows.
・ Reproduction TC for internal 6Hz count value (0, 1, 2, 3, 4)₃₀When the count value (1, 2, 3, 4, 0) corresponds to the phase difference pattern shown in FIG.
・ Reproduction TC for internal 6Hz count value (0, 1, 2, 3, 4)₃₀If the count value (2, 3, 4, 0, 1) corresponds to the phase difference pattern shown in FIG.
・ Reproduction TC for internal 6Hz count value (0, 1, 2, 3, 4)₃₀When the count value (3, 4, 0, 1, 2) corresponds to the phase difference pattern shown in FIG.
・ Reproduction TC for internal 6Hz count value (0, 1, 2, 3, 4)₃₀If the count value (4, 0, 1, 2, 3) corresponds to the phase difference pattern shown in FIG.
・ Reproduction TC for internal 6Hz count value (0, 1, 2, 3, 4)₃₀If the count value (0, 1, 2, 3, 4) corresponds to the phase difference pattern shown in FIG.
[0048]
The pattern detector 9 notifies the selector 7B of the determined phase difference pattern. The selector 7B reads the conversion table (see FIG. 2) corresponding to the phase difference pattern notified from the pattern detector 9 from the storage device 10 and supplies the conversion table to the converter main body 7A.
[0049]
The converter body 7A reads TC based on the conversion table supplied from the selector 7B.₃₀To TC₂₄Output after converting to. The time code conversion process for each pattern is shown in FIGS.
[0050]
On the other hand, the video converter 8 converts the digital video signal supplied from the reproducer 5 into a 24 FPS signal and outputs it. The video conversion is performed at a timing synchronized with the 24 Hz synchronization signal supplied from the 24 Hz synchronization signal generator 3. The converted 24FPS signal is a TC output from the converter main body 7A.₂₄Is output in a signal form synchronized at the synchronization point.
[0051]
As described above, in the video converter 1, the playback TC₃₀No matter which timing of the 1/30 second interval, the phase of the internal 6 Hz count value (24 Hz synchronization signal) is set, the TC is determined based on the conversion table according to the phase difference pattern.₃₀To TC₂₄Can be converted to Therefore, the video conversion device 1 can set the synchronization point at an interval shorter than the 6 Hz cycle, specifically, at a 30 Hz cycle, and accordingly, the responsiveness of the time code conversion is improved.
[0052]
The time code conversion process in the video conversion device 1 described above is based on the premise that a 30 FPS signal is reproduced at a constant speed. However, when converting the time code, it is necessary to accurately match the synchronization points. Therefore, immediately before the synchronization points coincide, the 30 FPS signal is reproduced while the reproduction speed is gradually reduced or is not gradually increased. In the video conversion device 1, highly accurate time code conversion can be performed by the time code conversion process described above. However, when the reproduction speed becomes a low-speed reproduction of less than 0.5 times speed, in the above-described time code conversion step, the reproduction TC output from the reproducer 5 is output.₃₀Creates a discontinuity in itself. Specifically, at the time of low-speed reproduction, the reproduction TC₃₀, The same time code is read out at the adjacent timing. In particular, at the time of low-speed reproduction at less than 0.5 times speed, the same time code is read at three adjacent timings. Reproduced TC having such discontinuity₃₀Is calculated according to the method described above.₂₄Continuous TC even if converted to₂₄Does not.
[0053]
Therefore, in the video conversion device 1, at the time of low-speed reproduction at less than 0.5 times speed, the TC₃₀Exactly TC₂₄Convert to The following conversion method is based on the following video conversion.
[0054]
A case where a 30-frame / second interlaced video signal (hereinafter referred to as a 60i video signal) is generated by performing a primary conversion on a 24 frame / second progressive video signal (hereinafter referred to as a 24p video signal). Suppose. In this case, field data constituting the original video signal (24p video signal) is overlapped as field data constituting the video signal (60i video signal) after the primary conversion. Specifically, a data area in which frame data for one frame of the original video signal (24p video signal) is overlapped and arranged as field data for three fields of the video signal (60i video signal) after the primary conversion, A data area set is repeatedly arranged with a data area in which frame data for one frame is overlapped and arranged as field data for two fields, and by performing such a data arrangement, the primary conversion is performed. Will be implemented. Hereinafter, such a conversion process is referred to as a 2-3 pull-down conversion process.
[0055]
The premise is that the video signal (60i video signal) on which the 2-3 pull-down conversion process (primary conversion) has been performed is secondarily converted into an original video signal (24p video signal).
[0056]
When the digital video tape V is reproduced at a low speed of less than 0.5 times speed by the reproducing device 5, the read TC₃₀In the case of, a time code area in which the time code value is read in three or more consecutive times occurs as the reproduction speed decreases. In this case, a conversion table based on the above-described phase difference patterns of patterns 1 to 5 cannot be used. However, if the field position of the 60i video signal being reproduced can be detected, it is possible to add a time code corresponding to the field position. This is because, in the regular conversion process of the video format from the 24p video signal to the 60i video signal, taking the above-described 2-3 pull-down conversion process as an example, the field position in the 60i video signal after the conversion and the 24p video before the conversion are used. It is based on the fact that the time code of the signal corresponds exactly one to one.
[0057]
Therefore, in the video conversion apparatus 1, the storage table further stores a conversion table at the time of low-speed reproduction. FIG. 13 shows an example of a conversion table at the time of slow speed reproduction (less than 0.5 times speed) corresponding to the 2-3 pull-down conversion process.
[0058]
In the video converter 1, the tape playback speed information from the tape traveling device 4 is supplied to the speed detector 12. When the speed detector 12 confirms that the tape playback speed is less than 0.5 times the slow playback speed, the speed detector 12 notifies the selector 7B of the fact. The selector 7B that has received the notification of the slow-speed reproduction calls the conversion table for the slow-speed reproduction (less than 0.5 times speed) from the storage device 10 and supplies the conversion table to the converter main body 7A. On the other hand, at this time, the field detector 11 reads out the field position information currently being reproduced from the digital video signal supplied from the reproducer 5, and supplies the field position information to the converter body 7A. Based on the conversion table supplied from the selector 7B and the field position information supplied from the field detector 11, the converter main unit 7A performs time code conversion (TC) at the time of slow playback (less than 0.5 times speed).₃₀→ TC₂₄). As a result, even when a 30 FPS signal is reproduced at a low speed such as less than 0.5 times speed, the TC₃₀With high accuracy₂₄Can be converted to The conversion table shown in FIG. 13 is a conversion table for low-speed reproduction when performing 2-3 pull-down conversion processing, and when converting a 24p video signal into a 60i video signal by another format conversion, the conversion table shown in FIG. A conversion table corresponding to the format conversion is set and stored in the storage device 10.
[0059]
In the above-described embodiment, the TC executed when converting from a 30 FPS signal to a 24 FPS signal is used.₃₀From TC₂₄The invention was implemented in the transformation of The present invention is not an invention that can be implemented only in such a conversion form. In addition, TC implemented when converting a 30 FPS signal to a 25 FPS signal₃₀From TC₂₅To TC, or TC implemented when converting from 24 FPS signal to 30 FPS signal₂₄From TC₃₀The present invention can be implemented in the conversion of. Further, in addition to the interlace signal, for example, a signal of 60 Hz per second may be converted to a 30 Hz TC (TC₃₀) May be a progressive signal. That is, the present invention can be basically implemented in any time code conversion form.
[0060]
【The invention's effect】
As described above, according to the present invention, at the point where the synchronization does not match between the 30 Hz synchronization signal serving as the synchronization signal of the 30 FPS signal before conversion and the 24 Hz synchronization signal serving as the synchronization signal of the 24 FPS signal after conversion. Also TC₃₀And TC₂₄Can be synchronized with the₃₀→ TC₂₄Responsiveness of the time code conversion is improved.
[0061]
Furthermore, the time code can be accurately converted even at the time of low-speed reproduction, and the editing control characteristics are improved accordingly.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a video conversion device incorporating a time code conversion device according to an embodiment of the present invention.
FIG. 2 is a diagram showing a configuration of a conversion table.
FIG. 3 is a timing chart showing a time code conversion pattern 1;
FIG. 4 is a timing chart showing a time code conversion pattern 2;
FIG. 5 is a timing chart showing a time code conversion pattern 3;
FIG. 6 is a timing chart showing a time code conversion pattern 4;
FIG. 7 is a timing chart showing a time code conversion pattern 5;
FIG. 8 is a timing chart showing a time code conversion process in pattern 1;
FIG. 9 is a timing chart showing a time code conversion process in pattern 2;
FIG. 10 is a timing chart showing a time code conversion process in pattern 3;
FIG. 11 is a timing chart showing a time code conversion process in pattern 4;
FIG. 12 is a timing chart showing a time code conversion process in pattern 5;
FIG. 13 is a diagram showing a configuration of a conversion table at the time of low-speed reproduction.
[Explanation of symbols]
1 Video converter
2 30Hz synchronous signal generator
3 24Hz synchronous signal generator
4 Tape runner
5 Regenerator
6 Sampling device
7 TC converter
7A converter body
7B selector
8 Video converter
9 Pattern detector
10 Recorder
11 Field detector
12 Speed detector

Claims (10)

When converting a first video signal having a first frame rate into a second video signal having a second frame rate different from the first frame rate, the first video signal corresponds to the first video signal. A time code conversion device for converting a first time code into a second time code corresponding to the second video signal,
A pattern detector for detecting a phase difference pattern between the time information added to the first video signal and the time information serving as a reference at the time of conversion to the second video signal;
A storage unit that sets and stores a conversion table for converting the first time code into the second time code for each of the phase difference patterns;
A time code converter that reads a conversion table corresponding to the phase difference pattern detected by the pattern detector from the storage device, and converts the first time code into the second time code based on the read conversion table; When,
A time code conversion device comprising: The time code conversion device according to claim 1,
The pattern detector sets a greatest common divisor frequency between a first synchronization signal added to the first video signal and a second synchronization signal used in converting the second video signal, The first and second synchronization signals are frequency-divided so as to have a set greatest common divisor frequency to generate a first synchronization frequency division signal and a second synchronization frequency division signal, respectively. A phase difference pattern between the first and second synchronization frequency-divided signals is detected;
A time code conversion device, characterized in that: The time code converter according to claim 1 or 2,
The first video signal is a video signal in a format of 30 frames / sec, and the second video signal is a video signal in a format of 24 frames / sec.
A time code conversion device, characterized in that: The time code conversion device according to claim 3,
The pattern detector includes a first 6-Hz synchronous frequency-divided signal corresponding to a 5-frequency-divided signal of the 30-Hz synchronous signal added to the first video signal, and a 24-Hz synchronous signal used at the time of the second video signal conversion. A second 6-Hz synchronous frequency-divided signal corresponding to the 4-frequency-divided signal is generated, and a phase difference pattern between the generated first and second 6-Hz synchronous frequency-divided signals is detected.
A time code conversion device, characterized in that: The time code conversion device according to claim 4,
The pattern detector generates, as the first and second 6 Hz synchronous frequency-divided signals, numerical data that repeats count-up at a 6 Hz cycle, and compares the generated numerical data with each other for an enhancement pattern, thereby obtaining the phase data. To detect the difference pattern,
A time code conversion device, characterized in that: The time code conversion device according to claim 5,
The pattern detector,
Generating a first 6 Hz synchronous frequency-divided signal converted into the numerical data from a remainder obtained by dividing the first time code by an integer 5;
The second 6-Hz synchronization frequency converted into the numerical data by repeating count-up based on the 30-Hz synchronization signal in a cycle of the second 6-Hz synchronization frequency signal generated by dividing the 24-Hz synchronization signal by 4. Generate a signal,
Is a thing,
A time code conversion device, characterized in that: The time code conversion device according to any one of claims 1 to 6,
A speed detector for detecting a reproduction speed of the first video signal when converting the first video signal into the second video signal;
A state detector for detecting a video progress state of the first video signal when the first video signal is reproduced;
Further comprising
The storage device further sets and stores the conversion table corresponding to a video lapse state at the time of slow-speed reproduction of the first video signal,
The time code converter stores the conversion table according to the video state detected by the state detector when the speed detector determines that the reproduction speed of the first video signal is slow reproduction. And converting the first time code into the second time code based on the read conversion table;
When judging that the reproduction speed is other than the low-speed reproduction, the conversion table set for each of the phase difference patterns is read from the storage device, and the first time code is converted to the second time code based on the read conversion table. To convert to time code,
A time code conversion device, characterized in that: The time code conversion device according to claim 7,
The first video signal is an interlaced video signal;
The state detector is for detecting a field position of the first video signal.
A time code conversion device, characterized in that: The time code conversion device according to claim 7 or 8,
The speed detector determines that the case where the reproduction speed of the first video signal is less than 0.5 times speed is slow-speed reproduction.
A time code conversion device, characterized in that: A time code converter according to claim 1, and a video converter that converts the first video signal into the second video signal.
A video conversion device comprising:

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