JP2004304130A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2004304130A
JP2004304130A JP2003098263A JP2003098263A JP2004304130A JP 2004304130 A JP2004304130 A JP 2004304130A JP 2003098263 A JP2003098263 A JP 2003098263A JP 2003098263 A JP2003098263 A JP 2003098263A JP 2004304130 A JP2004304130 A JP 2004304130A
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Japan
Prior art keywords
film
sio
insulating film
etching
layer
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JP2003098263A
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Japanese (ja)
Inventor
Hisaki Hara
寿樹 原
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Seiko Epson Corp
セイコーエプソン株式会社
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Abstract

Provided is a method for manufacturing a semiconductor device in which, when an opening is formed in an insulating film over a semiconductor layer or a semiconductor substrate, overetching of the semiconductor layer or the semiconductor substrate can be suppressed.
After forming an SiO 2 film 13 for an interlayer insulating film on a silicon layer 5 of an SOI substrate 10, an electron beam or a laser is contacted under conditions that cut off bonds between atoms of the SiO 2 film 13. Irradiation is performed on the SiO 2 film 13 in the hole formation region to modify the SiO 2 film 13 in the region, and then the modified SiO 2 film 13 is removed by dry etching to form a contact hole. It is possible to weaken the resistance to etching of the SiO 2 film 13, it is possible to increase the etching rate of the SiO 2 film 13.
[Selection] Fig. 2

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for application to a step of forming a contact hole in a transistor having an SOI structure.
[0002]
[Prior art]
In recent years, SOI (silicon on insulator) wafers have been used in place of bulk silicon wafers for the purpose of reducing power consumption and increasing the speed of devices. An SOI wafer is a wafer having a three-layer structure in which an insulating layer is provided on a semiconductor wafer and a semiconductor layer is provided on the insulating layer. When an element such as a MOS transistor is formed in this semiconductor layer, for example, a single crystal silicon layer, the elements can be completely separated. Further, since the capacity of the source / drain diffusion layer in the MOS transistor can be reduced, the operation speed can be improved.
[0003]
In the process of forming the MOS transistor, the insulating layer between the source / drain diffusion layers is etched to draw out the source / drain diffusion layers below the interlayer insulating film formed on the semiconductor layer onto the interlayer insulating film. To form a contact hole. Etching for forming a contact hole (hereinafter, referred to as contact hole etching) includes a method of performing all dry etching and a method of performing wet etching first and then performing dry etching. The final stage of the contact hole etching is performed by dry etching.
[0004]
Normally, the thickness of an interlayer insulating film in which a contact hole is formed varies in the wafer surface, and the etching rate of dry etching (the amount of etching per unit time) also varies in the wafer surface. Therefore, in order to form a contact hole in a wafer surface with good reproducibility, it is necessary to perform contact hole etching excessively with respect to the thickness of the interlayer insulating film (hereinafter referred to as over-etching). By this over-etching, the silicon layer on the SOI wafer is slightly etched. Further, when the thickness of the silicon layer is particularly small, the silicon layer may be completely etched and penetrated by the over-etching.
[0005]
In order to avoid the penetration of the silicon layer, a method of laminating a silicon layer for an etching stopper or a silicon nitride layer between the silicon layer of the SOI wafer and the interlayer insulating film is known (for example, see Patent Reference 1). As another method, nitrogen ions are implanted into the silicon layer of the SOI wafer, and then an interlayer insulating film is laminated on the SOI wafer, and between the silicon layer and the interlayer insulating film, or between the silicon layer and the SOI wafer. A method of forming a silicon nitride for an etching stopper between the insulating layer and the insulating layer is also known (for example, see Patent Document 2).
[0006]
[Patent Document 1]
JP-A-7-74126 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2000-133709 [Non-Patent Document 1]
M. Matsumoto, Y .; Maeda, M .; Kuwahara and M.K. Takayama, Proceeding of Radtech '97 Asia, (1997)
[0007]
[Problems to be solved by the invention]
By the way, according to the conventional method of manufacturing a semiconductor device, a silicon nitride layer for an etching stopper is laminated between the silicon layer and the interlayer insulating film in order to prevent the silicon layer from penetrating in the SOI wafer. I was Alternatively, nitrogen ions are implanted into the silicon layer, and then an interlayer insulating film is laminated, so that a silicon nitride layer for an etching stopper is formed between the silicon layer and the interlayer insulating film layer.
[0008]
However, in the method of laminating the silicon nitride layer between the silicon layer of the SOI wafer and the interlayer insulating film, stress is generated between the silicon nitride layer and the silicon layer because the silicon nitride layer and the silicon layer have different expansion coefficients. . Therefore, there is a possibility that the electrical characteristics of the MOS transistor are adversely affected. Further, in the method of forming a silicon nitride layer for an etching stopper by injecting nitrogen ions into the silicon layer, the silicon layer is reduced in film thickness, so that the parasitic resistance of the source / drain diffusion layers may increase. was there.
[0009]
Therefore, the present invention has solved such a problem, and when forming an opening in an insulating film over a semiconductor layer or a semiconductor substrate, it is possible to suppress overetching of the semiconductor layer or the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, a first method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor layer or a semiconductor substrate, and a step of cutting off bonds between atoms of the insulating film. Irradiating an insulating film in a predetermined region with an electron beam or a laser under the conditions to modify the insulating film in the predetermined region; and etching and removing the modified insulating film to form a predetermined opening. And the following.
[0011]
Here, the semiconductor layer is, for example, a silicon layer, and the semiconductor substrate is, for example, a bulk silicon substrate. The insulating film is, for example, a silicon oxide film for an interlayer insulating film. When energy equal to or higher than the bonding energy between silicon atoms and oxygen atoms is applied to the silicon oxide film, electrons related to the bonding between silicon atoms and oxygen atoms are excited, and the bonding state between silicon atoms and oxygen atoms is eliminated.
[0012]
According to the first method for manufacturing a semiconductor device of the present invention, the bond between atoms constituting the insulating film can be broken by irradiation with an electron beam or a laser. Can be weakened. Therefore, the etching rate of the insulating film can be increased, and the etching selectivity between the insulating film and the semiconductor layer or the semiconductor substrate under the insulating film can be increased.
[0013]
Accordingly, when an opening is formed in a semiconductor layer or an insulating film over a semiconductor substrate, overetching of the semiconductor layer or the semiconductor substrate can be suppressed.
A second method for manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film on a semiconductor layer or a semiconductor substrate; a step of etching and thinning the insulating film in a predetermined region; A step of irradiating the thinned insulating film with an electron beam or a laser under conditions that break the bond, and modifying the thinned insulating film; and etching and removing the modified insulating film by a predetermined method. Forming an opening of the above.
[0014]
According to the second method for manufacturing a semiconductor device according to the present invention, the thickness of the insulating film irradiated with an electron beam or a laser is reduced as compared with the first method for manufacturing a semiconductor device. The irradiation time of an electron beam or a laser can be reduced.
A third method for manufacturing a semiconductor device according to the present invention is characterized in that, in the first and second methods for manufacturing a semiconductor device, the semiconductor layer is a silicon layer of an SOI substrate.
[0015]
According to the third method for manufacturing a semiconductor device of the present invention, when an opening is formed in an insulating film on a silicon layer included in an SOI substrate, overetching of the silicon layer can be suppressed. The penetration of the layer can be prevented.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
(1) First Embodiment FIGS. 1A to 2B are process diagrams showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. This process chart shows a method of forming a contact hole 17 in the SOI wafer 10 along a procedure.
[0017]
As shown in FIG. 1A, first, an SOI wafer 10 is prepared. The SOI wafer 10 has a three-layer structure including, for example, a silicon wafer 1, a silicon oxide layer 3, and a single-crystal silicon layer 5 from below. Among these, the silicon layer 5 is an element forming layer on which elements such as MOS transistors are formed, and its thickness is, for example, about 50 nm. The SOI substrate 10 having such a three-layer structure is formed, for example, by a well-known SIMOX (silicon implanted oxide) method or a bonding method.
[0018]
Next, as shown in FIG. 1B, a silicon oxide film (hereinafter, referred to as an SiO 2 film) 13 is formed on the silicon layer 5. This SiO 2 film 13 is an interlayer insulating film, and its thickness is about 600 nm. The SiO 2 film 13 is formed by CVD (chemical vapor deposition) or the like.
Next, a resist pattern 15 is formed on the SiO 2 film 13 so as to open a region for forming a contact hole (hereinafter, referred to as a contact hole forming region). This contact hole formation region is, for example, a region on a source / drain diffusion layer of a MOS transistor. The formation of the resist pattern 15 is performed by, for example, lithography.
[0019]
That is, first, a resist for electron beam lithography is applied on the SiO 2 film 13. Next, an exposure mask for forming a contact hole is set in an exposure device such as a stepper, and the resist is exposed to light using this exposure device. Then, the exposed resist is developed. As a result, a resist pattern 15 is formed that exposes only the surface of the SiO 2 film 13 in the contact hole formation region and covers other regions.
[0020]
Next, using the resist pattern 15 as a mask, the SiO 2 film 13 is irradiated with an electron beam at an acceleration voltage of several to several tens keV to break the bonds between atoms in the SiO 2 film 13 in the contact hole formation region. Reform to a state. Here, since the bonding energy between Si and Si of the SiO 2 film 13 is about 7.6 eV and the bonding energy between Si and O is about 10.8 eV, the electron beam of about 10.8 eV or more is basically considered. Irradiation may be performed on the SiO 2 film 13.
[0021]
However, in practice, not all of the electron energy of the electron beam is used to break bonds between atoms, so the acceleration voltage of the electron beam is set to a value higher than these bond energies. For example, when the thickness of the SiO 2 film 13 is about 600 nm, the acceleration voltage of the electron beam is 5 to 10 keV, and the electron density is about 1 to 2 C / cm 2 . The acceleration voltage of the electron beam is set according to the thickness of the SiO 2 film 13. The acceleration voltage controls the depth of electron beam irradiation.
[0022]
Here, Equation (1) is known as a relationship between the acceleration voltage (energy) V [kV] and the electron beam irradiation depth S [μm] (electron range, stopping power) (for example, See Non-Patent Document 1.)
S = 0.0667V 5/3 /ρ...▲1▼
In the formula (1), ρ [g / cm 3 ] is the density of a substance to be irradiated with an electron beam (hereinafter, referred to as a substance to be irradiated). When the substance to be irradiated is SiO 2 (quartz glass), since ρ = 2.2 [g / cm 3 ], the relationship between the energy V [kV] and the depth S [μm] can be obtained from Equation (1) in FIG. Is obtained. Based on this, the acceleration voltage of the electron beam may be set in consideration of the thickness of the SiO 2 film 13.
[0023]
By irradiation of the electron beam, as compared with the conventional method, the etching rate of the SiO 2 film 13 of the contact hole formation region can be made higher than the SiO 2 film 13 in other areas. That is, in the contact hole formation region, a SiO 2 film 13, it is possible to increase the etching selectivity of the silicon layer 5 underneath the SiO 2 film 13.
[0024]
Next, the contact hole 17 is formed by removing the SiO 2 film 13 by dry etching while leaving the resist pattern 15. This dry etching (contact hole etching) is performed by, for example, RIE (reactive ion etching). The conditions of the RIE are, for example, a gas type and its flow rate ratio are CHF 3 / O 2 = 75 sccm / 8 sccm, the pressure in the chamber is 50 mTorr (6.6 Pa), and the high frequency power is 800 W (J / s). Since the SiO 2 film 13 in the contact hole forming region is modified to increase the etching rate, the contact hole etching conditions are more mild (the high-frequency power is reduced and the etching time is shortened) as compared with the conventional method. Etc.). Thereafter, a metal film such as an aluminum alloy is buried in the contact hole 17 and patterned into a wiring or electrode shape to complete a semiconductor device.
[0025]
As described above, according to the method for manufacturing a semiconductor device according to the first embodiment of the present invention, the SiO 2 film 13 in the contact formation region is irradiated with the electron beam, thereby forming the SiO 2 film 13 and the SiO 2 film. The etching selectivity with respect to the silicon layer 5 below 13 can be increased. Accordingly, overetching of the silicon layer 5 can be suppressed, and penetration of the silicon layer 5 can be prevented. Thus, a semiconductor device having stable electric characteristics can be manufactured.
(2) In the second embodiment the first embodiment described above, after forming a resist pattern 15 on the SiO 2 film 13 is irradiated with an electron beam to the SiO 2 film 13 using the resist pattern 15 as a mask, SiO 2 The method for modifying the film 13 to a state in which the bond between atoms has been cut has been described.
[0026]
However, in this method, as the thickness of the SiO 2 film 13 increases, the irradiation energy of the electron beam needs to be increased, and it is difficult to control the depth of the incident electrons. Therefore, not only the SiO 2 film 13 but also the underlying silicon layer 5 may be modified. Therefore, in the second embodiment, a description will be given of a method of manufacturing a semiconductor device capable of reducing the possibility that the silicon layer 5 is adversely affected by electron beam irradiation, as compared with the above-described first embodiment. .
[0027]
3A to 3C are process diagrams showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. This process chart shows a method of forming a contact hole in an SOI wafer along a procedure. The steps up to the step of forming the resist pattern 15 shown in FIG. 3A are the same as the steps of forming the contact holes described in the first embodiment. Therefore, in FIGS. 3 (A) to 3 (C), parts corresponding to FIGS. 1 (A) to 2 (B) are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0028]
In FIG. 3A, after a resist pattern 15 is formed, the SiO 2 film 13 is dry-etched using the resist pattern 15 as a mask to reduce the thickness of the SiO 2 film 13 in the contact hole formation region to, for example, about 100 nm. I do.
This first dry etching is performed by, for example, RIE. The conditions of the RIE are, for example, a gas type and its flow rate ratio are CHF 3 / O 2 = 75 sccm / 8 sccm, the pressure in the chamber is 50 mTorr (6.6 Pa), and the high frequency power is 1200 W (J / s). In the first dry etching, since the SiO 2 film is left at about 100 nm, it is not necessary to consider over-etching of the silicon layer 5. Therefore, the high frequency power can be set higher than the contact hole etching described in the first embodiment.
[0029]
Next, by using the resist pattern 15 as a mask, the SiO 2 film 13 is irradiated with an electron beam to modify the thinned SiO 2 film 13 into a state in which bonds between atoms have been cut. Since the SiO 2 film 13 to be modified is thinner than in the first embodiment, the irradiation energy of the electron beam can be set lower.
For example, the acceleration voltage of the electron beam is 2 to 4 keV, and the electron density is about 1 to 2 C / cm 2 . Thus, compared to the first embodiment, the incidence of electrons on the silicon layer 5 by an electron beam can be suppressed, and the possibility of adversely affecting the silicon layer 5 can be reduced.
[0030]
Next, using the resist pattern 15 as a mask, the SiO 2 film 13 is dry-etched to form a contact hole 17. This second dry etching is performed by, for example, RIE. The conditions of the RIE are, for example, a gas type and a flow rate ratio thereof are CHF 3 / O 2 = 75 sccm / 8 sccm, the pressure in the chamber is 50 mTorr (6.6 Pa), and the power is 1200 W (J / s). In the second dry etching, the etching rate of the SiO 2 film 13 is increased by the irradiation of the electron beam. Therefore, the second dry etching is performed under milder conditions (reduced high-frequency power) than the first dry etching. To shorten the etching time). Thereafter, as in the first embodiment, a metal film such as an aluminum alloy is buried in the contact hole 17 and patterned into a wiring or electrode shape to complete a semiconductor device.
[0031]
As described above, according to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, it is possible to obtain the same functions and effects as those of the above-described first embodiment. Further, since the film thickness of the SiO 2 film 13 irradiated with the electron beam is reduced to about 100 nm, the irradiation time of the electron beam can be shortened. Thus, the possibility that the irradiation of the electron beam adversely affects the silicon layer 5 can be reduced.
(3) Third Embodiment In the first and second embodiments described above, as shown in FIGS. 2A and 3B, the SiO 2 film 13 in the contact hole formation region is irradiated with an electron beam. The case where the Si—Si bond and the Si—O bond of the SiO 2 film 13 are cut has been described.
[0032]
However, the breaking of the interatomic bond described in the first and second embodiments is not limited to the electron beam, and may be performed by a laser. For example, an excimer laser such as KrF (oscillation wavelength 248 nm) 5.0 eV or ArF (oscillation wavelength 193 nm) 6.4 eV is used. In this case, it is preferable to use a resist pattern 15 that can absorb laser light.
[0033]
The energy of this type of excimer laser is smaller than the bonding energy between Si—Si and between Si—O, but usually, the SiO 2 film 13 for the interlayer insulating film is often formed by CVD, and its structure is It is amorphous.
For this reason, there is a portion in the SiO 2 film 13 where the bonding energy between Si—Si and between Si—O is weak, and the energy of the excimer laser such as KrF or ArF is absorbed by this portion. Further, in order not to adversely affect the silicon layer 5 under the SiO 2 film 13, it is necessary to apply sufficient energy to the SiO 2 film 13 to break the bond between Si and O.
[0034]
Here, the excimer laser two-photon absorption mode is a phenomenon in which one molecule absorbs two photons at a time and is excited. In a laser having a high energy such as an excimer laser, two-photon absorption occurs, and energy twice as much as the incident energy is absorbed. Since this is comparable to the binding energy between Si—O, Si—O is selectively excited.
[0035]
Note that the oscillation output of the excimer laser needs to be kept low enough that the SiO 2 film 13 is not gasified or turned into fine particles. This is because if the SiO 2 film 13 is gasified or turned into fine particles, there is a high possibility that the silicon layer 5 under the SiO 2 film 13 will be gasified or turned into fine particles. For this reason, the oscillation output of the excimer laser is set lower than, for example, 100 W (J / s).
[0036]
In the first to third embodiments described above, the silicon layer 5 corresponds to the semiconductor layer of the present invention, and the SiO 2 film 13 corresponds to the insulating film of the present invention. The contact hole forming region corresponds to a predetermined region of the present invention, and the contact hole 17 corresponds to an opening of the present invention.
[Brief description of the drawings]
FIG. 1 is a process chart showing a method (1) for manufacturing a semiconductor device according to a first embodiment.
FIG. 2 is a process chart showing a method (2) for manufacturing the semiconductor device according to the first embodiment.
FIG. 3 is a process chart showing a method for manufacturing a semiconductor device according to a second embodiment.
FIG. 4 is a table showing a relationship between energy V [kV] and depth S [μm].
[Explanation of symbols]
Reference Signs List 1 silicon substrate, 3 silicon oxide layer, 5 silicon layer, 10 SOI wafer, 13 SiO 2 film (interlayer insulating film), 15 resist pattern, 17 contact hole

Claims (3)

  1. Forming an insulating film on a semiconductor layer or a semiconductor substrate,
    Irradiating the insulating film in a predetermined region with an electron beam or a laser under such conditions as to break the bond between the atoms of the insulating film, a step of modifying the insulating film in the predetermined region,
    Etching the modified insulating film to form a predetermined opening.
  2. Forming an insulating film on a semiconductor layer or a semiconductor substrate,
    A step of etching and thinning the insulating film in a predetermined region;
    A step of irradiating the thinned insulating film with an electron beam or a laser under conditions such as breaking the bonds between atoms of the insulating film, and modifying the thinned insulating film,
    Etching the modified insulating film to form a predetermined opening.
  3. 3. The method according to claim 1, wherein the semiconductor layer is a silicon layer of an SOI substrate. 4.
JP2003098263A 2003-04-01 2003-04-01 Manufacturing method of semiconductor device Withdrawn JP2004304130A (en)

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Cited By (15)

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JP2007187608A (en) * 2006-01-16 2007-07-26 Denso Corp Manufacturing method of semiconductor dynamic quantity sensor
WO2010016351A1 (en) * 2008-08-07 2010-02-11 株式会社フジクラ Method for manufacturing semiconductor device
JP2010164394A (en) * 2009-01-15 2010-07-29 Denso Corp Method of manufacturing semiconductor device
US8541319B2 (en) 2010-07-26 2013-09-24 Hamamatsu Photonics K.K. Laser processing method
US8591753B2 (en) 2010-07-26 2013-11-26 Hamamatsu Photonics K.K. Laser processing method
US8673167B2 (en) 2010-07-26 2014-03-18 Hamamatsu Photonics K.K. Laser processing method
US8685269B2 (en) 2010-07-26 2014-04-01 Hamamatsu Photonics K.K. Laser processing method
US8741777B2 (en) 2010-07-26 2014-06-03 Hamamatsu Photonics K.K. Substrate processing method
US8802544B2 (en) 2010-07-26 2014-08-12 Hamamatsu Photonics K.K. Method for manufacturing chip including a functional device formed on a substrate
US8828873B2 (en) 2010-07-26 2014-09-09 Hamamatsu Photonics K.K. Method for manufacturing semiconductor device
US8828260B2 (en) 2010-07-26 2014-09-09 Hamamatsu Photonics K.K. Substrate processing method
US8841213B2 (en) 2010-07-26 2014-09-23 Hamamatsu Photonics K.K. Method for manufacturing interposer
US8945416B2 (en) 2010-07-26 2015-02-03 Hamamatsu Photonics K.K. Laser processing method
US8961806B2 (en) 2010-07-26 2015-02-24 Hamamatsu Photonics K.K. Laser processing method
US9108269B2 (en) 2010-07-26 2015-08-18 Hamamatsu Photonics K. K. Method for manufacturing light-absorbing substrate and method for manufacturing mold for making same

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007187608A (en) * 2006-01-16 2007-07-26 Denso Corp Manufacturing method of semiconductor dynamic quantity sensor
JP4692292B2 (en) * 2006-01-16 2011-06-01 株式会社デンソー Manufacturing method of semiconductor dynamic quantity sensor
WO2010016351A1 (en) * 2008-08-07 2010-02-11 株式会社フジクラ Method for manufacturing semiconductor device
EP2312619A1 (en) * 2008-08-07 2011-04-20 Fujikura, Ltd. Method for manufacturing semiconductor device
JPWO2010016351A1 (en) * 2008-08-07 2012-01-19 株式会社フジクラ Manufacturing method of semiconductor device
EP2312619A4 (en) * 2008-08-07 2012-12-12 Fujikura Ltd Method for manufacturing semiconductor device
JP2010164394A (en) * 2009-01-15 2010-07-29 Denso Corp Method of manufacturing semiconductor device
US8673167B2 (en) 2010-07-26 2014-03-18 Hamamatsu Photonics K.K. Laser processing method
US8591753B2 (en) 2010-07-26 2013-11-26 Hamamatsu Photonics K.K. Laser processing method
US8541319B2 (en) 2010-07-26 2013-09-24 Hamamatsu Photonics K.K. Laser processing method
US8685269B2 (en) 2010-07-26 2014-04-01 Hamamatsu Photonics K.K. Laser processing method
US8741777B2 (en) 2010-07-26 2014-06-03 Hamamatsu Photonics K.K. Substrate processing method
US8802544B2 (en) 2010-07-26 2014-08-12 Hamamatsu Photonics K.K. Method for manufacturing chip including a functional device formed on a substrate
US8828873B2 (en) 2010-07-26 2014-09-09 Hamamatsu Photonics K.K. Method for manufacturing semiconductor device
US8828260B2 (en) 2010-07-26 2014-09-09 Hamamatsu Photonics K.K. Substrate processing method
US8841213B2 (en) 2010-07-26 2014-09-23 Hamamatsu Photonics K.K. Method for manufacturing interposer
US8945416B2 (en) 2010-07-26 2015-02-03 Hamamatsu Photonics K.K. Laser processing method
US8961806B2 (en) 2010-07-26 2015-02-24 Hamamatsu Photonics K.K. Laser processing method
US9108269B2 (en) 2010-07-26 2015-08-18 Hamamatsu Photonics K. K. Method for manufacturing light-absorbing substrate and method for manufacturing mold for making same

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