JP2004303752A - Semiconductor device and optical transceiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a shield structure of electromagnetic wave noise for restricting an electromagnetic interference between semiconductor components mounted on the same substrate surface. <P>SOLUTION: On the outer layer of a substrate touching a casing, an outer layer conductor pattern for isolating different semiconductor circuits, respectively, on the substrate surface is formed. The outer layer conductor pattern is connected with an inner layer conductor pattern through a plurality of vias, and the signal line of the semiconductor circuit is passed through a gap formed at a part of the outer layer conductor pattern. Consequently, an electromagnetic interference between semiconductor components mounted on the same substrate surface is restricted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a substrate on which semiconductor components are mounted and a housing for housing the substrate, and an optical transceiver having a transmission circuit and a reception circuit mounted inside the housing.
[0002]
[Prior art]
In recent years, with an increase in communication traffic in an optical communication system, the transmission speed of an optical transceiver mounted on the system has been improved. Optical transceivers that transmit signals at high transmission speeds of 2.5 Gbps and 10 Gbps have already been commercialized, and 40 Gbps optical transceivers are currently being put into practical use. In this type of optical transceiver, electromagnetic wave noise is radiated inside the housing by inputting and outputting a high-frequency electric signal. As the transmission signal speeds up, the electromagnetic wave noise is erroneously recognized as a transmission signal, so that a malfunction easily occurs. In particular, a signal radiated from the high-frequency circuit of the transmission circuit is regarded as noise by the high-sensitivity reception circuit, and the S / N ratio is deteriorated.
[0003]
As a countermeasure against noise of a conventional optical transceiver, there has been a method of receiving a weak signal from a light receiving element and covering a light receiving circuit which is weak against noise with a shield cover. In addition, by giving the role of a hinge to a flexible flexible substrate that connects the rigid rigid substrates to each other, by folding the rigid substrate, the transmission / reception circuit is wrapped by a ground layer to form a shield cover, and the transmission / reception circuit is shielded. There was also a method (for example, see Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-85733 A
[0005]
In a transceiver as described in Patent Document 1, both a transmission circuit and a reception circuit are arranged in the same space surrounded by a shield cover, so that an oscillator constituting the transmission circuit and a reception circuit are constituted. Noise interference occurred with the amplifier. Further, as disclosed in FIG. 6 of Patent Document 1, when a cutout provided in a substrate and a projection of a shield case are fitted, an electromagnetic wave leaks from the cutout and a sufficient shielding effect is obtained. There was a problem that can not be.
[0006]
In order to solve this problem, there is known a method in which an electromagnetic wave absorber is arranged close to a component having a high noise radiation level in a transmission circuit or a component having a high reception sensitivity in a reception circuit (for example, Patent Document 2). reference).
[0007]
[Patent Document 2]
JP-A-2002-185408
[0008]
However, the provision of the electromagnetic wave absorber increases the number of components and necessitates adjustment of the installation position of the electromagnetic wave absorber, which hinders a reduction in the price of the optical transceiver. Further, the high-frequency characteristics of the transmission circuit and the reception circuit vary depending on the installation position of the electromagnetic wave absorber, and it has been difficult to manufacture an optical transceiver having a constant quality. In addition, the high frequency characteristics fluctuated due to the aging of the electromagnetic wave absorber.
[0009]
On the other hand, as disclosed in Patent Literature 2, different shields are provided inside a housing, and a substrate on which a transmitting circuit is mounted and another substrate on which a receiving circuit is mounted are housed in different partitions. An optical transceiver that separates a transmitting circuit from a receiving circuit by doing so is known. In this case, it is necessary to form a two-layer board for the transmitting circuit and the receiving circuit, and to provide a gap between the partition wall for shielding and the side end face of the circuit board. The wiring pattern is restricted.
[0010]
Therefore, after mounting the transmission circuit and the reception circuit on the same substrate, a slit is provided in the substrate between the transmission circuit and the reception circuit, and a linear shield wall having a length shorter than the substrate length is inserted into the slit. This partially shields the transmission circuit and the reception circuit. As a result, the number of boards can be reduced to one, the mounting area of the boards can be increased, and the cost of parts can be reduced. Details of this configuration will be described later in the description of the embodiment.
[0011]
However, since only a linear shield wall is interposed between the transmission circuit and the reception circuit, and the transmission circuit and the reception circuit are not shielded in a completely isolated state, electromagnetic wave noise radiated from the transmitter becomes inductive. It is conceivable that the light enters the receiver through the inner layer of the body substrate and enters the receiver, and the effect of the electromagnetic wave leaking to the inner layer of the dielectric substrate has not been considered.
[0012]
When a shield wall is provided so as to eliminate the influence of electromagnetic wave noise transmitted and received between the semiconductor components, the ground surface of the substrate is connected to the ground potential of the housing. For this reason, external noise input through the housing fluctuates the ground potential of the transmission circuit or the reception circuit. Further, there is the opposite effect, and the signal source in the transmission circuit or the reception circuit affects the potential of the housing, causing a potential change outside the housing. This problem similarly exists even when the radio wave absorber is provided.
[0013]
[Problems to be solved by the invention]
Conventional semiconductor devices such as optical transceivers have an oscillator and an amplifier mounted on the same substrate surface, and a slit is provided on the substrate between the two devices in order to increase the mounting area of the substrate and reduce the number of components. It has been considered to install a straight shield wall in the slit. However, there is a problem that electromagnetic wave noise radiated from the oscillator passes through the inner layer of the dielectric substrate and enters the amplifier, causing interference between the oscillator and the amplifier, failing to obtain a sufficient shielding effect.
[0014]
In addition, since the mounting board of the semiconductor component is grounded to the housing, external noise input through the housing fluctuates the ground potential of the semiconductor component shielded in the housing, and the operation of the semiconductor component is reduced. There was a problem of becoming unstable.
[0015]
The present invention has been made to solve the above problem, and has as its object to obtain an electromagnetic noise shielding structure for suppressing electromagnetic interference between semiconductor components mounted on the same substrate surface.
[0016]
It is another object of the present invention to suppress electromagnetic interference between semiconductor components and to obtain a shield structure for electromagnetic wave noise in which a potential change of a housing does not change a potential of a ground plane of the semiconductor component.
[0017]
[Means for Solving the Problems]
A semiconductor device according to the present invention includes an outer conductor pattern provided in an outer layer of a substrate and having at least a part thereof formed with a gap portion forming a gap, an inner conductor pattern provided in an inner layer of the substrate, the outer conductor pattern and the inner conductor pattern And a multi-layer substrate formed by laminating a dielectric, and a periphery surrounded by the outer-layer conductor pattern. A first semiconductor component mounted on the outer layer of the substrate and connected to one end of the outer conductor line, and a part of the outer conductor pattern surrounding the first semiconductor component together with the first semiconductor component. A second semiconductor component mounted on the outer layer of the substrate and connected to the other end of the outer layer conductor line, and a wall surface forming an opening, and an end face of the wall surface is formed on the outer layer conductor path; In contact with the over emissions, in which a housing accommodating the first semiconductor component.
[0018]
Further, the semiconductor device according to the present invention is preferably a first inner layer conductor pattern provided on an outer layer of a substrate, and a first inner layer conductor pattern provided on a first inner layer of the substrate and having at least a gap formed at least in part. A second inner layer conductor pattern provided in a second inner layer of the substrate and having at least a part thereof formed with a gap partly spaced from each other, and surrounded by a first inner layer conductor pattern on a first inner layer surface of the substrate An inner-layer ground plane having a hollow formed therein, a via connecting the outer-layer conductor pattern to the first and second inner-layer conductor patterns, an outer-layer conductor line provided in an outer layer of the substrate, and a second layer of the substrate. An inner layer conductor line provided in the inner layer and passing through a gap of the inner layer conductor pattern, and a signal passing through a hollow hole in the inner layer ground plane and connecting one end of the outer layer conductor line and one end of the inner layer conductor line. A multilayer substrate formed by laminating a dielectric, and a semiconductor mounted on the outer layer of the substrate surrounded by the outer layer conductor pattern and connected to the other end of the outer layer conductor line And parts.
[0019]
Still further, the optical transceiver according to the present invention has a first pattern, a second pattern in which a first gap portion that forms a gap is formed partially, and a second pattern that forms a gap is formed in a portion. And a third pattern having a gap formed therein, an outer conductor pattern provided on the outer layer of the substrate, an inner conductor pattern provided on the inner layer of the substrate, a via connecting the outer conductor pattern and the inner conductor pattern, and A first and second outer conductor lines provided on the outer layer of the substrate and passing through the first and second gaps of the outer conductor pattern, respectively, and a multilayer substrate formed by laminating a dielectric; A transmission circuit mounted on the outer layer of the substrate and surrounded by first and second patterns of the outer conductor pattern, and connected to one end of the first outer conductor line; and the outer conductor pattern together with the transmission circuit The first putter A receiving circuit mounted on the outer layer of the substrate and surrounded by the first and third patterns of the outer layer conductor pattern, and connected to one end of the second outer layer conductor line; The transmission circuit is placed on the substrate outer layer with a part of the second pattern of the outer conductor pattern sandwiched therebetween, and the reception circuit is placed on the outer layer of the substrate with a part of the third pattern of the outer conductor pattern sandwiched therebetween, and A semiconductor component connected to the other end of the second outer conductor line, a first partition wall forming an opening, and a wall surface having a second partition wall, and an end surface of the wall abuts on the outer layer conductor pattern; A housing for accommodating the transmitting circuit in the first partition and a housing for accommodating the receiving circuit in the second partition.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a configuration diagram for explaining a semiconductor device according to a first embodiment of the present invention, and shows an example in which an optical transceiver is configured as a semiconductor device. FIG. 1A is a perspective view of the optical transceiver, showing a state in which the housing is seen through. FIG. 1B is a perspective view of a substrate constituting the optical transceiver (a view with the housing removed), and FIG. 1C is a sectional view of the optical transceiver taken along line AB.
[0021]
In the figure, a housing 1 is composed of an upper housing 2 and a lower housing 3. The upper housing 2 and the lower housing 3 are joined with the substrate 5 interposed therebetween. The substrate 5 has a transmitting circuit 10 and a receiving circuit 12 mounted thereon, and is configured by laminating dielectrics in multiple layers. The transmission circuit 10 is connected to a light emitting element module 15 that accommodates a semiconductor laser (LD). The transmission circuit 10 has a function as a drive circuit (driver) that generates a drive current whose amplitude is adjusted and intensity is modulated in order to extinguish (ON / OFF) the LD. The receiving circuit 12 is connected to a photodiode (PD) and a light receiving element module 17 containing a preamplifier for converting an output current of the PD into a voltage signal. The receiving circuit 12 functions as an amplifier that amplifies the output voltage signal of the light receiving element module 17 so as to adjust the amplitude. The transmission circuit 10 is connected to one end of the outer conductor line 20. The receiving circuit 12 is connected to one end of the outer conductor line 22. The integrated circuit 13 is connected to the other end of the outer conductor line 20. The integrated circuit 13 converts, for example, four low-speed (3.125 Gb / s) electric signals into one high-speed electric signal (10.3125 Gb / s [= 3.125 × 8/10 × 4 × 66 / 64]). The integrated circuit 14 is connected to the other end of the outer conductor line 22. The integrated circuit 14 extracts, for example, a clock signal from a received signal amplified and output by the reception circuit 12 and reproduces a data signal, and then converts a high-speed electric signal (10 Gb / s) into 16 low-speed (3 Gb / s) signals. .125 Gb / s) and a demultiplexing circuit (DEMUX) for separating the signals into electric signals.
[0022]
An outer conductor pattern 24 is provided on the periphery of the outer surface of the substrate 5, around the transmitting circuit 10, and around the receiving circuit 12. The substrate 5 is formed by the outer layer conductor pattern 24 so that the transmission area 25 where the transmission circuit 10 is arranged, the reception area 26 where the reception circuit 12 is arranged, and the integrated circuit area 27 where the integrated circuits 13 and 14 are mounted. It is divided into three areas. The outer conductor pattern 24 includes a first conductor pattern 30, a second conductor pattern 31, a third conductor pattern 32, a fourth conductor pattern 33, and a fifth conductor pattern. The first conductor pattern 30 is provided between the transmission circuit 10 and the reception circuit 12, and separates them from each other on the outer layer surface of the substrate. The second conductor pattern 31 is provided between the transmission circuit 10 and the integrated circuit 13. The third conductor pattern 32 is provided between the receiving circuit 12 and the integrated circuit 14. The fourth conductor pattern 33 is provided on the periphery of the substrate 5 on the transmission circuit 10 side. The fifth conductor pattern 34 is provided on the periphery of the substrate 5 on the receiving circuit 12 side. The second conductor pattern 31 and the third conductor pattern 32 are connected to the first conductor pattern 30 in a T-shape. The fourth conductor pattern 33 and the second conductor pattern 31 are connected in a T-shape. The fifth conductor pattern 34 and the third conductor pattern 32 are connected in a T-shape. As a result, the transmitting section region 25 is disposed so as to be surrounded on three sides by the first conductor pattern 30, the second conductor pattern 31, and the third conductor pattern 33. The outer layer conductor pattern 24 is partially disposed on the periphery of the substrate 5 on the light emitting element module 15 side, but no pattern is formed in a region where the light emitting element module 15 is disposed. As a result, the electrical connection between the light emitting element module 15 and the outer conductor pattern 24 is cut off. Similarly, the receiving section area 26 is arranged so as to be surrounded on three sides by the first conductor pattern 30, the third conductor pattern 32, and the fifth conductor pattern. The outer layer conductor pattern 24 is partially disposed on the periphery of the substrate 5 on the light receiving element module 17 side, but no pattern is formed in the region where the light receiving element module 17 is disposed.
[0023]
Although the outer conductor pattern 24 has been described so as to surround the transmitting circuit 10 and the receiving circuit 12 from three sides, however, this is not necessarily the case depending on the circuit. For example, if the light emitting element module 15 and the light receiving element module 17 do not have a portion that is in electrical contact with the edge of the substrate, the transmitting circuit 10 and the receiving circuit 12 may be surrounded from all sides.
[0024]
A gap 38 is provided in the second conductor pattern 31, and the outer layer conductor line 20 passes through the gap 38. A gap 39 is provided in the third conductor pattern 32, and the outer conductor line 22 passes through the gap 39. The substrate 5 is sandwiched between a conductive pad 40 in contact with the upper surface and a conductive pad 41 in contact with the lower surface. That is, the conductive pad 40 is sandwiched between the upper housing 2 and the substrate 5, and the conductive pad 41 is sandwiched between the lower housing 3 and the substrate 5. Frames 43 and 44 provided on the side surface of the upper housing 2 are fitted into the lower housing 3, and the lower housing 3 and the upper housing 2 are fastened and fixed to each other by fastening parts (not shown). In the conductive pad, a steel wire is buried in a mesh shape in a silicone resin.Electromagnetic noise in a frequency band equal to or less than a predetermined number determined by the mesh interval is cut off. Prevent leaks or ingress.
[0025]
An electric signal such as a data signal, a power supply, or a control signal input from a signal terminal (not shown) of the substrate 5 is input to the integrated circuits 13 and 14. The integrated circuit 13 multiplexes the input data signal and outputs a high bit rate data signal. The output high-frequency data signal is transmitted through the outer conductor line 20 and input to the transmission circuit 10. The transmission circuit 10 generates a modulated signal (LD drive current) whose amplitude has been adjusted based on the input data signal, and sends the generated signal to the light emitting element module 15. In the light emitting element module 15, the LD is caused to emit or extinguish the light based on the LD driving current, and outputs a digital optical signal whose intensity is modulated.
[0026]
The light receiving element module 17 outputs the received digital optical signal as a voltage signal (received signal). The reception signal output from the light receiving element module 17 is input to the reception circuit 12 and output as a high-frequency digital signal whose amplitude has been adjusted. This digital signal is transmitted through the outer conductor line 22 and input to the integrated circuit 14. The integrated circuit 14 extracts a clock signal and a data signal from the input signal, and outputs a low-speed clock and data signal by demultiplexing.
[0027]
In this example, the case where the LD driving current and the reception signal are transmitted as the outer layer conductor lines 20 and 22 has been described. However, the outer layer conductor lines 20 and 22 are signal lines for transmitting other control signals and power. May be provided. In this case, a plurality of signal lines passing through the gaps 38 and 39 may be provided within a range that satisfies a predetermined gap for obtaining the shielding effect. Further, another gap similar to the gaps 38 and 39 may be provided in the outer conductor pattern, and a plurality of signal lines may be provided in the gap.
[0028]
The outer layer lines 20 and 22 that pass through the gaps provided in the outer layer conductor pattern are relatively easy to route, and the degree of freedom in line design and component arrangement is improved. In addition, when the high-frequency signal transmission line is provided on the substrate, it is not necessary to provide the high-frequency signal transmission line in the inner layer using a via, and the impedance control can be easily performed.
[0029]
Furthermore, the outer layer line may be eliminated and the inner layer line alone may be used (a signal transmission line using the inner layer line will be described later in a second embodiment). Since electromagnetic waves are radiated from the outer layer line to the air, the use of the inner layer triplate line reduces the degree of freedom in designing wiring, but extremely reduces electromagnetic radiation.
[0030]
FIG. 2 is a perspective view showing the structure of the housing 1 (the upper housing 2 and the lower housing 3). In FIG. 2A, the upper housing 2 includes a first partition 50 that covers the transmission circuit 10, a second partition 51 that covers the reception circuit 12, and a third partition 52 that covers the integrated circuits 13 and 14. Provided. Each partition is partitioned by a partition plate 55 including a wall surface 56 and a wall surface 58. The first partition 50 is formed so as to be surrounded by the wall surface 56, the wall surface 60, the wall surface 61, and the wall surface 58. The second partition wall 51 is formed by being surrounded by a wall surface 56, a wall surface 59, a wall surface 62, and a wall surface 58. The third partition wall 52 is formed to be surrounded by the wall surfaces 58, 59, 60, and 65. The upper housing 2 is provided with an upper wall 66 that closes the first partition 50, the second partition 51, and the third partition 52.
In FIG. 2B, the lower housing 3 is surrounded on all sides by wall surfaces 71, 72, 73, and 74 and closed by a bottom surface 75. The lower housing 3 is provided with a partition plate 76 including a wall surface 76a and a wall surface 76b. Here, the wall surface 56 functions particularly as a shield wall between the transmission circuit 10 and the reception circuit 12. The wall surface 58 functions as a shield wall between the transmission circuit 10 and the reception circuit 12 and the integrated circuits 13 and 14. Further, the partition plate 76 functions as a shield wall for preventing the electromagnetic noise leaking from the notch 61 from entering the notch 62. However, the periphery of the light emitting element module 15 and the light receiving element module 17 is covered with a cylindrical metal member or a conductive resin member having an appropriate thickness so that the electromagnetic wave noise does not leak from the notches 61 and 62. In this case, there is no need to provide the partition plate 76. The thickness in this case is proportional to the electromagnetic quantity of interest.
The wall surface 58 is provided with a depression 501 and a depression 502.
Light through holes 601 and 602 are provided on the side surface of the housing, and an optical signal from the light emitting element module is output through the light through holes, or an optical signal is input to the light receiving element module.
[0031]
The first conductive pattern 30, the second conductive pattern 31 and the third conductive pattern 32, the fourth conductive pattern 33, and the fifth conductive pattern 34 provided on the substrate 5 are connected via a conductive pad 40. , Respectively, against the wall surfaces 56, 58, 60 and 59 of the housing 2. In addition, depressions 501 and 502 are provided on the wall surface 58. A through hole is formed by joining the wall surface 58 to the substrate 5, and the outer conductor lines 20, 22 are arranged so as to pass through the through hole.
[0032]
3A is a perspective view showing the substrate 5, FIG. 3B is a plan view of an outer layer surface 81 of the substrate, FIG. 3C is a plan view of an inner layer surface 82 of the substrate, and FIG. 3 (e) is a plan view of the inner layer surface 84 of the substrate, FIG. 3 (f) is a plan view of the inner layer surface 85 of the substrate, and FIG. 3 (g) is an outer surface of the substrate. 86 is a plan view of FIG.
[0033]
In the figure, the substrate 5 is laminated such that inner layers 82, 83, 84, 85 are arranged below the outer layer 81, and an outer layer 86 is arranged below the inner layer 85. On the outer layer surface 81, an outer layer conductor pattern 24, outer layer conductor lines 20, 22, a transmitting circuit 10, and a receiving circuit 12 are provided. The configuration of the outer layer conductor pattern 24 is as described in FIG. On the inner layer surface 82, an inner layer conductor pattern 89 and ground conductors 90 and 91 are provided. The inner conductor pattern 89 has the same shape as the outer conductor pattern 24, and conductor patterns 201, 202 having gap portions 203, 204 are provided in a part of the inner conductor pattern 89. The conductor patterns 201 and 202 are arranged at positions where the second and third conductor patterns 31 and 32 are projected, respectively. The ground conductor 90 is configured such that rectangular ground planes 902 and 903 are connected to both ends of the inner conductor line 901, respectively, and the ground planes 902 and 903 are arranged along the inner periphery of the inner conductor pattern 89. The gap 203 allows the inner conductor line 901 to pass through. The ground conductor 91 is configured by connecting rectangular ground planes 905 and 906 to both ends of the inner conductor line 904, respectively. The ground planes 905 and 906 are arranged along the inner periphery of the inner conductor pattern 89. The inner conductor layer 904 passes through the gap 204. The ground conductor 90 constitutes a microstrip line together with the conductor line 20, and forms a ground plane. The ground conductor 91 forms a microstrip line together with the conductor line 22 and forms a ground plane. The inner conductor pattern 89 is connected to the outer conductor pattern 24 by a plurality of (vertical) vias 300 juxtaposed.
[0034]
On the inner layer surface 83, an inner layer conductor pattern 101 is provided. The inner layer conductor pattern 101 includes conductor patterns 111, 112, 113, and 114. The conductor pattern 111 is connected to the conductor pattern 112 in a T-shape. The conductor pattern 113 is connected to the conductor pattern 111 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 114 is connected to the conductor pattern 111 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 111 is arranged on the projection surface of the pattern connecting the conductor patterns 31 and 32. The conductor pattern 112 is arranged on the projection surface of the conductor pattern 30. The inner conductor pattern 101 is connected to the outer conductor pattern 24 via a via 300.
[0035]
On the inner layer surface 84, an inner layer conductor pattern is provided. The inner layer conductor pattern 102 includes conductor patterns 121, 122, 123, and 124. The conductor pattern 121 is connected to the conductor pattern 122 in a T-shape. The conductor pattern 123 is connected to the conductor pattern 121 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 124 is connected to the conductor pattern 121 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 121 is arranged on the projection surface of the pattern connecting the conductor patterns 31 and 32. The conductor pattern 122 is arranged on the projection surface of the conductor pattern 30. The inner conductor pattern 102 is connected to the outer conductor pattern 24 by a via 300.
[0036]
On the inner layer surface 85, an inner layer conductor pattern 103 is provided. The inner layer conductor pattern 103 includes conductor patterns 131, 132, 133, and 134. The conductor pattern 131 is connected to the conductor pattern 132 in a T-shape. The conductor pattern 133 is connected to the conductor pattern 131 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 134 is connected to the conductor pattern 131 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 131 is arranged on the projection surface of the pattern connecting the conductor patterns 31 and 32. The conductor pattern 132 is arranged on the projection surface of the conductor pattern 30. The inner conductor pattern 103 is connected to the outer conductor pattern 24 via a via 300.
[0037]
The outer layer conductor pattern 104 is provided on the outer layer surface 86. The outer layer conductor pattern 104 includes conductor patterns 141, 142, 143, and 144. The conductor pattern 141 is connected to the conductor pattern 122 in a T-shape. The conductor pattern 143 is connected to the conductor pattern 141 in a T-shape, and is provided around the edge of the inner layer of the substrate. The conductor pattern 144 is connected to the conductor pattern 141 in a T-shape, and is provided on the peripheral edge of the inner layer of the substrate. The conductor pattern 141 is arranged on the projection surface of the pattern connecting the conductor patterns 31 and 32. The conductor pattern 142 is arranged on the projection surface of the conductor pattern 30. The outer conductor pattern 104 is connected to the outer conductor pattern 24 via a via 300. The outer conductor pattern 104 contacts the partition plate 76 of the lower housing 3.
[0038]
Here, the ground conductor 90 and the ground conductor 91 are electrically insulated from each other, and are also electrically insulated from the outer conductor pattern 33 connected to the inner conductor pattern 89. Therefore, the reference potentials used in the transmission circuit 10 and the reception circuit 12 are separated, so that the transmission reference potential and the reception reference potential can be configured separately. Further, the potential fluctuation does not propagate to the ground conductor 90 and the ground conductor 91 via the outer conductor pattern 33 grounded to the housing 2, so that external noise input through the housing is not transmitted to the transmission circuit or the reception circuit. There is no fluctuation of the ground potential of the circuit.
[0039]
As described above, the outer conductor pattern and the inner conductor pattern are connected by the plurality of juxtaposed vias 300, and the vias 300 are arranged at predetermined intervals. Here, the shielding effect due to juxtaposition of the vias 300 will be described.
[0040]
FIG. 4A is an enlarged perspective view showing a vertical via according to the first embodiment, and FIG. 4B is a cross-sectional view.
In the figure, an outer conductor pattern 33 provided on an outer surface 81 and an inner conductor pattern 82 provided on an inner surface 82 are connected by vias 300 arranged in a vertical direction between the patterns. At this time, in FIG. 4C, the distance d between vias when the line width of each of the outer conductor pattern 33 and the inner conductor pattern 82 is L, the wavelength λ of the frequency requiring shielding, and the cutoff wavelength λc are shown. A relational expression (Expression 1) and a relational expression (Expression 2) between the line width L and the shield shielding amount A are shown.
[0041]
Here, in FIG. 5, the line width of the outer layer conductor pattern 33 and the inner layer conductor pattern 82 is L = 1 mm, the cutoff frequency fc of the frequency requiring shielding is 15 [GHz], and the relative permittivity of the substrate is 3.6. The relationship between the via spacing d and the shield shielding amount P in the case of performing the above is shown.
[0042]
As shown in the drawing, if the vias are formed at intervals smaller than 1/2 of the wavelength λ of the frequency requiring the shield, the juxtaposed vias exhibit the shielding effect. If the interval is longer than that, the shield shielding amount becomes 0 [dB], and the effect as a shield is lost. Further, as the interval between the vias is made smaller than λ / 2 and the interval is reduced, the shield shielding amount increases. Preferably, the interval between the vias is set to λ / 4. As a result, a shielding effect of about 10 dB can be obtained (that is, a plurality of vias juxtaposed at a predetermined interval acts as an electromagnetic shield wall). Further, when the via interval becomes λ / 8, the shielding effect sharply increases, and a shielding effect of as much as 20 dB can be obtained. Therefore, it is more preferable to set the via interval to λ / 8 or less.
[0043]
Here, the outer conductor lines 20 and 22 cross the gaps 38 and 39 provided in the outer conductor pattern. The gaps 38 and 39 have an appropriate width, and two conductors are arranged to face each other. The width of the gap may be less than １ ／, more preferably の or less, of the wavelength λ of the frequency requiring shielding. In addition, it is necessary to provide depressions 501 and 502 for passing wiring on the wall surface of the housing, and the width of this notch is also less than 1/2 of the wavelength λ of the frequency requiring shielding, and more preferably 1 / It is better to be 8 or less. Further, the diameter of each of the light through holes 601 and 602 provided on the side surface of the housing is preferably less than １ ／, more preferably の or less of the wavelength λ of the frequency that requires shielding.
[0044]
As a result, since the outer conductor patterns 31 and 32 and the vias 300 are provided on the substrate 5, the electromagnetic noise radiated from the oscillators and amplifiers constituting the transmission circuit 10 and the reception circuit 12 passes through the transmission circuit 10 through the inner layer of the substrate 5. No electromagnetic interference occurs between the receiver 10 and the receiving circuit 12. In addition, since the conductive pad is provided, this electromagnetic wave noise does not leak from the joint surface between the housing 2 and the substrate 5. Further, since the wall surfaces 56 and 58 are provided, it is possible to shield electromagnetic noise that propagates through the space between the substrate 5 and the inner wall of the upper housing 2.
[0045]
As described above, by providing the outer-layer shield pattern, the inner-layer shield pattern, the housing and the shield wall of each layer, the conductive pad, and the via with the optimized spacing, an electromagnetic wave shield having a desired shielding effect can be formed. .
[0046]
In addition, this makes it possible to prevent electromagnetic interference between the two circuits even if the transmitting circuit and the receiving circuit are arranged in parallel on the same substrate surface. Therefore, it is possible to arrange the transmitting circuit and the receiving circuit in parallel on the same surface at the shortest interval.
[0047]
Here, as a comparative example, FIG. 6 shows a shield structure in which a slit is provided on the substrate surface.
In the figure, a casing 601 is in contact with the upper surface of a substrate 600. The housing 601 has two partition walls 603 and 604 separated from each other. Further, a shield wall 605 is provided to shield another space 607 in the housing. The transmission circuit 10 and the reception circuit 12 are arranged on the substrate 600. The transmission circuit 10 and the reception circuit 12 are housed and shielded in partition walls 603 and 604, respectively. Further, the substrate 600 is provided with a slit 604, and a partition plate (shield wall) for the partition walls 603 and 604 is provided in the slit 604. A cutout 608 is formed on the upper surface of the substrate 600 at a position facing the transmission circuit 10 and the reception circuit 12. The shield wall 605 has a protrusion at the lower end, and the protrusion fits into the cut hole 608 and is soldered. This is the same as the joint structure of the leg 7 and the through hole 6 described in FIG.
[0048]
In the comparative example of FIG. 6 configured as described above, there is a possibility that a gap may be formed in the joint surface between the housing 601 and the substrate 600, and there is a concern that electromagnetic wave noise leaks from this gap. Also, the mounting space and the wiring space are reduced by the provision of the cut holes. In addition, there is a possibility that electromagnetic noise leaks through the cutout portion and the inner layer of the substrate.
[0049]
As described above, in the example shown in FIG. 6, even if the transmitting circuit and the receiving circuit are mounted on the same board, the transmitting circuit and the receiving circuit are not shielded in a completely isolated state, so that the radiation from the transmitter is not performed. It is conceivable that the electromagnetic wave noise to be transmitted enters the receiver through the inner layer of the dielectric substrate and enters the receiver, and there has been a concern about the influence of the electromagnetic wave noise leaking into the inner layer of the dielectric substrate.
[0050]
However, in the invention according to the first embodiment, different semiconductor components are formed on the outer layer of the substrate in contact with the housing, and the outer semiconductor patterns are separated from each other on the upper surface of the substrate. By performing signal transmission by providing a gap in a part of the semiconductor device, there is an effect that electromagnetic interference between semiconductor components mounted on the same substrate surface can be suppressed.
[0051]
Embodiment 2 FIG.
FIG. 7 is a perspective view showing a configuration of a semiconductor device according to a second embodiment of the present invention. In the figure, an end surface of a wall surface of a housing 502 is joined to an upper surface of a substrate 501. A semiconductor component 503 is mounted on the substrate 501. The housing 502 is provided with a shielding partition 504 for housing the semiconductor component 503 inside. The conductive pad 505 is held between the substrate 501 and the housing 502, and the joint surface is electromagnetically shielded. A signal via 510 is provided on the substrate 501, and the via 510 is connected to the semiconductor component 503. The semiconductor component 503 is connected to the conductor line 512 via the signal via 510. An outer conductor pattern 515 is formed on the substrate 501 so as to surround the semiconductor component 503.
[0052]
FIG. 8 is a diagram illustrating a stacked structure of a substrate 501 of a semiconductor device.
In the drawing, a substrate 501 has an outer layer surface 551, one side of which is arranged at an edge of the substrate, and an outer layer conductor pattern formed of a conductor line, which is formed of a rectangle by the one side and the other three sides shorter than this. 515 are provided. The semiconductor component 503 is mounted inside the outer conductor pattern 515. The semiconductor component 503 is connected to the conductor line 511. The conductor line 511 is connected to the signal via 510. Outside the region surrounded on all sides by the outer conductor pattern 515, another semiconductor component (not shown) is arranged.
[0053]
An inner conductor pattern 516 is provided on the inner surface 552. The inner conductor pattern 516 has the same shape as the outer conductor pattern 515 except that a part of the inner conductor pattern 516 has a gap. The outer layer conductor pattern 515 is connected to the inner layer conductor pattern 516 by a plurality of juxtaposed vias 520. The inner conductor pattern 516 has a gap partially. A connection line 518 of the inner conductor surface 517 is provided passing through the gap. The inner conductor surface 517 has a ground plane at each end of the connection line 518. A hollow 700 is formed in the inner conductor surface 517, and a signal via 510 is arranged in the hollow.
[0054]
The inner layer surface 553 is provided with an inner layer conductor pattern 530 partially having a gap. The inner layer conductor pattern 530 has the same shape as the inner layer conductor pattern 516. A signal via 510 is arranged in the inner conductor pattern 530. One end of the signal via 510 is connected to the inner conductor line 512, and the other end of the signal via 510 passes through a gap between the inner conductor patterns 530 and communicates with a region surrounded by the inner conductor pattern 530. The inner conductor pattern 530 is connected to the inner conductor pattern 516 by a via 520.
[0055]
The inner layer surface 554 is provided with an inner layer conductor pattern 531 partially having a gap, and has a connection line 559 having the same shape as the inner layer conductor pattern 516 and passing through the gap. The inner conductor surface 519 is provided with ground planes connected to both ends of the connection line 559, respectively. The inner conductor pattern 531 is connected to the inner conductor pattern 530 by a via 520.
[0056]
An outer conductor surface 555 is provided with an inner conductor pattern 540 and is connected to the inner conductor pattern 531 by a via 520. Thereby, semiconductor component 503 arranged in inner layer conductive pattern 540 is connected to another semiconductor component.
[0057]
According to this embodiment, the inner layer line is provided so as to pass through the gap provided in the inner layer conductor pattern. This makes it possible to perform signal transmission through the inner layer while preventing electromagnetic interference between the semiconductor component and another semiconductor component via the inner layer of the substrate. In this case, connection with other semiconductor components is made using the same transmission path as the signal via 510 and the inner layer conductor line 512 described above.
[0058]
【The invention's effect】
According to this invention, different semiconductor components are formed on the outer layer of the substrate in contact with the housing, and the outer layer conductive patterns are separated from each other on the upper surface of the substrate, connected to the inner layer conductive pattern by vias, and a gap is formed in a part of the outer layer conductive pattern. By providing the signal transmission, the electromagnetic interference between the semiconductor components mounted on the same substrate surface can be suppressed.
[0059]
In addition, a gap is provided in a part of the inner conductor pattern, and a connection portion for connecting the ground plane is passed through the gap to insulate the ground plane from the outer conductor pattern. The potential of the ground plane of the component can be kept from fluctuating.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a configuration of an optical transceiver according to Embodiment 1 of the present invention.
FIG. 2 is a perspective view showing a structure of a housing according to the first embodiment of the present invention.
FIG. 3 is a perspective view showing a substrate according to the first embodiment of the present invention.
FIG. 4 is an enlarged perspective view showing a vertical via according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a relationship between a via interval and a shield shielding amount according to the first embodiment of the present invention;
FIG. 6 is a diagram showing a shield structure of a comparative example in which a slit is provided on a substrate.
FIG. 7 is a perspective view showing a configuration of the semiconductor device according to the first embodiment of the present invention;
FIG. 8 is a diagram showing a laminated structure of a substrate of the semiconductor device according to the first embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 housing | casing, 2 upper housing | casing, 3 lower housing | casings, 5 board | substrates, 10 transmission circuits, 12 reception circuits, 24 outer layer conductor patterns, 20, 22 outer layer conductor lines, 40, 41 conductive pads, 55, 76 partition plate, 90 , 91 ground conductor, 300 via, 510 signal via, 512 inner layer conductor line, 516 inner layer conductor pattern, 517 inner layer conductor surface.

Claims (11)

An outer layer conductor pattern provided on an outer layer of the substrate and having at least a part thereof formed with a gap that forms a gap, an inner layer conductor pattern provided on an inner layer of the substrate, a via connecting the outer layer conductor pattern and the inner layer conductor pattern, and a substrate Having an outer conductor line provided in the outer layer and passing through the gap of the outer conductor pattern, a multilayer substrate formed by laminating dielectrics,
A first semiconductor component that is mounted on the outer layer of the substrate around the periphery of the outer layer conductor pattern and connected to one end of the outer layer conductor line;
A second semiconductor component mounted on the outer layer of the substrate with a part of the outer conductor pattern surrounding the first semiconductor component interposed therebetween, together with the first semiconductor component, and connected to the other end of the outer layer conductor line; ,
A housing provided with a wall surface forming an opening, an end surface of the wall surface abutting on the outer conductor pattern, and housing the first semiconductor component;
A semiconductor device comprising: The interval of the gap in the gap is less than half the signal wavelength of the outer layer conductor line,
2. The semiconductor device according to claim 1, wherein a gap between the vias is less than half a signal wavelength of the outer conductor line. 3. 3. The semiconductor device according to claim 2, wherein an interval between the gaps in the gap is equal to or less than a quarter of a signal wavelength of the outer conductor line. 4. The multilayer substrate according to claim 1, wherein a gap is formed at least partially in the inner conductor pattern to form a gap, and the inner conductor line is disposed in the gap. 3. The semiconductor device according to claim 1. The inner-layer conductor line forms a ground conductor line of the outer-layer conductor line, and both ends of the inner-layer conductor line are respectively connected to first and second ground conductor surfaces forming a ground plane,
5. The semiconductor device according to claim 4, wherein said first and second ground conductor surfaces are arranged in non-contact with said inner layer conductor pattern. The outer conductor pattern is arranged so as to surround the second semiconductor component, and an end surface of the housing wall contacts the outer conductor pattern surrounding the second semiconductor component to accommodate the second semiconductor component. The semiconductor device according to claim 1, wherein: The semiconductor device according to claim 1, wherein an end surface of the wall surface of the housing is joined to the outer layer conductor pattern with a conductive pad interposed therebetween. The semiconductor device according to claim 1, wherein the first and second semiconductor components are connected to the inner conductor line via a via. The casing wall has a depression in a part of a joint surface with the outer conductor pattern, and is arranged such that the outer conductor line passes through a through hole formed by joining the depression and the multilayer substrate. The semiconductor device according to claim 1, wherein: An outer conductor pattern provided on the outer layer of the substrate, a first inner layer conductor pattern provided on the first inner layer of the substrate and having at least a part thereof formed with a gap that forms a gap, and provided on the second inner layer of the substrate; A second inner conductor pattern in which a gap is formed at least partially apart from the first inner layer conductor pattern on the first inner surface of the substrate to form a hollow; Inner ground plane, vias connecting the outer conductor pattern to the first and second inner conductor patterns, outer conductor lines provided on the outer layer of the substrate, and gaps between the inner conductor patterns provided on the second inner layer of the substrate An inner layer conductor line passing through the inner portion, and a signal via connecting one end of the outer layer conductor line and one end of the inner layer conductor line while passing through a hollow hole of the inner layer ground plane, and a dielectric is laminated. hand And the multi-layer substrate has been made,
A semiconductor component mounted on the substrate outer layer surrounded by the outer layer conductor pattern and connected to the other end of the outer layer conductor line;
A semiconductor device comprising: A first pattern, a second pattern in which a first gap portion that forms a gap is formed partially, and a third pattern in which a second gap portion that forms a gap is formed partially. Is connected to the outer layer conductor pattern provided on the outer layer of the substrate,
An inner layer conductor pattern provided on the inner layer of the substrate,
A via connecting the outer conductor pattern and the inner conductor pattern,
And a first and second outer conductor lines provided on the outer layer of the substrate and passing through the first and second gaps of the outer conductor pattern, respectively, and a multilayer substrate formed by laminating dielectrics,
A transmitting circuit mounted on the outer layer of the substrate, surrounded by the first and second patterns of the outer layer conductor pattern, and connected to one end of the first outer layer conductor line;
The transmission circuit includes a part of the first pattern of the outer conductor pattern sandwiched between the first and third patterns of the outer conductor pattern, is placed on the outer layer of the substrate, and is placed on the outer layer of the substrate. A receiving circuit connected to one end of the conductor line,
The transmission circuit is mounted on the outer layer of the substrate with a part of the second pattern of the outer layer conductor pattern sandwiched therebetween, and the reception circuit is mounted on the outer layer of the substrate with a part of the third pattern of the outer layer conductor pattern sandwiched therebetween. A semiconductor component connected to the other end of the second outer layer conductor line;
A first partition wall forming an opening, a wall surface having a second partition wall is provided, and an end face of the wall surface contacts the outer layer conductor pattern, and the transmission circuit is accommodated in the first partition wall. A housing for housing the receiving circuit in a second partition;
An optical transceiver equipped with.

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