JP2004296943A - Fabricating method of ic wafer, and flip-chip ic using the ic wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fabricating method of an IC wafer and a flip-chip IC using the IC wafer, enabling the easy printing of print paste in each IC chip area relatively accurately on a barrier metal layer. <P>SOLUTION: In the IC wafer having a multiplicity of IC chip areas on an upper surface and a plurality of barrier metal layers 3 in each IC chip area, when a printing mask having apertures corresponding to the barrier metal layers 3 disposed on the IC wafer, adjustment marks 5 for recognizing a position deviation amount between the apertures and the barrier metal layers are formed in the entire IC chip areas. Further, the flip-chip IC is fabricated by a process for adjusting the position relation between the IC wafer and the printing mask, according to the position deviation amount between the apertures and the barrier metal layers in each IC chip area, recognized by each adjustment mark, when positioning to the IC wafer a printing mask having a plurality of apertures corresponding to the barrier metal layers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an IC wafer provided with a plurality of barrier metal layers to which a printing paste is applied, and a method for manufacturing a flip-chip IC using the IC wafer.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, ICs are face-down bonded to the upper surface of a circuit board having circuit wiring, that is, the IC is mounted on the circuit board with the circuit forming surface of the IC facing the circuit board. ing.
[0003]
An IC used for such face-down bonding is called a flip-chip type IC, and its terminal is generally connected to circuit wiring on a circuit board via solder.
[0004]
As such a conventional flip-chip type IC, for example, a circuit pattern made of Al or a semiconductor element (not shown) is attached on the upper surface of a silicon substrate on which an insulating film (not shown) is attached, and Ni is placed on the circuit pattern. Structure in which a plurality of barrier metal layers made of a metal layer and an Au layer are applied, and a passivation layer made of silicon nitride or the like is applied to a region where no barrier metal layer is formed, and a substantially spherical solder bump is formed on the barrier metal layer. When such a flip-chip type IC is mounted on a circuit board, the flip-chip type IC is mounted such that the solder bumps of the flip-chip type IC face the corresponding circuit wiring on the circuit board. The flip-chip barrier metal is placed on a circuit board and then heated and melted at a high temperature. There is soldered to the circuit wiring on the circuit board.
[0005]
The solder bump provided on the flip-chip type IC is usually formed by the following method. That is,
(1) An IC wafer in which a large number of IC chip areas are formed on an upper surface, and a semiconductor element and a plurality of barrier metal layers (not shown) are provided in each of the IC chip areas, and a print mask having openings corresponding to the barrier metal layers And prepare
(2) Next, disposing the print mask on the IC wafer such that the opening thereof is located directly above the barrier metal layer on the IC wafer;
(3) Next, after supplying the solder paste on the print mask, the supplied solder paste is printed and applied on the barrier metal layer through the opening,
(4) Finally, a substantially spherical solder bump is formed on the barrier metal layer by reflowing the solder paste applied on the barrier metal layer.
[0006]
In order to accurately form solder bumps on the barrier metal layer by such a method, it is necessary to align the print mask with the IC wafer with high precision. An alignment mark for aligning the print mask is provided thereon, and an alignment hole corresponding to the alignment mark is provided in the print mask, and the IC wafer and the print mask are aligned with reference to the alignment mark and the alignment hole. Like that.
[0007]
In general, as shown in FIG. 5, the number of the alignment marks provided is significantly smaller than the number of IC chip regions on one IC wafer, for example, one to three alignment marks are provided. 1).
[0008]
[Patent Document 1]
JP-A-11-274206
[Problems to be solved by the invention]
However, since the above-described print mask has distortions and the like due to manufacturing variations and the like, even if the alignment holes of the print mask are aligned with the alignment marks 15 provided on the IC wafer, the print mask does not Is not necessarily located on the barrier metal layer 13, and there may be a region where the positional relationship between the two greatly shifts. In such a case, in a region where the displacement between the opening of the print mask and the barrier metal layer 13 is large, a problem occurs that the printed portion of the solder paste deviates from a desired position, and the solder paste must be reprinted. There is a problem that the productivity of the mold IC is significantly reduced.
[0010]
SUMMARY OF THE INVENTION The present invention has been devised in view of the above problems, and has as its object to provide an IC wafer and a flip using the same, which make it possible to relatively accurately print a printing paste on a barrier metal layer in each IC chip area. An object of the present invention is to provide a method of manufacturing a chip-type IC.
[0011]
[Means for Solving the Problems]
The IC wafer according to the present invention has an IC wafer in which a large number of IC chip regions are formed on an upper surface and a plurality of barrier metal layers are provided in each IC chip region. An adjustment mark for recognizing the amount of displacement between the barrier metal layer and the opening when the IC chip is provided on the IC wafer is provided in a plurality of IC chip areas.
[0012]
Further, in the IC wafer according to the present invention, the adjustment mark has a scale.
[0013]
Further, the IC wafer according to the present invention is characterized in that the barrier metal layer is also used as the adjustment mark.
[0014]
Still further, the method of manufacturing a flip-chip type IC according to the present invention is characterized in that, when the print mask having a plurality of openings corresponding to the barrier metal layer is aligned with the above-mentioned IC wafer, each IC chip recognized by the adjustment mark is aligned. The method includes a step of adjusting a positional relationship between the IC wafer and the print mask based on a positional shift amount between the barrier metal layer and the opening in the region.
[0015]
Furthermore, in the method of manufacturing a flip-chip type IC according to the present invention, the positional relationship between the IC wafer and the print mask is adjusted so that the amount of displacement between the barrier metal layer and the opening in each IC chip area is equal to or less than a predetermined reference value. The method of manufacturing a flip-chip type IC according to claim 4, wherein
[0016]
Still further, in the flip chip type IC manufacturing method according to the present invention, the reference value is set to 5% to 50% of a diameter of the barrier metal layer having a circular upper surface. A plurality of IC chip regions are formed on the upper surface, and a plurality of barrier metal layers are provided in each IC chip region. In the IC wafer, a print mask having an opening corresponding to the barrier metal layer is formed on the IC wafer. At the time of disposition, adjustment marks for recognizing the amount of displacement between the barrier metal layer and the opening are provided in a plurality of IC chip areas. Even if the amount of positional deviation greatly differs for each IC chip area, the amount of positional deviation can be grasped in a plurality of IC chip areas. Accordingly, it is possible to adjust the amount of displacement between the barrier metal layer and the opening of the print mask in a plurality of IC chip areas so as to be equal to or less than a predetermined reference value. It can be applied, effectively preventing reprinting and improving the productivity of flip-chip ICs. In this case, when the upper surface of the barrier metal layer has a circular shape, the reference value is preferably set to 5% to 50% of its diameter.
[0017]
Further, according to the present invention, since the scale is provided on the adjustment mark, it is extremely easy to ascertain the amount of misalignment between the print mask and the IC wafer, thereby also improving the productivity of the flip-chip type IC. be able to.
[0018]
Further, according to the present invention, by using the barrier metal layer of the IC wafer also as the adjustment mark, the solder paste applied on the adjustment mark is not wasted, and the use amount of the solder paste can be reduced. is there.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
[0020]
FIG. 1 is a plan view of an IC wafer according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of a main part of the IC wafer shown in FIG. 1, and the IC wafer shown in FIG. Has a structure in which a circuit pattern 2, a barrier metal layer 3, a passivation layer 4, an adjustment mark 5, an alignment mark X, and the like are provided on the upper surface.
[0021]
The semiconductor substrate 1 is formed in a substantially circular shape from a single crystal semiconductor such as single crystal silicon having an insulating film made of an insulating material such as SiO _{2 on} the surface, and a large number of IC chip regions are formed on the upper surface thereof. I have.
[0022]
The semiconductor substrate 1 is provided with a semiconductor element (not shown), a circuit pattern 2, a barrier metal layer 3, and a passivation layer 4 in each IC chip region on the upper surface thereof, and functions as a supporting base material for supporting them. In the case where such a semiconductor substrate 1 is made of the above-described single crystal silicon, for example, an ingot made of single crystal silicon is formed by adopting a conventionally known Czochralski method (pulling method), and This is sliced into a plate shape using a diamond cutter or the like, and the surface is polished to obtain a plate having a predetermined thickness. Thereafter, a conventionally known thermal oxidation method or the like is applied to the plate, It is manufactured by oxidizing the plate body surface to a predetermined depth region (1.5 μm to 4.5 μm) from the surface.
[0023]
The circuit pattern 2 attached to each IC chip area of the semiconductor substrate 1 is formed in a predetermined pattern from a metal material such as Al or Cu. The circuit pattern 2 is applied to a semiconductor element (not shown) from an external power supply. It functions as a power supply wiring for supplying electric power and electric signals.
[0024]
Such a circuit pattern 2 is formed to a predetermined thickness (0.5 μm to 1.5 μm) by employing a conventionally known thin film forming technique, specifically, sputtering, photolithography, etching, or the like. You.
[0025]
Further, the barrier metal layer 3 provided on the circuit pattern 2 has, for example, a three-layer structure in which zinc (Zn), nickel (Ni), and gold (Au) are sequentially stacked from the semiconductor substrate 1 side.
[0026]
When the flip-chip type IC obtained by processing the IC wafer according to the present invention is mounted on a circuit board, when the solder bumps provided on the barrier metal layer 3 are melted, The effect of effectively preventing "erosion" of the aluminum or the like forming the circuit pattern 2 due to the solder formed is provided.
[0027]
Such a barrier metal layer 3 is formed on a circuit pattern 2 exposed in an opening of the passivation layer 4, that is, in a region where the passivation layer 4 does not exist, after a passivation layer 4 described later is formed. By adopting plating or the like and sequentially depositing Zn, Ni, and Au, the whole is formed to have a substantially columnar shape.
[0028]
Of the three layers constituting the barrier metal layer 3, the lowermost Zn layer is formed by subjecting a part of the Ni layer to a substitution reaction when the Ni layer is formed by conventionally known electroless plating or the like. The thickness is set to 0.01 μm to 0.05 μm, and the Ni layer serving as the intermediate layer is used to improve the wettability of the solder to the barrier metal layer 3. The thickness is set to 0.5 μm to 7.0 μm, and the Au layer serving as the uppermost layer is for effectively preventing oxidative corrosion of the Ni layer, and the thickness is set to 0.02 μm to 0.1 μm. An alignment mark X is provided in a region outside the IC chip region of the semiconductor substrate 1 (a formation region of a dummy IC or a TEG (test element group) IC). The IC chip area of Te adjustment marks 5 are provided by at least one.
[0029]
The alignment mark X is made of the same metal material as that of the circuit pattern 2 such as Al or Cu. When a print mask is provided on an IC wafer to print and apply a solder paste on the barrier metal layer 3, the alignment mark X is used for both. Functions as a mark for high-accuracy alignment.
[0030]
The adjustment mark 5 is made of the same metal material as the circuit pattern 2 such as Al or Cu, and has a substantially square mark main body, and a constant interval (1 μm to 10 μm) extending outward from the mark main body. It is composed of attached scale parts.
[0031]
Such an adjustment mark 5 is for recognizing a positional shift between the barrier metal layer 3 and an opening of a print mask described later in each IC chip area when the print mask is aligned based on the alignment mark X. The distance between the center position of the mark body and the center position of the opening of the print mask is easily recognized by the scale portion as the amount of displacement between the print mask and the IC wafer in each IC chip area.
[0032]
The adjustment mark 5 and the alignment mark X can be formed at the same time as the circuit pattern 2 by adopting a method similar to that of the circuit pattern 2 described above, that is, a thin film forming technique such as sputtering, photolithography, and etching. It is formed to a thickness of 5 μm to 1.5 μm.
[0033]
A passivation layer 4 is applied to a region of the upper surface of the semiconductor substrate 1 where the barrier metal layer 3 is not formed, and the circuit pattern 2, the adjustment mark 5, and the alignment mark X are shared by the passivation layer 4. Coated.
[0034]
The passivation layer 4 is formed of an electrically insulating material having an excellent sealing property such as silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ). By properly shielding the marks 5 from the atmosphere, the marks 5 can be effectively prevented from being corroded by contact with moisture or the like contained in the atmosphere.
[0035]
Such a passivation layer 4 is formed by applying the above-mentioned electrically insulating material to the semiconductor substrate 1 on which the circuit pattern 2 and the like are provided by employing a conventionally known thin film forming technique, for example, a CVD method or a sputtering method. The barrier metal layer 3 is formed by forming a thickness of 5 μm to 1.5 μm and then processing it into a predetermined pattern by a conventionally known photolithography and etching technique, etc., and providing an opening at a position where the barrier metal layer 3 is formed.
[0036]
Next, a method of manufacturing a flip-chip type IC using the above-described IC wafer will be described in detail with reference to FIG. FIG. 3 is a cross-sectional view of each step for explaining a method for manufacturing a flip-chip type IC using the IC wafer of FIG. 1, wherein 6 is a metal sheet, 7 is an opening, 8 is an adjustment hole, and 9 'is a paste. 9a and 9b are solder bumps as bumps.
[0037]
(1) First, the above-described IC wafer W and print mask M are prepared (see FIG. 3A).
[0038]
The printing mask M is formed by forming an opening 7 corresponding to the barrier metal layer 3 and an adjusting hole 8 corresponding to the adjustment mark 5 in a metal sheet 6 formed in a plate shape from a metal material such as an aluminum alloy or a Ni alloy. And a structure in which an alignment hole corresponding to the alignment mark X is formed. When the print mask M is made of a Ni alloy, the print mask M is manufactured by employing, for example, a conventionally known additive method.
[0039]
(2) Next, a print mask M is provided on the IC wafer W, and the two are aligned (see FIG. 3B).
[0040]
In order to dispose the print mask M on the IC wafer W, for example, the IC wafer W is placed and fixed on the stage of a screen printing machine on which the print mask M is disposed, and the print mask M is placed on the alignment mark X of the IC wafer W. Is performed by moving the stage so that the alignment hole of the print mask M is positioned.
[0041]
(3) Next, the amount of misalignment between the adjustment mark 5 of the IC wafer W and the adjustment hole 8 of the print mask M is measured for each IC chip area, and the amount of misalignment is equal to or less than a predetermined reference value. Next, the positional relationship between the print mask M and the IC wafer W is adjusted.
[0042]
At this time, if at least one of the positional deviation amounts in each IC chip area is larger than a predetermined reference value (for example, a value of 5% to 50% of the diameter of the upper surface of the barrier metal layer), the stage is moved and the IC wafer W The position is varied, and the positions are adjusted so that the amount of displacement is equal to or less than the reference value in all the IC chip areas.
[0043]
Therefore, even if the amount of displacement between the opening 7 of the print mask M and the barrier metal layer 3 of the IC wafer W greatly differs for each IC chip region due to the distortion generated in the print mask M, all ICs In the chip region, the amount of displacement between the barrier metal layer 3 and the opening 7 of the print mask M can be reduced, and the solder paste 9 'to be printed in a later step can be relatively accurately applied to a desired location. It becomes. As a result, reprinting can be effectively prevented, and the productivity of the flip-chip type IC can be improved.
[0044]
In addition, since the adjustment mark 5 is provided with a scale, it is extremely easy to grasp the amount of misalignment between the print mask M and the IC wafer W, thereby also improving the productivity of the flip-chip type IC. Can be.
[0045]
In addition, since the adjustment mark 5 has a shape in a plan view different from that of the barrier metal layer 3, the adjustment mark 5 is more easily recognized at the time of alignment, whereby the adjustment mark 5 can be connected to the barrier metal layer 3. It is possible to effectively prevent a trouble such as a mistake.
[0046]
(3) Next, a solder paste 9 'is prepared, and the solder paste 9' is supplied onto the print mask M.
[0047]
As the solder paste 9 ', one obtained by adding and mixing a rosin-based flux to a large number of solder particles and adjusting the viscosity to a predetermined viscosity is suitably used.
[0048]
(4) Next, the solder paste 9 ′ on the print mask M is moved in a predetermined direction while pressing the squeegee toward the IC mask M, so that the solder paste 9 ′ is formed in the opening 7 of the print mask M and the adjustment hole. Printing and application are performed on the barrier metal layer 3 and the adjustment mark 5 through the reference numeral 8 (see FIG. 3C).
[0049]
(5) Next, by reflowing the applied solder paste 9 ', the solder particles contained in the solder paste 9' are melted to bond the solder particles to each other, and this is cooled as it is. The solder bumps 9a and 9b are formed on the barrier metal layer 3 and the adjustment mark 5 (see FIG. 3D).
[0050]
At this time, although the solder bumps 9 a on the barrier metal layer 3 are firmly adhered to the barrier metal layer 3 by the action of the Ni layer forming the barrier metal layer 3, unnecessary solder bumps 9 a Since 9b is formed on the adjustment mark 5 via the passivation layer 4 having poor solder wettability, the adhesive force of the solder bump 9b to the passivation layer 4 can be significantly reduced. Therefore, the solder bumps 9b on the adjustment marks 5 are in a state of being attached to the IC wafer W with extremely low strength by the action of the flux (not shown) attached to the solder bumps themselves.
[0051]
The reflow of the solder paste 9 'is performed at a temperature of, for example, 230C to 260C.
[0052]
(6) Next, the solder bumps 9b on the adjustment marks 5 are removed by cleaning the flux attached to the solder bumps 9a and 9b (see FIG. 3E).
[0053]
Such cleaning of the flux is performed by oscillating the IC wafer up and down in a state where the IC wafer is immersed in a semi-aqueous solvent, whereby the flux residue attached to the bumps is washed away. Therefore, the unnecessary solder bumps 9b that have been deposited on the adjustment mark 5 by the action of the flux are significantly removed from the adjustment mark 5 by the flux cleaning, the adhesion to the passivation layer 4 is greatly reduced. Become. This eliminates the need to individually remove unnecessary solder bumps 9b with a semiconductor sucking device or the like, thereby simplifying the manufacturing process of the flip-chip IC and improving the productivity of the flip-chip IC. It becomes.
[0054]
(7) Finally, by cutting and processing the IC wafer W for each IC chip area using a diamond saw or the like, a large number of flip-chip type ICs can be obtained.
[0055]
When the obtained flip-chip type IC is mounted on a circuit board, the flip-chip type IC is mounted on the circuit board such that the solder bumps of the flip-chip type IC face the corresponding circuit wiring on the circuit board. Then, the barrier metal layer of the flip chip is soldered to the circuit wiring on the circuit board by heating and melting the solder bump at a high temperature.
[0056]
The present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.
[0057]
For example, in the above-described embodiment, as shown in FIG. 4, if the barrier metal layer 3 is also used as the adjustment mark 5, the opening of the IC wafer can also be used as the adjustment hole. There is also an advantage that the solder paste 9 'applied to the substrate is not wasted and the amount of the solder paste 9' used can be reduced.
[0058]
In this case, since the barrier metal layer 3 functioning as the adjustment mark 5 itself functions as the mark body according to the above-described embodiment, the above-described scale portion is provided around the barrier metal layer 3. And is distinguished from other barrier metal layers.
[0059]
In the above-described embodiment, a “metal mask” having a plurality of openings in the metal sheet 6 is used as a print mask. However, instead of this, various resin materials such as a polyimide resin, a polyester resin, and a polyethylene resin are used. The present invention is applicable to a mask made of.
[0060]
Further, in the above-described embodiment, the solder bumps 9a are formed using the solder paste 9 ', but instead, silver bumps or other conductive bumps may be formed using another conductive paste such as a silver paste. It may be formed.
[0061]
Further, in the above-described embodiment, the barrier metal layer 3 has a three-layer structure of Zn, Ni, and Au. Alternatively, the barrier metal layer 3 may have a two-layer structure. For example, a structure in which Ni and Au are sequentially stacked is considered as an example.
[0062]
Furthermore, in the above-described embodiment, the mark body of the adjustment mark 5 is formed in a square shape, but may be formed in various shapes such as a triangular shape, a circular shape, and a cross shape instead. On the other hand, the scale portion of the adjustment mark 5 is also provided in four directions, but may be in any direction as long as it has two or more directions.
[0063]
Further, in the above-described embodiment, the adjustment mark 5 and the alignment mark X are formed of a metal material. Alternatively, a hole formed by etching a metal layer in which a metal material is laminated is adjusted. It can also be used as a mark or alignment mark.
[0064]
Furthermore, in the above embodiment, the adjustment marks 5 are provided in all the IC chip areas. However, the adjustment marks are provided in a plurality of IC chip areas so that the adjustment marks are dispersed throughout the IC chip area of the IC wafer. Specifically, adjustment marks may be provided for IC chip areas that are 30% or more of the total number of IC chip areas, and these adjustment marks may be dispersed throughout the IC chip area. good.
[0065]
【The invention's effect】
According to the present invention, in an IC wafer in which a large number of IC chip regions are formed on an upper surface and a plurality of barrier metal layers are provided in each IC chip region, an opening corresponding to the barrier metal layer is formed in the IC wafer. When a print mask having a mask is provided, an adjustment mark for recognizing the amount of displacement between the barrier metal layer and the opening is provided in a plurality of IC chip areas. Even when the amount of displacement between the metal layer and the opening differs greatly from one IC chip region to another, these displacements can be grasped in a plurality of IC chip regions. Therefore, it is possible to adjust the amount of misalignment between the barrier metal layer and the opening of the print mask in a plurality of IC chip areas so as to be equal to or less than a predetermined reference value, and to print the solder paste at a desired location relatively accurately. It can be applied, effectively preventing reprinting and improving the productivity of flip-chip type ICs. In this case, when the upper surface of the barrier metal layer has a circular shape, the reference value is preferably set to 5% to 50% of its diameter.
[0066]
Further, according to the present invention, since the scale is provided on the adjustment mark, it is extremely easy to ascertain the amount of misalignment between the print mask and the IC wafer, thereby also improving the productivity of the flip-chip type IC. be able to.
[0067]
Further, according to the present invention, by using the barrier metal layer of the IC wafer as the adjustment mark, the solder paste applied on the adjustment mark is not wasted, and the amount of the solder paste used can be reduced. is there.
[Brief description of the drawings]
FIG. 1 is a plan view of an IC wafer according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of a main part of the IC wafer shown in FIG.
3 (a) to 3 (e) are cross-sectional views of respective steps for explaining a method of manufacturing a flip-chip type IC using the IC wafer shown in FIG.
FIG. 4 is an enlarged plan view of a main part of an IC wafer according to another embodiment of the present invention.
FIG. 5 is a plan view of a conventional IC wafer.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 semiconductor substrate 2 circuit pattern 3 barrier metal layer 4 passivation layer 5 adjustment mark 6 metal sheet 7 opening 8 adjustment hole 9 ′ ... Solder paste 9a, 9b ... Solder bump M ... Print mask W ... IC wafer X ... Alignment mark

Claims (6)

In an IC wafer in which a large number of IC chip regions are formed on the upper surface and a plurality of barrier metal layers are provided in each IC chip region,
When a print mask having an opening corresponding to the barrier metal layer is provided on an IC wafer, adjustment marks for recognizing a positional shift amount between the barrier metal layer and the opening are provided in a plurality of IC chip areas. IC wafer. The IC wafer according to claim 1, wherein the adjustment mark has a scale. 3. The IC wafer according to claim 1, wherein the barrier metal layer also serves as the adjustment mark. When positioning a print mask having a plurality of openings corresponding to the barrier metal layer with respect to the IC wafer according to any one of claims 1 to 3, a position in each IC chip area recognized by the adjustment mark is adjusted. A method for manufacturing a flip-chip type IC, comprising a step of adjusting a positional relationship between an IC wafer and a print mask based on a positional shift amount between a barrier metal layer and an opening. 5. The flip chip according to claim 4, wherein the positional relationship between the IC wafer and the print mask is adjusted so that the amount of displacement between the barrier metal layer and the opening in each IC chip area is equal to or less than a predetermined reference value. Manufacturing method of mold IC. 6. The method according to claim 5, wherein the reference value is set to 5% to 50% of a diameter of the barrier metal layer having a circular upper surface.

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