JP2004220093A - Processor, execution task deciding device and arithmetic processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently execute a plurality of tasks in a real time. <P>SOLUTION: This processor is provided with a task starting part 11 for determining whether or not each of a plurality of tasks can be started, an execution task deciding part 12 for deciding a task to be started based on the determination result of the task starting part 11 and a processor core 13 for executing the task decided by the execution task deciding part 12. A plurality of FIFO 10 are connected to the task starting part 11. Data to be inputted to the task are stored in the FIFO 10, and whether or not any free area is present in another FIOF 10 where the execution result of the task should be stored is determined by the task starting part 11, and the task to be started is decided by the execution task deciding part 12 based on the determination result. Thus, it is possible to execute the scheduling of the task without providing any operating system, and to eliminate the overhead of the operating system. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a processor that executes a plurality of tasks in a time-sharing manner and an execution task determination device.
[0002]
[Prior art]
When a processor executes a plurality of tasks in a time-division manner, it is common to switch tasks using software such as an operating system.
[0003]
The operating system detects whether or not each task becomes executable at regular intervals. Whether or not execution is possible can be determined by, for example, whether data to be processed is ready.
[0004]
While the operating system is performing such determination processing, the task execution must be interrupted. When the execution of a task is interrupted, the contents of a general-purpose register, a stack pointer (SP), and a program counter (PC) are saved in a main memory outside the processor. The saved information is managed by the operating system together with the task identification information (task ID).
[0005]
The operating system has a scheduler, and the scheduler determines a task to be actually executed from executable tasks according to a method such as round robin.
[0006]
The operating system acquires various information saved in the main memory or the like for the task determined to be executed by the scheduler, and stores the contents of the general-purpose register, the stack pointer (SP), and the program counter (PC) in the save destination. Each register is restored from a main storage device or the like outside the processor, and then execution of the task is started.
[0007]
A method of realizing parallel processing of real-time data using a plurality of hardware data processing units has also been proposed (for example, see Patent Document 1). However, there is a problem that the configuration itself is complicated, such as providing a plurality of data processing cores for performing parallel processing and further providing an arbitration mechanism for them.
[0008]
[Patent Document 1]
JP 2000-509528 Gazette
[0009]
[Problems to be solved by the invention]
In task switching using software such as an operating system, there is an overhead due to the operation of the operating system itself, and it is necessary to prepare a processor with higher performance than that required for the original task processing.
[0010]
Further, in task switching by the operating system, it takes time to switch tasks, and it is difficult to construct a system with real-time properties.
[0011]
Furthermore, since the operating system only determines whether a task can be executed at regular time intervals, the operating system determines that the task can be executed after the task is executable, and waits until the task is actually executed. However, the response was poor. This poor response has made it more difficult to construct a system with real-time characteristics.
[0012]
In addition, when it is determined that the task can be started on the condition that data to be processed is ready, data may not be stored in an area for storing a processing result, and in such a case, data may be lost. Become.
[0013]
On the other hand, when realizing real-time processing by using many hardware, conventionally, the configuration tends to be complicated and the cost tends to be high.
[0014]
The present invention has been made in view of such a point, and an object of the present invention is to provide a processor and an execution task determination device that can efficiently execute a plurality of tasks in real time.
[0015]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention provides a processor for processing a plurality of tasks in a time-division manner, wherein one or more first and / or first processors for storing data used in the processing of the predetermined task for a predetermined task. (First In First Out) type storage means and a processing result after performing the task processing using the data obtained from the first FIFO type storage means, and the stored processing result If there is another task that uses the task, one or more second FIFO-type storage means for storing data used in the processing of the other task, and the first FIFO-type storage means performs processing of the task. To determine whether or not the second FIFO type storage means has data to be used in the second FIFO type storage means, and whether or not there is a free area for storing the processing result of the task. Comprising a click determining means, based on the determination result of the task determining means, and a execution task determining means for determining a next to be started task from among the plurality of tasks.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a processor and an execution task determination device according to the present invention will be specifically described with reference to the drawings.
[0017]
(Principle of the present invention)
There is an increasing demand to execute multiple tasks in real time on a time-sharing basis. For example, FIG. 1 is a diagram showing processing contents of a software defined radio. In the software defined radio of FIG. 1, processes A to D are continuously executed. For example, in the process B, the result of performing a predetermined arithmetic process using the output of the process A as an input is passed to the process C.
[0018]
In FIG. 1, the number of output data in each process does not always match the number of data required to start the next process. Also, the processing amount of each processing varies depending on the processing content. Furthermore, since the timing of data transfer differs between processes, it is necessary to synchronize between stages of each process.
[0019]
In order to efficiently realize the processing of FIG. 1, each processing is often generated as one or more tasks. Each task may be realized by software or hardware.
[0020]
In the present invention, a FIFO (First In First Out) is inserted between tasks so that strict synchronization between tasks is not required. The FIFO generally refers to a method of storing data. In the embodiments described below, a method in which stored data is sequentially retrieved from those stored in the past, that is, a FIFO type storage device. The most recently stored data is the last to be retrieved, and for example, a data structure called a queue is a storage device of this type. The schematic configuration of the processor in this case is as shown in FIG.
[0021]
In FIG. 2, FIFO 1 outputs input data to task 1, and FIFO 2 receives output data from task 1 and outputs input data to task 2.
[0022]
In FIG. 2, one FIFO is provided on the input side and one output side of each task. However, a plurality of FIFOs may be provided.
[0023]
Although it is possible to realize the software defined radio with the configuration shown in FIG. 2, since the amount of processing for synchronizing each task is large, even if a FIFO is used, software synchronization is performed by a processor. Overhead becomes large and implementation is difficult.
[0024]
Here, focusing on the activation condition of each task, each task does not need to be activated when input data does not exist. If there is no free space for storing the processing result of each task in the FIFO on the output side of each task, there is a possibility that the processing result of each task may be lost. In this case, there is no need to activate the task.
[0025]
Therefore, each embodiment of the present invention described below monitors the storage state of data in the FIFO, and only when there is input data to each task and there is a free area in the FIFO on the output side. Have started the task.
[0026]
(1st Embodiment)
FIG. 3 is a block diagram showing a schematic configuration of the first embodiment of the processor according to the present invention. The processor in FIG. 3 includes a task activation unit 11 that determines whether each of a plurality of tasks can be activated, an execution task determination unit 12 that determines a task to be activated based on the determination result of the task activation unit 11, A processor core 13 for executing the task determined by the task determining unit 12.
[0027]
A plurality of FIFOs 10 are connected to the task activation unit 11. Each FIFO 10 corresponds to the FIFO 10 in FIG. 2, and the task activating unit 11 exchanges data between the FIFOs 10. More specifically, the task activation unit 11 holds the output data of the FIFO 10 to be input to the task, and checks whether there is an empty area in another FIFO 10 in which the processing result of the task is to be stored. . Then, it is determined that the task should be started only when there is output data of the FIFO 10 to be input to the task and there is a free area in another FIFO 10 in which the processing result of the task is to be stored.
[0028]
When there are a plurality of tasks that can be activated, the execution task determination unit 12 selects any one of the tasks. For example, the task with the smallest task ID for identifying each task is executed.
[0029]
The processor core 13 includes, for example, an instruction acquisition unit, an instruction interpretation unit, an instruction execution unit, an instruction execution result storage unit that stores an instruction execution result, and an instruction execution state storage unit that stores an execution state of an instruction.
[0030]
As described above, in the first embodiment, the FIFO 10 holds the data to be input to the task, and determines whether or not there is a free area in another FIFO 10 in which the execution result of the task is to be stored. Since the execution task determination unit 12 determines the task to be started based on the determination result, the task can be scheduled without an operating system, and is not affected by the overhead of the operating system. Tasks can be processed in real time.
[0031]
(Second embodiment)
In the second embodiment, priorities are assigned to a plurality of tasks, and the tasks are executed according to the priorities.
[0032]
FIG. 4 is a block diagram showing a schematic configuration of a second embodiment of the processor according to the present invention. The processor in FIG. 4 includes a task ID / priority supply unit 14 for supplying task IDs and priorities of a plurality of tasks in addition to the configuration in FIG.
[0033]
FIG. 5 is a block diagram showing the detailed configurations of the execution task determination unit 12 and the task ID / priority supply unit 14. As shown in the figure, the task ID / priority supply unit 14 stores the correspondence between the task ID of each task and the priority. The execution task determining unit 12 includes an executable task ID list 15 in which a list of executable tasks notified from the task activating unit 11 is registered, and a priority encoder 16 that determines a task to be activated.
[0034]
The priority encoder 16 acquires the priority of the tasks registered in the task ID list from the task ID / priority supply unit 14, and determines, for example, the task with the highest priority as the activation task.
[0035]
There is no particular limitation on the method of setting the priority supplied by the task ID / priority supply unit 14. For example, when a new task is generated, the priority of the task may be set, The priority order may be changed.
[0036]
FIG. 6 is a flowchart showing a processing procedure of the execution task determining unit 12 of FIG. First, the task ID of the task registered in the executable task ID list 15 is referred to (step S1), and the priority corresponding to the task ID is acquired from the task ID / priority supply unit 14 (step S2).
[0037]
Next, it is determined whether or not the priority acquired in step S2 is higher than the priority of the task activation candidate (step S3). If higher, the task having the task ID referred to in step S1 is set as the activation candidate. (Step S4).
[0038]
When the processing in step S4 is completed, or when it is determined in step S3 that the task is not high, it is determined whether or not a task whose priority has not yet been compared remains in the executable task ID list 15 (step S4). S5) If remaining, the processing after step S1 is repeated, and if not remaining, the processing is terminated.
[0039]
As described above, in the second embodiment, since the priorities of the tasks are determined in advance, when a plurality of tasks are listed as the activation candidates, the task with the higher priority can be executed preferentially, and the processing efficiency can be improved. Can be achieved. In addition, it is possible to quickly select a task to be started.
[0040]
(Third embodiment)
In the third embodiment, the priority can be dynamically changed.
[0041]
FIG. 7 is a block diagram showing a schematic configuration of a third embodiment of the processor according to the present invention. The processor in FIG. 7 includes a priority changing unit 30 that dynamically changes task priorities in addition to the configuration in FIG.
[0042]
The priority change unit 30 includes a time measurement unit 17 that measures the execution time of each task, a startup time table 18 in which a correspondence between the task ID of each task and a past startup time is registered, and a startup interval of each task. It has an average time interval calculation unit 19 for calculating an average, and a priority determination unit 20 for determining the priority of each task based on the calculation result of the average time interval calculation unit 19.
[0043]
The smaller the calculation result of the average time interval calculator 19, the more frequently the task is started. For this reason, the priority determination unit 20 sets a higher priority, for example, for a task with a smaller calculation result of the average time interval calculator 19.
[0044]
More specifically, the average time interval calculation unit 19 calculates the data input interval to each FIFO 10 and sets the priority order in the priority order determination unit 20 so that the priority order of the task corresponding to the FIFO 10 whose interval is short becomes higher. Is determined. Alternatively, the average time interval calculation unit 19 calculates the execution interval of each task notified from the processor core 13 and determines the priority in the priority order determination unit 20 so that the priority of the task with the short interval becomes higher. You may. Alternatively, the average time interval calculating unit 19 monitors the free area of each FIFO 10 that supplies data to each task, and the priority order determining unit 20 sets the priority of the task corresponding to the FIFO 10 with the small free area to be higher. The ranking may be determined. Alternatively, the average time interval calculation unit 19 calculates the data output interval from each task to each FIFO 10, and sets the priority order by the priority order determination unit 20 so that the priority order of the task corresponding to the FIFO 10 having the shortest interval becomes higher. You may decide.
[0045]
As described above, in the third embodiment, since the priority of each task can be dynamically changed, task scheduling can be performed with reference to the past execution history.
[0046]
(Fourth embodiment)
In the fourth embodiment, when a task having a higher priority than a task being executed is ready to be activated, the task being executed is interrupted and a task with a higher priority is activated.
[0047]
The block configuration of the fourth embodiment is the same as in FIGS. FIG. 8 is a time chart for explaining the operation of the fourth embodiment of the processor according to the present invention. FIG. 8 shows an example in which there are three tasks A, B, and C, in which task A has the highest priority, task B has the highest priority, and task C has the lowest priority.
[0048]
First, it is assumed that the task C is activated at time t0. Thereafter, it is assumed that the preparation for starting the task B is completed at time t1. As a result, the execution task determination unit 12 suspends the execution of the task C and starts the activation of the task B instead.
[0049]
Thereafter, it is assumed that the preparation for starting the task A is completed at time t2. As a result, the execution task determination unit 12 suspends the execution of the task B, and starts the activation of the task A instead.
[0050]
Thereafter, assuming that the execution of the task A is completed at time t3, the execution of the task B having the next highest priority is resumed. Execution of task C is started.
[0051]
As described above, in the fourth embodiment, when the preparation for starting a task having a higher priority than the task being executed is ready, the processing of the task being executed is interrupted, and the execution of the task having the higher priority is started. Thus, important tasks can always be processed with priority, and the processing performance of the entire processor can be improved.
[0052]
(Fifth embodiment)
The fifth to eleventh embodiments described below relate to a mechanism for quickly switching a task being executed.
[0053]
FIG. 9 is a block diagram showing a schematic configuration of a fifth embodiment of the processor according to the present invention. The processor of FIG. 9 includes a task start unit 11, an execution task determination unit 12, and a task ID / priority supply unit 14 similar to those of FIG. 4, and a register set group 21 including a plurality of register sets. A register set selecting unit 22 for selecting any one register set from the register set group 21 and an operation unit 23 for performing an operation process using the selected register set are provided. The processor core 13 is composed of the register set, the register set selection unit 22 and the operation unit 23.
[0054]
A decoder 22a for selecting one register set from the register set group 21 is provided inside the register set selection unit 22. The decoder 22a outputs a register set selection signal corresponding to the task ID from the execution task determination unit 12.
[0055]
Each register set consists of one or more registers that contain all the information specific to the individual task. The type of each register constituting the register set depends on the architecture of the processor, and is, for example, a program counter (PC), a stack pointer (SP), or a general-purpose register (R0, R1,...). In this specification, the total number of registers in one register set is r (r is an integer of 1 or more).
[0056]
The total number of register sets is m (m is an integer) equal to or greater than the number n of tasks that can be executed in a time-division manner. Each register set is identified by a unique identification number (register set ID).
[0057]
The task being executed uses one register set. If the type of register used differs for each task, a dedicated register set may be provided for each task. At the time of designing the processor, the types of the registers configuring the register set may be determined, or the types of the registers configuring the register set may be changed a posteriori by a program instruction.
[0058]
When the type of register used for each task is different, a register set ID task ID correspondence unit 24 in which the correspondence between the task ID and the register set ID is registered as shown in FIG. The register set corresponding to each task may be determined with reference to the table.
[0059]
More specifically, the register set ID task ID correspondence unit 24 is configured by a table as shown in FIG. The table in FIG. 11 may be created at the time of designing the processor so that it cannot be changed thereafter, or the contents of the table may be changed by some instruction after the processor is started.
[0060]
When the execution task determination unit 12 in FIG. 9 or FIG. 10 switches the task, the execution task determination unit 12 notifies the register set selection unit 22 of the task ID of the switched task. The register set selection unit 22 obtains a register set ID corresponding to the task after switching using the table or the like in FIG. 11 and supplies the register set value corresponding to the ID to the calculation unit 23. The operation unit 23 performs an operation by setting the value of the register set selected by the register set selection unit 22 to each register, and stores the operation result in the register set selected by the register set selection unit 22.
[0061]
As described above, in the fifth embodiment, when the task switching occurs, the register set is also switched, so that the processing preparation time at the time of task switching can be reduced, and high-speed switching of tasks can be realized. Also, when the processing of a task is interrupted and then resumed, the value of the register set may be read before resuming, so that the processing of the task that has been interrupted can be quickly resumed.
[0062]
(Sixth embodiment)
In the sixth embodiment, at least some of the register sets in the register set group 21 are saved to the outside.
[0063]
FIG. 12 is a block diagram showing a schematic configuration of a sixth embodiment of the processor according to the present invention. The processor in FIG. 12 includes a hit determination unit 31, an external register set storage unit 32, an external storage control unit 33, and a register set transfer unit 34 in addition to the configuration in FIG.
[0064]
The register set group 21 of the present embodiment may be more, less or equal to the number n of tasks to be executed in a time division manner.
[0065]
The hit determination unit 31 determines whether the register set of the task to be executed is registered in the register set ID task ID correspondence unit 24. The register set transfer unit 34 transfers the contents of at least a part of the register sets in the register set group 21 to the external register set storage unit 32, and transfers the contents of the register set read from the external register set storage unit 32 to the register set. Transfer to group 21. The external register set storage unit 32 stores the contents of at least some of the register sets in the register set group 21.
[0066]
FIG. 13 is a diagram showing a data configuration of the external register set storage unit 32. The external register set storage unit 32 can store the contents of an arbitrary register set included in the register set group 21, and can also transfer the stored contents of the register set to the register set group 21. Each register set stored in the external register set storage unit 32 is managed by a task ID, and the task ID is designated when the contents of the register set once stored are called.
[0067]
As described above, the external register set storage unit 32 can temporarily save the contents of at least a part of the register sets in the register set group 21 and transfer the contents to the register set group 21 as necessary.
[0068]
The external register set storage unit 32 may be configured by dedicated hardware, or may use a partial area of a memory provided in advance such as a main storage memory.
[0069]
FIG. 14 is a flowchart illustrating the processing procedure of the hit determination unit 31. First, it is determined whether a register set ID corresponding to a task ID indicating a task to be executed is registered in the register set ID task ID corresponding unit 24 (step S11). If registered, it is determined that a hit has occurred, and a register set ID corresponding to the corresponding task ID is obtained (step S12). In this case, task switching is performed in the same procedure as in FIG.
[0070]
On the other hand, if not registered, it is determined that a mistake has occurred (step S13), the corresponding register set is called from the external register set storage unit 32, and a part of the register set group 21 is replaced.
[0071]
More specifically, first, the contents of at least a part of the register sets in the register set group 21 are transferred to the external register set storage unit 32 via the register set transfer unit 34. At the same time, the contents of the register set used by the task to be executed are read from the external register set storage unit 32 and transferred to the register set group 21 via the register set transfer unit 34.
[0072]
As described above, in the sixth embodiment, the contents of at least some of the register sets in the register set group 21 are saved in the external register set storage unit 32, and the contents of the register set are stored in the external register set storage unit 32 as necessary. Since the contents of the register set can be returned to the group 21, tasks more than the total number of register sets in the register set group 21 can be processed. Therefore, the number of register sets in the register set group 21 can be reduced, and the size of the processor can be reduced.
[0073]
(Seventh embodiment)
In the seventh embodiment, a register set to be saved is specified in advance when the hit determination unit 31 does not hit.
[0074]
FIG. 15 is a block diagram showing a schematic configuration of a seventh embodiment of the processor according to the present invention. The processor in FIG. 15 includes a save register set determining unit 35 in addition to the configuration in FIG.
[0075]
The save register set determination unit 35 determines a register set to be saved in the external register set storage unit 32 from the register set group 21 based on the priority supplied from the task ID / priority supply unit 14. The register set transfer unit 34 transfers the contents of the register set determined by the save register set determination unit 35 to the external register set storage unit 32, and transfers the contents of the register set read from the external register set storage unit 32 to a register set group. Transfer to 21.
[0076]
FIG. 16 is a flowchart showing a processing procedure of the save register set determining unit 35. First, it is determined whether a register set to be used exists in the register set group 21 and a task corresponding to the register set cannot be executed (step S21). If the determination is Yes, the task with the lowest priority is selected from the tasks (step S22).
[0077]
On the other hand, if the determination in step S21 is No, the task with the lowest priority is selected from the tasks corresponding to each register set in the register set group 21 (step S23).
[0078]
When the processing in step S22 or S23 ends, the ID of the register set (register set ID) used by the selected task is obtained (step S24), and the obtained ID is instructed to the register set transfer unit 34 (step S25). .
[0079]
As described above, in the seventh embodiment, the register set to be saved can be explicitly specified in the external register set storage unit 32. Therefore, the register set that is not frequently used can be replaced, and the register set to be saved can be replaced. A reduction in processing efficiency can be prevented.
[0080]
(Eighth embodiment)
In the sixth and seventh embodiments, the hit determination unit 31 determines whether or not the register set used by the task to be executed exists in the register set group 21. May not be possible. Therefore, in an eighth embodiment described below, processing of a task that is not affected by the determination result of the hit determination unit 31 is performed while the hit determination unit 31 is performing processing.
[0081]
FIG. 17 is a block diagram showing a schematic configuration of an eighth embodiment of the processor according to the present invention. The execution task determination unit 12 of FIG. 17 performs a different process from the execution task determination unit 12 of FIG. That is, the execution task determination unit 12 in FIG. 17 requests the hit determination unit 31 to transmit the determination result, and receives the determination result from the hit determination unit 31.
[0082]
As shown in FIG. 18, the register set ID task ID correspondence unit 24 in FIG. 17 has a flag in association with each task ID and register set ID. This flag is set during execution of a process for transferring a content of a register set used by the task from the external register set storage unit 32 when an attempt is made to execute a certain task, but a miss occurs in the hit determination unit 31. You.
[0083]
When switching the task to be executed, the execution task determination unit 12 issues either a miss transfer hit determination request or a hit determination request. The miss transfer hit determination request notifies the hit determination unit 31 of the task ID. If a miss occurs, the register set used by the task is transferred from the external register set transfer device to the register set group 21. This is an instruction to the set selection unit 22.
[0084]
The processing procedure of the hit judging unit 31 in the case of receiving a transfer hit judging request at the time of a miss is shown in the flowchart of FIG. First, it is determined whether the task ID of the task to be executed is registered in the register set ID task ID correspondence unit 24 (step S31). If registered, a register set ID corresponding to the corresponding task ID is obtained (step S32). If not registered, a mistake is determined (step S33), and transfer of the register set used by the corresponding task is performed. To the register set transfer unit 34 (step S34).
[0085]
On the other hand, the hit determination request notifies the hit determination unit 31 of the task ID, and performs a hit determination while excluding a register set whose flag is valid. Even if a mistake is made, the register set is not transferred.
[0086]
The processing procedure of the hit determination unit 31 when a hit determination request is received is shown in the flowchart of FIG. First, it is determined whether or not the task ID of the task to be executed is registered in the register set ID task ID correspondence unit 24 except for the task ID for which the flag is set (step S41). If the task ID has been registered, a register set ID corresponding to the task ID is obtained (step S42), and if not, it is determined that a mistake has occurred (step S43).
[0087]
If the set flag does not exist in the register set ID task ID correspondence unit 24, the execution task determination unit 12 determines, when switching the task to be executed, a transfer hit at the time of a miss using the switched task ID. Make a request. If there is a hit, the execution task determination unit 12 acquires the register set ID corresponding to the new hit task ID from the register set ID task ID correspondence unit 24, and notifies the register set ID to the register set selection unit 22. , Start executing a new task. On the other hand, when a miss occurs, the hit determination unit 31 instructs the register set transfer unit 34 to transfer the register set, and the register set ID task ID corresponding unit 24 sets a flag corresponding to the register set to be transferred.
[0088]
When the transfer of the register set is completed, the register set transfer unit 34 notifies the register set ID task ID corresponding unit 24 of the completion of the transfer. According to this notification, the register set ID task ID corresponding unit 24 invalidates the register set flag.
[0089]
The execution task determination unit 12 acquires the register set ID corresponding to the task to be executed from the register set ID task ID correspondence unit 24, notifies the acquired register set ID to the register set selection unit 22, and executes the task. To start.
[0090]
If the set flag exists in the register set ID task ID correspondence unit 24, the execution task determination unit 12 issues a hit determination request with the switched task ID when switching the task to be executed. . If there is a hit, the execution task determination unit 12 acquires the register set ID corresponding to the new hit task ID from the register set ID task ID correspondence unit 24, and notifies the register set ID to the register set selection unit 22. , Start executing a new task. On the other hand, if a mistake is made, the task is not switched.
[0091]
FIG. 21 is a diagram for explaining a task execution mode when a flag set in the register set ID task ID correspondence unit 24 exists. In this example, during execution of the task with the task ID 5, when it becomes possible to execute the task with the task ID 1 having a higher priority than this task, the execution task determination unit 12 sends the task ID 1 to the hit determination unit 31. Request for a transfer hit determination at the time of a miss.
[0092]
In this example, the hit judging unit 31 that has received this request makes a miss judgment, whereby the register set transfer unit 34 starts transferring registers used by the task ID 1 in the register set group 21. This transfer takes time until time t3.
[0093]
When the execution of task ID5 ends at time t2 between times t1 and t3, the execution task determination part issues a hit determination request for the task with the highest priority (task ID7 in the example of FIG. 21) among the executable tasks. Do. If there is a hit, task ID 7 is executed.
[0094]
Thereafter, at time t3, the completion of the transfer is notified from the register set transfer unit 34, whereby the execution task determination starts the execution of the task ID1.
[0095]
As described above, in the eighth embodiment, during the transfer of the register set used by a certain task, another task that does not affect the execution of the task is executed, so that the transfer of the register set is not waited for. Task processing can be performed, and task processing efficiency can be improved.
[0096]
(Ninth embodiment)
In the ninth embodiment, a flag indicating whether or not the contents of a register has been updated is provided in each register constituting the register set.
[0097]
The ninth embodiment has the same block configuration as that of FIG. 12, but differs from FIG. 12 in the data structure of the register set of the register set group 21. FIG. 22 is a diagram illustrating a data structure of a register set according to the ninth embodiment. As shown, a change flag is provided for each register constituting the register set. This change flag is set when rewriting the contents of the corresponding register. The processing procedure in this case is represented by a flowchart as shown in FIG.
[0098]
In FIG. 23, first, a change flag corresponding to a register to be rewritten is set (step S51), and thereafter, the register is rewritten (step S52).
[0099]
The change flag in FIG. 22 is cleared when the register set stored in the external register set storage unit 32 is read. The processing procedure when there is a transfer request from the external register set storage unit 32 to the register set group 21 is represented by a flowchart as shown in FIG.
[0100]
In FIG. 24, first, all the change flags in the transfer destination register set are cleared (step S61), and thereafter, the register set is transferred (step S62).
[0101]
FIG. 25 is a flowchart showing a processing procedure of the register set transfer unit 34 when the register set group 21 requests the external register set storage unit 32 to transfer the contents of the register set. First, attention is paid to one register in the register set to be transferred (step S71), and it is determined whether or not a change flag of the noted register set is set (step S72).
[0102]
If it is set, the register to be transferred is transferred to the external register set storage unit 32 (step S73). If it has not been set or if the processing of step S73 has been completed, it is determined whether or not processing has been performed for all the registers (step S74). If it is done, it ends.
[0103]
As described above, in the ninth embodiment, only the changed registers among the registers included in the register set group 21 are transferred to the external register set storage unit 32. The transfer time can be reduced.
[0104]
(Tenth embodiment)
In the tenth embodiment, the external register set storage unit 32 has a flag indicating whether each register of each register set has been rewritten.
[0105]
FIG. 26 shows the data structure of the external register set storage unit 32. As shown, a valid flag is provided for each register of each register set. This valid flag is set when the corresponding register is rewritten.
[0106]
FIG. 27 is a flowchart showing a process of initializing a valid flag, which is a process performed by the external storage control unit 33 when a task is activated. The external storage control unit 33 clears all the valid flags in the register set corresponding to the task to be started (Step S81).
[0107]
FIG. 28 is a flowchart showing the setting process of the valid flag, which is performed by the external storage control unit 33 when a register set transfer request from the register set transfer unit 34 to the external register set storage unit 32 is issued. The external storage control unit 33 sets a valid flag corresponding to the register to be transferred from the external register set storage unit 32 (Step S91). After that, the corresponding register is transferred from the register set group 21 to the external register set storage unit 32 (Step S92).
[0108]
FIG. 29 is a flowchart showing a processing procedure of the external storage control unit 33 when there is a transfer request from the external register set storage unit 32 to the register set group 21. First, a valid flag in the register set to be transferred is read (step S101). Next, attention is paid to one register in the register set to be transferred (step S102).
[0109]
It is determined whether or not the valid flag corresponding to this register is set (step S103). If it is set, the register is transferred to the external register set storage unit 32 (step S104). Next, it is determined whether or not processing has been performed on all registers (step S105). If there is a register that has not been processed, the processing from step S101 is repeated.
[0110]
As described above, in the tenth embodiment, since the valid flag indicating whether the register has been rewritten is provided in the external register set storage unit 32, the external register set is stored only when the contents of the register are rewritten. What is necessary is just to transfer the contents of the registers from the storage unit 32 to the register set group 21, so that the number of transfers can be reduced and the transfer time can be shortened.
[0111]
(Eleventh embodiment)
In the eleventh embodiment, the register set of each task in the external register set storage unit 32 has a list structure.
[0112]
FIG. 30 is a diagram showing a data structure of the external register set storage unit 32 according to the eleventh embodiment. The external register set storage unit 32 has a list structure, and stores a register value storage area for storing a changed register value and an identification number (register ID) of the register stored in the register value storage area. Store as a set. That is, the external register set storage unit 32 does not store the values of the registers whose contents do not change.
[0113]
FIG. 31 is a flowchart showing a processing procedure of the external storage control unit 33 when there is a transfer request from the external register set storage unit 32 to the register set group 21. First, the pointer is moved to the head of the list of register sets to be transferred (step S111). Next, the register ID and the register value are read from the list in the external register set storage unit 32 (Step S112). Next, the value of the register is written to the register of the register set group 21 corresponding to the register ID (step S113). Next, it is determined whether or not the end of the list is reached (step S114). If it is at the end of the list, the process ends. If it is not at the end of the list, the process moves to the next item in the list and repeats the processing from step S111.
[0114]
FIG. 32 is a flowchart showing a processing procedure of the external storage control unit 33 when a register transfer request is issued from the register set transfer unit 34 to the external register set storage unit 32. First, it is determined whether the register ID to be transferred is in the corresponding list in the external register set storage unit 32 (step S121). If it is not in the list, an item of the register ID to be transferred to the list is added (step S122).
[0115]
If it is determined in step S121 that it is in the list, or if the processing in step S122 is completed, the value of the register is written to the register value storage area corresponding to the register ID to be transferred in the list (step S123).
[0116]
FIG. 33 is a flowchart showing a processing procedure of the external storage control unit 33 when the task is completed. The contents of the list corresponding to the completed task in the external register set storage unit 32 are discarded (step S131).
[0117]
As described above, in the eleventh embodiment, since the external register set storage unit 32 has a list structure and stores only the values of the changed registers, the memory capacity of the external register set storage unit 32 can be reduced, and , The amount of data transferred to and from the register set group 21 can also be reduced.
[0118]
In the first to eleventh embodiments described above, examples in which the present invention is applied to a processor have been described. However, the present invention is also applicable to semiconductor integrated devices other than processors. For example, only the execution task determination unit 12 shown in FIG. 1 or the like may be provided separately from the processor.
[0119]
【The invention's effect】
As described above in detail, according to the present invention, it is determined whether or not the task is ready to be started based on the data storage states of the first and second FIFO storage units, and only the task that is ready to be started is started. As a result, task activation scheduling can be performed without an operating system, and the overhead of the operating system can be eliminated, and a plurality of tasks can be processed efficiently.
[0120]
In addition, since the first and second FIFO storage units that store data to be processed by the task are monitored, there is no possibility that data will be lost, and highly reliable task processing can be performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing processing contents of a software defined radio.
FIG. 2 is a schematic configuration diagram of a processor provided with a FIFO between tasks.
FIG. 3 is a block diagram showing a schematic configuration of a first embodiment of a processor according to the present invention.
FIG. 4 is a block diagram showing a schematic configuration of a second embodiment of the processor according to the present invention.
FIG. 5 is a block diagram showing a detailed configuration of an execution task determination unit 12 and a task ID / priority order supply unit 14.
FIG. 6 is a flowchart showing a processing procedure of an execution task determining unit 12 of FIG. 5;
FIG. 7 is a block diagram showing a schematic configuration of a third embodiment of the processor according to the present invention.
FIG. 8 is a time chart for explaining the operation of a fourth embodiment of the processor according to the present invention.
FIG. 9 is a block diagram showing a schematic configuration of a fifth embodiment of the processor according to the present invention.
FIG. 10 is a block diagram of a processor showing a modification of FIG. 9;
FIG. 11 is a diagram showing a data structure of a register set ID task ID correspondence unit 24.
FIG. 12 is a block diagram showing a schematic configuration of a sixth embodiment of the processor according to the present invention.
FIG. 13 is a diagram showing a data configuration of an external register set storage unit 32.
FIG. 14 is a flowchart showing a processing procedure of a hit determination unit 31.
FIG. 15 is a block diagram showing a schematic configuration of a seventh embodiment of the processor according to the present invention.
FIG. 16 is a flowchart showing a processing procedure of a save register set determining unit 35;
FIG. 17 is a block diagram showing a schematic configuration of an eighth embodiment of a processor according to the present invention.
FIG. 18 is a diagram illustrating a data structure of a register set ID task ID corresponding unit according to the eighth embodiment.
FIG. 19 is a flowchart illustrating a processing procedure of a hit determination unit when a transfer hit determination request at the time of a miss is received;
FIG. 20 is a flowchart illustrating a processing procedure of a hit determination unit when a hit determination request is received.
FIG. 21 is a view for explaining a task execution mode when a flag set in the register set ID task ID correspondence unit 24 exists.
FIG. 22 is a view showing a data structure of a register set according to the ninth embodiment;
FIG. 23 is a flowchart showing a processing procedure when a register rewrite request is issued.
FIG. 24 is a flowchart showing a processing procedure when there is a transfer request from the external register set storage unit to the register set group.
FIG. 25 is a flowchart showing a processing procedure when there is a transfer request from a register set group to an external register set storage unit.
FIG. 26 is a diagram showing a data structure of an external register set storage unit 32.
FIG. 27 is a flowchart showing a processing procedure when a task is started.
FIG. 28 is a flowchart showing a processing procedure when a register transfer request is sent from the register set transfer unit to the external register set storage unit.
FIG. 29 is a flowchart showing a processing procedure when there is a transfer request from the external register set storage unit to the register set group.
FIG. 30 is a diagram illustrating a data structure of an external register set storage unit 32 according to the eleventh embodiment.
FIG. 31 is a flowchart showing a processing procedure when there is a transfer request from the external register set storage unit to the register set group.
FIG. 32 is a flowchart showing a processing procedure when there is a register transfer request from the register set transfer unit to the external register set storage unit.
FIG. 33 is a flowchart showing task end processing.
[Explanation of symbols]
11 Task launcher
12. Execution task determination unit
13 processor core
14 Task ID / Priority Supply Unit
15 Executable task ID list
16 priority encoder
17 Time measurement unit
18 Start time table
19 Average Time Perception Calculator
20 Priority order determination unit
21 Register set group
22 Register set selector
23 Calculation section
24 Register Set ID Task ID Corresponding Section
30 Priority change unit
31 Hit judgment unit
32 External register set storage
33 External storage control unit
34 Register set transfer section
35 Save register set decision unit

Claims (17)

In a processor that processes multiple tasks in a time-sharing manner,
One or more first FIFO (First In First Out) storage means for storing data used in processing of the predetermined task;
Using the data obtained from the first FIFO type storage means, store the processing result after performing the processing of the task, and if there is another task using the stored processing result, One or more second FIFO-type storage means for storing data used in the processing of the task of
Whether the first FIFO storage means holds data used for processing the task, and whether the second FIFO storage means has a free area for storing the processing result of the task. Task determining means for determining whether or not
An execution task determining unit that determines a task to be started next from the plurality of tasks based on a determination result of the task determining unit. Priority setting means for setting a priority for each of the plurality of tasks, wherein the execution task determining means determines the task to be started based on the priority set by the priority setting means. The processor of claim 1, wherein: Comprising a start frequency measuring means for measuring the start frequency of each of the plurality of tasks,
3. The processor according to claim 2, wherein the priority order setting unit sets the priority order based on the activation frequency measured by the activation frequency measurement unit. The processor according to claim 3, wherein the priority setting unit sets a higher priority for a task having a higher activation frequency. The execution task determination means, during the activation of the first task, the first FIFO type storage means holds data used for a second task having a higher priority than the first task, and When the second FIFO type storage unit has a free area in which to store the processing result of the second task, the activation of the first task is interrupted and the second task is activated. 3. The processor according to claim 2, wherein A register set group including at least a total number of tasks that can be executed in a time-sharing manner, including a register set including at least one register including all information unique to each task;
Register set selecting means for selecting the register set used by the task determined by the execution task determining means;
2. The processor according to claim 1, further comprising: an arithmetic processing unit that performs processing of the task determined by the execution task determining unit using a register set selected by the register set selecting unit. A correspondence storage unit for storing a correspondence between a task and the register set used by the task,
7. The processor according to claim 6, wherein the register set selection unit selects a register set used by the task determined by the execution task determination unit based on the correspondence stored in the correspondence storage unit. . A register set group including at least one register set including at least one register including all information unique to each task, the number of registers being less than the total number of tasks executable in a time-sharing manner;
Register set selecting means for selecting the register set used by the task determined by the execution task determining means;
Using a register set selected by the register set selecting means, an arithmetic processing means for processing the task determined by the execution task determining means,
External register set storage means capable of storing the contents of any register set included in the register set group,
When the contents of the register set used by the task are stored in the external register set storage means,
A register set used by the task stored in the external register set storage means, while transferring the contents of the register set used by the task being interrupted or to be interrupted included in the register set group to the external register set storage means. 2. The processor according to claim 1, further comprising: storage control means for transferring the contents of the register set to a register set corresponding to the register set transferred to the external register set storage means in the register set group. Hit determination means for determining whether the register set used by the task determined by the execution task determination means is present in the register set group,
When the hit determination means determines that the register set used by the task exists in the register set group,
The register set selecting means selects the register set from the register set group,
On the other hand, if it is determined that it does not exist,
After transferring the contents of the register set used by the task stored in the external register set storage means to the register set corresponding to the transfer destination in the register set group, the storage control means selects the register set. 9. The processor according to claim 8, wherein the means selects the register set after the transfer. When the hit determination unit determines that the register set does not exist, the external register set storage unit includes a save register set determination unit that selects a register set of the register set group to be saved.
10. The processor according to claim 9, wherein the storage control unit transfers the contents of the register set selected by the save register set determination unit to the external register set storage unit. The execution task determination unit takes into account the determination result of the task determination unit, and the storage control unit performs a register set exchange process between the register set group and the external register set storage unit. 9. The processor according to claim 8, wherein a task that can be executed without being affected by the replacement process is determined so that another task can be processed. The storage control unit, when it is necessary to update the storage content of the external register set storage unit, transfers only the changed register value of the register set group to the external register set storage unit. The processor of claim 8, wherein The storage control means, when it is necessary to transfer data from the external register set storage means to the register set group, a register whose register value of the register set group has been rewritten by execution of another task. 9. The processor according to claim 8, wherein only the contents of the register set are transferred from the external register set storage unit to the register set group. The storage control unit transfers the contents of the register set to the external register set storage unit only when the same register set as the register set stored in the external register set storage unit does not exist in the register set group. The processor of claim 8, wherein: 9. The processor according to claim 8, wherein the external register set storage means stores only the value of the changed register and the identification information of the register. In an execution task determination device for determining a task to be started next from among the plurality of tasks,
For each of the plurality of tasks, whether or not data that can be processed by the task is stored in one or more first FIFO type storage means for storing input data of processing of the task, and It is determined whether or not one or more second FIFO-type storage means for storing the processing result of the above has a free area in which the data of the processing result can be stored. An execution task determination unit that determines a task to be started next from the execution task determination device. In an arithmetic processing method for processing a plurality of tasks in a time-division manner,
For each of the plurality of tasks, whether or not data that can be processed by the task is stored in one or more first FIFO type storage means for storing input data of processing of the task, and It is determined whether or not one or more second FIFO-type storage means for storing the processing result of the above has a free area in which the data of the processing result can be stored. An operation processing method characterized in that a task to be started next is determined from the following.

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