JP2004179343A - Semiconductor substrate and manufacturing method thereof - Google Patents

Semiconductor substrate and manufacturing method thereof Download PDF

Info

Publication number
JP2004179343A
JP2004179343A JP2002342938A JP2002342938A JP2004179343A JP 2004179343 A JP2004179343 A JP 2004179343A JP 2002342938 A JP2002342938 A JP 2002342938A JP 2002342938 A JP2002342938 A JP 2002342938A JP 2004179343 A JP2004179343 A JP 2004179343A
Authority
JP
Japan
Prior art keywords
sealing material
surface
bare chip
inclined surface
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002342938A
Other languages
Japanese (ja)
Inventor
Eitaro Matsui
Hiroshi Yamanaka
山中  浩
栄太郎 松居
Original Assignee
Matsushita Electric Works Ltd
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd, 松下電工株式会社 filed Critical Matsushita Electric Works Ltd
Priority to JP2002342938A priority Critical patent/JP2004179343A/en
Publication of JP2004179343A publication Critical patent/JP2004179343A/en
Application status is Pending legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

Abstract

A sealing material having a required thickness is secured on a bare chip even if the amount of the sealing material is small.
A bare chip, a mounting board on which the bare chip is surface-mounted, and a sealing material for covering the bare chip mounted on the mounting board. The mounting substrate 1 has a slope 12 or a wall surface extending downward around the chip mounting portion 10 on which the bare chip 2 is mounted. The outermost peripheral edge of the sealing material 3 covering the bare chip 2 is located on the inclined surface 12 or the wall surface. The substantial contact angle at the outer peripheral edge of the sealing material can be increased, and the thickness can be increased with a small amount of the sealing material.
[Selection diagram] Fig. 1

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor substrate in which a bare chip is mounted on a mounting substrate and the bare chip is sealed with a sealing material, and a method for manufacturing the same.
[0002]
[Prior art]
There is a semiconductor substrate in which a bare chip such as a semiconductor element, a sensor element such as a pyroelectric element or a piezoelectric element is mounted on a mounting substrate, and the bare chip is further sealed with a sealing material. When high-density mounting is performed on such a semiconductor substrate, not only the pitch of the terminal portion of the chip mounting portion on the bare chip or the mounting substrate is reduced, but also as described in Japanese Patent Application Laid-Open No. 2001-110935, etc. There are many points to be resolved.
[0003]
[Patent Document 1]
JP 2001-110935 A
[Problems to be solved by the invention]
One of the problems that must be solved is the spread of the sealing material that covers the bare chip. The sealing material is supplied in a fluid state onto the bare chip, and the bare chip is covered with the sealing material and cured to perform sealing. In such a case, the height (thickness) of the sealing material cannot be sufficiently secured, and a part of the bare chip may not be sealed. To compensate for this, a large amount of the sealing material is required.
[0005]
In addition, there may be a problem that the sealing material spreads to the mounting area of another chip.
[0006]
The present invention has been made in view of such a point, and it is intended that a sealing material of a required thickness is secured within a desired range on a bare chip even if the sealing material is a small amount. And a method of manufacturing the same.
[0007]
[Means for Solving the Problems]
Thus, the semiconductor substrate according to the present invention is a semiconductor substrate comprising a bare chip, a mounting substrate on which the bare chip is surface-mounted, and a sealing material covering the bare chip mounted on the mounting substrate. The outer periphery of the chip mounting portion on which the bare chip is mounted is provided with an inclined surface which is lowered toward the outer periphery or a wall surface which extends downward, and a sealing material covering the bare chip has an outermost peripheral edge on the inclined surface or the wall surface. It is characterized by being located in. The inclination angle of the inclined surface or the wall surface extending downward can be added to the contact angle at the outer peripheral edge of the sealing material to increase the substantial contact angle (inclination angle + contact angle). It can have a thickness.
[0008]
In this case, a concave groove is formed around the chip mounting portion of the mounting substrate, and the inner peripheral wall of the concave groove has an inclined surface that becomes lower toward the outer periphery or a wall surface that extends downward. Even when the outermost peripheral edge of the sealing material is located, the chip mounting portion of the mounting substrate is provided on the upper surface of the convex portion provided on the mounting substrate, and the peripheral wall of the convex portion becomes lower toward the outer periphery. It may be an inclined surface or a wall surface extending downward, and the outermost peripheral edge of the sealing material may be located on the inclined surface or the wall surface.
[0009]
Further, the boundary between the chip mounting portion and the inclined surface may be a chamfered surface or a curved surface, and this curved surface may be formed by plating applied to the boundary.
[0010]
It is also preferable that the inclination angle of the inclined surface that is closer to the highest point of the sealing material is larger than the inclination angle of the inclined surface that is farther from the highest point of the sealing material, so that the inclined surface is steeply inclined.
[0011]
The method of manufacturing a semiconductor substrate according to the present invention is a method of manufacturing a semiconductor substrate including a bare chip, a mounting substrate on which the bare chip is surface-mounted, and a sealing material covering the bare chip mounted on the mounting substrate. The chip of the mounting substrate having a circuit pattern formed on the surface thereof, using, as a mounting substrate, a chip mounting portion on which a bare chip is mounted and having an inclined surface that becomes lower toward the outer periphery or a wall surface that extends downward. The bare chip is surface-mounted on the mounting portion, and then a sealing material in a fluid state is supplied on the chip mounting portion so that the outermost peripheral edge of the sealing material reaches the inclined surface or the wall surface, and sealing is performed in this state. It is characterized by hardening the stopper.
[0012]
At this time, a thin-film conductive layer is formed on the surface of the mounting substrate having an inclined surface or a wall surface extending downward on the outer periphery of the chip mounting portion, and then a laser is used as a circuit pattern of the thin-film conductive layer by laser. It is also preferable to form a circuit pattern by removing the boundary between the portion to be left and the non-circuit portion to insulate them, and then electroplating the remaining portion of the thin film conductive layer as a circuit pattern.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
1 and 2 show a semiconductor substrate according to the present invention, wherein 1 is a mounting substrate, 2 is a semiconductor mounted on a mounting substrate 1 It is a bare chip such as an element, and is connected to a circuit pattern on the mounting board 1 by wire bonding using wires 4. The bare chip 2 and the wire 4 are covered and sealed by the sealing material 3.
[0014]
Here, the chip mounting portion 10 on which the bare chip 2 is mounted on the mounting substrate 1 is provided on the surface of the convex portion provided on the mounting substrate 1, and the terminal on the mounting substrate 1 side which is wire-bonded to the bare chip 2 has the convex shape. It is provided on the surface of the part. The side wall of the convex portion is formed as an inclined surface 12 that becomes lower toward the outer periphery, and the sealing material 3 covering the bare chip 1 and the wire 4 for wire bonding is formed so that the outer peripheral edge thereof is located on the inclined surface 12. Is provided.
[0015]
The sealing material 3 is, for example, a thermosetting resin such as an epoxy resin or an ultraviolet-curing resin, and the sealing is performed by applying the sealing material 3 in a fluid state and performing thermosetting or ultraviolet curing. However, when the sealing material 3 is applied on a flat surface without irregularities, the sealing material 2 becomes circular as shown in FIG. 2, and when the application amount of the sealing material 3 is constant, the coating height H and the spread D vary with the thixotropy of the sealing material 3. That is, as shown in FIG. 3, if the thixotropy index is large, the coating height H is large and the coating spread D is small. If the thixoindex is small, the coating height H is small and the coating spread D is large.
[0016]
Here, in order to completely cover not only the bare chip 2 but also the wire 4, it is necessary to secure a sufficient coating height H. In this case, when trying to secure a coating height H of 0.8 mm, When a resin commonly used is used for the encapsulating material 3, the thixotropy is about 1.5, so that the application spread D is 4 to 5 mm.
[0017]
However, the application spread D is a case where the application surface is flat, and when the outer peripheral edge of the sealing material 3 is located on the inclined surface 12 (inclination angle θ) that is lower toward the outer periphery, the application spread D is reduced. can do.
[0018]
That is, the sealing material 3 having the thixotropic index that has the contact angles θr1 and θr2 as shown in FIGS. 4A and 4B on a plane where the inclination angle θ is 0 ° 4 (c) and 4 (d), the contact angles θr1 ′ and θr2 ′, and the contact angles θr1 When θr1 ′ and θr2 ′ are compared with the above contact angles θr1 and θr2, θr1 ′ <θr1 and θr2 ′ <θr2, but when θr1> θr2, the relationship of θr1 ′> θr2 ′ is maintained. The actual contact angles θ + θr1 ′ and θ + θr2 ′ including the inclination angle θ of the inclined surface 12 are respectively θ + θr1 ′> θr1 and θ + θr2 ′> θr2, and the sealing material 3 having the outer peripheral edge positioned on the inclined surface 12 Substantially increases the contact angle (θ + θr) with respect to the plane. As a result, when the application spread D is the same, the application height H of the sealing material 3 can be increased when the outer peripheral edge is positioned on the inclined surface 12. Note that the entire outer peripheral edge of the sealing material 3 does not need to be on the inclined surface 12, and a part thereof may remain on the chip mounting portion 10 surrounded by the inclined surface 12.
[0019]
In addition, the fact that the outer peripheral edge of the sealing material 3 is located on the inclined surface 12 makes it easy to control the spread shape of the coating. That is, when the sealing material (resin) 3 is applied, when the sealing material 3 is applied to the inclined surface 12 closest to the application position as shown in FIG. In the part, the application height H has a margin for the above-mentioned reason, and the flow of the sealing material 3 stops, and if the application amount is increased from this state, the sealing material 3 flows to another flat surface portion, and The whole bare chip 2 is covered as shown in FIG.
[0020]
The flow of the sealing material 3 is controlled by the inclined surface 12 surrounding the chip mounting portion 10, so that the application amount of the sealing material 3 can be easily controlled, and the plating for solder mounting is nearby. Even in the case where there is a pad or the like, the sealing material 3 does not flow to that position, which is advantageous for ensuring quality.
[0021]
FIG. 6 shows another example. This shows that a concave groove 11 surrounding the chip mounting portion 10 is formed on the surface of the mounting substrate 1 and the inner peripheral wall of the concave groove 11 is formed as an inclined surface 12 which becomes lower toward the outer periphery. In this case, since the chip mounting portion 10 on which the bare chip 2 is mounted can be at the same height as the surface of the mounting substrate 1 on which the other surface mounting components 5 are mounted, it is necessary to form a circuit pattern on the surface of the mounting substrate 1. A screen printing method can be applied, and mass productivity is improved.
[0022]
FIG. 7 shows that the boundary between the chip mounting part 10 and the inclined surface 12 on the outer periphery is formed by a gentle curved surface R. Instead of the curved surface R, a chamfered surface may be formed. Further, the curved surface R may be formed by electroplating or electroless plating on the above-mentioned boundary portion as shown in FIG.
[0023]
When the curved surface R or the chamfered surface is provided at the boundary portion, when the sealing material 3 flows to the inclined surface 12 when the sealing material 3 is applied, the inclination angle θ becomes larger as the sealing material 3 progresses. If the speed of the sealing material 3 becomes abrupt, the progress of the sealing material 3 stops, so that there is a margin in the application height of the sealing material 3.
[0024]
As compared with the case where the inclination angle of the inclined surface 12 is constant, the margin of the application height increases as the sealing material 3 flows, and the change in the application spread can be suppressed with respect to the change in the application amount. Control of the amount of application becomes easier. In addition to the curved surface R and the chamfered surface, the inclined surface 12 may, of course, be formed by a plurality of inclined surfaces 12 whose angles gradually become steeper.
[0025]
By the way, as shown in FIG. 8, it is conceivable to mount the bare chip 2 at a position shifted from the center of the mounting portion 2 surrounded by the inclined surface 12, but at this time, the inclination angles of the four circumferential inclined surfaces 12 are the same. Since the height of the sealing material 3 is highest at the center B of the mounting portion, if it is desired to secure the height h1 of the sealing material 3 in the range A near the bare chip 2, the height at the center B is required. h2 (h2> h1) must be ensured, and the amount of resin of the sealing material 3 also increases.
[0026]
However, as shown in FIG. 9, among the inclined surfaces 12 surrounding the periphery of the chip mounting portion 10, the inclined surface 12 close to the bare chip 2, that is, the inclined surface 12 located at a short distance from the highest portion of the sealing material 3. If the inclination angle θn is greater than the inclination angle θf of the other distant inclined surface 12 and becomes the steeply inclined surface 12, the highest part of the sealing material 3 covering the chip mounting portion 10 Can be positioned not on the center of the chip mounting portion 10 but on the bare chip 2. As a result, the amount of resin of the sealing material 3 can be reduced, and at the same time, reliable sealing can be performed.
[0027]
Further, the contact angle θr between the sealing material 3 and the mounting substrate 1 is affected not only by the thixotropy of the sealing material 3 but also by the wettability of the mounting substrate 1 with respect to the sealing material 3. That is, if the wettability is deteriorated, the contact angle θr can be increased, and the height of the sealing material 3 can be increased. From this point, as shown in FIG. 10, a fluororesin 6 is applied to the inclined surface 12 surrounding the chip mounting portion 10 of the mounting substrate 1, or a roughening process for reducing the surface roughness of the inclined surface 12 is performed. If the interfacial free energy with the sealing material 3 is reduced, favorable results can be obtained.
[0028]
The inclination angle θ of the inclined surface 12 may be changed depending on whether a circuit pattern passes through the inclined surface 12. As is clear from the above description, it is preferable that the inclination angle θ is large in terms of increasing the height of the sealing material 3. However, as the inclination angle θ increases, the circuit pattern on the inclined surface 12 increases. Therefore, the inclination angle θ of the inclined surface 12 through which the circuit pattern passes is reduced, and the inclination angle θ of the inclined surface 12 through which the circuit pattern does not pass is increased.
[0029]
As is apparent from the above description, such a semiconductor substrate is provided with a circuit board 1 having an inclined surface 12 which becomes lower toward the outer periphery around a chip mounting portion 10 on which a bare chip is mounted. The surface of the bare chip 2 is mounted on the chip mounting portion 10 of the mounting substrate 1 having the surface formed thereon, and then the sealing material 3 in a fluid state is supplied onto the chip mounting portion 10 to form the sealing material 3. It can be obtained by bringing the outermost peripheral edge to the inclined surface 12 and curing the sealing material 3 in this state. As the mounting substrate 1 used here, one manufactured by the following method is preferably used. Can be.
[0030]
In other words, a resin such as PPA or LCP (liquid crystal polymer) is injection-molded or compression-molded to obtain the mounting substrate 1 having the chip mounting portion 10 and the inclined surface 12 which becomes lower toward the outer periphery. Next, depending on the material and process of the mounting substrate 1, the mounting substrate 1 is annealed at, for example, about 150 to 200 ° C. for about 2 hours. Thereafter, a thin film conductive layer such as a copper thin film having a thickness of about 0.1 to 3 μm is formed on the surface of the mounting substrate 1 by a technique such as sputtering, and then the surface is irradiated with a laser to form a circuit of the thin film conductive layer. The boundary between the portion to be left as a pattern and the non-circuit portion is removed to insulate them. Thereafter, electroplating (for example, copper plating with a thickness of 5 to 20 μm, nickel plating with a thickness of 5 to 20 μm, and gold plating with a thickness of 0.5 μm) is performed on a portion of the thin film conductive layer left as a circuit pattern to form a circuit pattern.
[0031]
In this case, it is easy to form the wiring up to the terminal provided on the chip mounting portion 10 on the inclined surface 12.
[0032]
In each of the above examples, the inclined surface 12 that is lower toward the outer periphery is provided around the chip mounting portion 10. However, instead of the inclined surface 12, a wall surface that extends downward is formed and the bare chip 2 is formed. The outermost peripheral edge of the sealing material 3 covering the above may be located on the wall surface. That is, the inclination angle of the inclined surface 12 may be close to 90 °.
[0033]
【The invention's effect】
As described above, the semiconductor substrate according to the present invention includes a bare chip, a mounting substrate on which the bare chip is surface-mounted, and a sealing material that covers the bare chip mounted on the mounting substrate. The peripheral surface of the chip mounting portion to be mounted is provided with an inclined surface or a wall surface extending downward as the outer periphery is lowered, and the sealing material covering the bare chip has its outermost peripheral edge positioned on the inclined surface or the wall surface. Therefore, it is possible to increase the substantial contact angle (inclination angle of inclined surface + contact angle) of the outer peripheral edge of the sealing material, and therefore, it is necessary to increase the thickness with a small amount of the sealing material. Thus, reliable sealing can be performed.
[0034]
In this case, a concave groove is formed around the chip mounting portion of the mounting substrate, and the inner peripheral wall of the concave groove has an inclined surface that becomes lower toward the outer periphery or a wall surface that extends downward. The outermost peripheral edge of the sealing material may be located at the uppermost position. The surface of the chip mounting portion can be at the same height as the surface of the mounting substrate, which is advantageous in manufacturing.
[0035]
The chip mounting portion of the mounting substrate is provided on the upper surface of the convex portion provided on the mounting substrate, and the peripheral wall of the convex portion has an inclined surface that becomes lower toward the outer periphery or a wall surface that extends downward. The outermost peripheral edge of the sealing material may be located. Three-dimensional component arrangement is possible, which is advantageous for miniaturization.
[0036]
If the boundary between the chip mounting portion and the inclined surface is a chamfered surface or a curved surface, favorable results can be obtained in terms of increasing the contact angle and controlling the flow of the sealing material.
[0037]
If this curved surface is formed by plating applied to the boundary, it is easy to obtain a curved surface at the boundary.
[0038]
In addition, if the inclination angle of the inclined surface that is closer to the highest point of the sealing material is larger than the inclination angle of the inclined surface that is farther from the highest point of the sealing material and the steeply inclined surface, Can easily be located at the portion of the chip mounting portion where the bare chip is located.
[0039]
The method of manufacturing a semiconductor substrate according to the present invention uses a substrate having a sloped surface or a wall surface extending downward around an outer periphery of a chip mounting portion on which a bare chip is mounted as a mounting substrate. The bare chip is surface-mounted on the chip mounting portion of the mounting substrate formed on the substrate, and then a sealing material in a fluid state is supplied on the chip mounting portion, and the outermost peripheral edge of the sealing material is inclined on the inclined surface. Alternatively, the semiconductor substrate having the above characteristics can be easily manufactured because the sealing material is hardened in this state by reaching the wall surface.
[0040]
At this time, a thin-film conductive layer is formed on the surface of the mounting substrate having an inclined surface or a wall surface extending downward around the periphery of the chip-mounting portion, and then formed as a circuit pattern of the thin-film conductive layer by laser. The boundary between the part to be left and the non-circuit part is removed to insulate them, and then the part left as the circuit pattern in the thin film conductive layer is electroplated to form a circuit pattern. The formation of the circuit pattern is also facilitated.
[Brief description of the drawings]
FIGS. 1A and 1B show an example of an embodiment of the present invention, in which FIG. 1A is a sectional view, and FIG. 1B is a partially enlarged sectional view.
2A is a plan view when a sealing material is applied, and FIG. 2B is a side view showing the application height and the application spread when the sealing material is applied.
FIG. 3 (a) is a correlation diagram between the thixotropy of the sealing material and the application height, and FIG. 3 (b) is a correlation diagram between the thixoindex of the sealing material and the application spread.
FIGS. 4 (a), (b), (c) and (d) are explanatory diagrams relating to a contact angle.
FIGS. 5A, 5B, and 5C are explanatory diagrams regarding application of a sealing material according to the first embodiment.
FIG. 6 is a sectional view of another example.
FIGS. 7A, 7B, and 7C are cross-sectional views of still another example.
8A and 8B show another example, in which FIG. 8A is a plan view, FIG. 8B is a sectional view, and FIG. 8C is a sectional view after sealing with a sealing material.
9A and 9B show still another example, in which FIG. 9A is a plan view, FIG. 9B is a sectional view, and FIG. 9C is a sectional view after sealing with a sealing material.
FIGS. 10A and 10B are cross-sectional views of still another example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Mounting board 2 Bare chip 3 Sealant 10 Chip mounting part 12 Inclined surface

Claims (8)

  1. A semiconductor substrate comprising a bare chip, a mounting board on which the bare chip is mounted on the surface, and a sealing material covering the bare chip mounted on the mounting board, wherein the mounting board is provided around a chip mounting portion on which the bare chip is mounted. The outer peripheral edge of the sealing material that covers the bare chip is located on the inclined surface or the wall surface. Semiconductor substrate.
  2. A concave groove is formed around the chip mounting portion of the mounting substrate, and the inner peripheral wall of the concave groove has an inclined surface that becomes lower toward the outer periphery or a wall surface that extends downward, and is sealed on the inclined surface or the wall surface. 2. The semiconductor substrate according to claim 1, wherein an outermost peripheral edge of the material is located.
  3. The chip mounting portion of the mounting substrate is provided on the upper surface of the convex portion provided on the mounting substrate, and the peripheral wall of the convex portion has an inclined surface that is lower toward the outer periphery or a wall surface that extends downward. The semiconductor substrate according to claim 1, wherein an outermost peripheral edge of the sealing material is located.
  4. 4. The semiconductor substrate according to claim 1, wherein a boundary between the chip mounting portion and the inclined surface is a chamfered surface or a curved surface.
  5. 5. The semiconductor substrate according to claim 4, wherein the curved surface is formed by plating applied to the boundary.
  6. The inclination angle of the inclined surface which is closer to the highest point of the sealing material is larger than the inclination angle of the inclined surface which is farther from the highest point of the sealing material, and is a steeply inclined surface. The semiconductor substrate according to any one of Items 1 to 3.
  7. A method of manufacturing a semiconductor substrate, comprising: a bare chip, a mounting board on which the bare chip is surface-mounted, and a sealing material covering the bare chip mounted on the mounting board, wherein the chip mounting includes the bare chip mounted as the mounting board Using a sloped surface or a wall surface that extends downward around the periphery of the part, the surface of a bare chip is mounted on the chip mounting part of the mounting substrate on which the circuit pattern is formed, and then A semiconductor substrate, wherein a sealing material in a fluid state is supplied onto the chip mounting portion so that the outermost peripheral edge of the sealing material reaches the inclined surface or the wall surface, and the sealing material is cured in this state. Manufacturing method.
  8. On a mounting substrate having an inclined surface or a wall surface extending downward on the outer periphery of the chip mounting portion, a thin film conductive layer is formed on the surface, and then a portion to be left as a circuit pattern of the thin film conductive layer by laser. 8. The circuit pattern according to claim 7, wherein a boundary portion between the thin film conductive layer and the non-circuit portion is removed to insulate them, and thereafter, a portion of the thin film conductive layer left as a circuit pattern is electroplated to form a circuit pattern. A method for manufacturing a semiconductor substrate.
JP2002342938A 2002-11-26 2002-11-26 Semiconductor substrate and manufacturing method thereof Pending JP2004179343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002342938A JP2004179343A (en) 2002-11-26 2002-11-26 Semiconductor substrate and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002342938A JP2004179343A (en) 2002-11-26 2002-11-26 Semiconductor substrate and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2004179343A true JP2004179343A (en) 2004-06-24

Family

ID=32704859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002342938A Pending JP2004179343A (en) 2002-11-26 2002-11-26 Semiconductor substrate and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2004179343A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310856A (en) * 2005-04-27 2006-11-09 Samsung Electro Mech Co Ltd Lcd backlight unit using light-emitting diode
JP2008091864A (en) * 2006-09-08 2008-04-17 Nichia Chem Ind Ltd Light emitting device
JP2009532900A (en) * 2006-04-04 2009-09-10 クリー インコーポレイテッドCree Inc. Uniform radiation LED package
WO2010021346A1 (en) * 2008-08-20 2010-02-25 三菱化学株式会社 Semiconductor light emitting device and method for manufacturing the same
WO2012157644A1 (en) * 2011-05-16 2012-11-22 日亜化学工業株式会社 Light-emitting device and method for manufacturing same
JP2013138148A (en) * 2011-12-28 2013-07-11 Nichia Chem Ind Ltd Light-emitting device and manufacturing method thereof
US8558252B2 (en) 2011-08-26 2013-10-15 Cree, Inc. White LEDs with emission wavelength correction
JP2014003151A (en) * 2012-06-18 2014-01-09 Mitsubishi Electric Corp Light emitting device
US8877524B2 (en) 2008-03-31 2014-11-04 Cree, Inc. Emission tuning methods and devices fabricated utilizing methods
US9401461B2 (en) 2007-07-11 2016-07-26 Cree, Inc. LED chip design for white conversion
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310856A (en) * 2005-04-27 2006-11-09 Samsung Electro Mech Co Ltd Lcd backlight unit using light-emitting diode
US8148897B2 (en) 2005-04-27 2012-04-03 Samsung Electro-Mechanics Co., Ltd. Backlight unit for LCD using LED
JP2009532900A (en) * 2006-04-04 2009-09-10 クリー インコーポレイテッドCree Inc. Uniform radiation LED package
US8969908B2 (en) 2006-04-04 2015-03-03 Cree, Inc. Uniform emission LED package
JP2008091864A (en) * 2006-09-08 2008-04-17 Nichia Chem Ind Ltd Light emitting device
US9401461B2 (en) 2007-07-11 2016-07-26 Cree, Inc. LED chip design for white conversion
US10505083B2 (en) 2007-07-11 2019-12-10 Cree, Inc. Coating method utilizing phosphor containment structure and devices fabricated using same
US8877524B2 (en) 2008-03-31 2014-11-04 Cree, Inc. Emission tuning methods and devices fabricated utilizing methods
WO2010021346A1 (en) * 2008-08-20 2010-02-25 三菱化学株式会社 Semiconductor light emitting device and method for manufacturing the same
JP5983603B2 (en) * 2011-05-16 2016-08-31 日亜化学工業株式会社 Light emitting device and manufacturing method thereof
JP2016213492A (en) * 2011-05-16 2016-12-15 日亜化学工業株式会社 Light-emitting device and method for manufacturing the same
CN107768502A (en) * 2011-05-16 2018-03-06 日亚化学工业株式会社 Light-emitting device and its manufacture method
WO2012157644A1 (en) * 2011-05-16 2012-11-22 日亜化学工業株式会社 Light-emitting device and method for manufacturing same
US10090446B2 (en) 2011-05-16 2018-10-02 Nichia Corporation Light emitting device and method for manufacturing the same
CN107768502B (en) * 2011-05-16 2019-07-05 日亚化学工业株式会社 Light emitting device and its manufacturing method
CN103688377A (en) * 2011-05-16 2014-03-26 日亚化学工业株式会社 Light-emitting device and method for manufacturing same
US8558252B2 (en) 2011-08-26 2013-10-15 Cree, Inc. White LEDs with emission wavelength correction
JP2013138148A (en) * 2011-12-28 2013-07-11 Nichia Chem Ind Ltd Light-emitting device and manufacturing method thereof
JP2014003151A (en) * 2012-06-18 2014-01-09 Mitsubishi Electric Corp Light emitting device

Similar Documents

Publication Publication Date Title
CN1143374C (en) Semiconductor device, method of manufacture thereof, circuit board and electronic device
CN1284230C (en) High-frequency module
KR100522223B1 (en) Semiconductor device and method for manufacturing thereof
US7045870B2 (en) Solid image-pickup device and method for manufacturing the solid image pickup device
RU2327311C2 (en) Method of integration of components to plate-base
EP0684641B1 (en) Semiconductor device moulding capable of accomplishing a high moisture proof
US7263768B2 (en) Method of making a semiconductor device having an opening in a solder mask
JP4526651B2 (en) Semiconductor device
CA2340677C (en) Semiconductor package, semiconductor device, electronic device, and method for producing semiconductor package
KR101075241B1 (en) Microelectronic package with terminals on dielectric mass
US5834340A (en) Plastic molded semiconductor package and method of manufacturing the same
US6582991B1 (en) Semiconductor device and method for fabricating the same
US5859471A (en) Semiconductor device having tab tape lead frame with reinforced outer leads
US5874784A (en) Semiconductor device having external connection terminals provided on an interconnection plate and fabrication process therefor
EP0928016B1 (en) Process for manufacturing semiconductor wafer, semiconductor chip, and ic card
US7312533B2 (en) Electronic component with flexible contacting pads and method for producing the electronic component
KR100625632B1 (en) Semiconductor device and method of manufacturing the semiconductor device
EP0684644B1 (en) Method for manufacturing bump leaded film carrier type semiconductor device
JP2010098337A (en) Semiconductor device manufacturing method
US4237607A (en) Method of assembling semiconductor integrated circuit
US7547094B2 (en) Liquid discharge recording head and ink jet recording apparatus
JP3923368B2 (en) Manufacturing method of semiconductor device
JP3945483B2 (en) Manufacturing method of semiconductor device
US6387734B1 (en) Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
KR101376265B1 (en) Wiring board and its fabricating method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050712

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070625

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070828

A02 Decision of refusal

Effective date: 20071225

Free format text: JAPANESE INTERMEDIATE CODE: A02