JP2004157865A - Multiprocessor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system preventing getting wrong data due to simultaneous access when transferring data between processors. <P>SOLUTION: An access bank control register 111 is provided to which control data is written by a first processor 101 determining which of a first bank 103 or a second bank 104 is accessed by own processor 101 or a second processor 102 and the control data can only be read from the second processor 102. Furthermore, a first memory controller 112 is provided making the first or the second processor possible to access only the first bank 103 which is allotted by the control data set to the access bank control register. Moreover, a second memory controller 113 is provided making the first or the second processor possible to access only the second bank 104 which is allotted by the control data set by the access bank control registor. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multiprocessor system in which a plurality of processors share a memory, and more particularly to access control of a memory shared by a plurality of processors.
[0002]
In the ASIC design, the number of cases in which a plurality of processors are incorporated in one chip has been increasing in recent years in order to achieve the functions required by the LSI.
Processors to be incorporated are different processors or different clock frequencies and bus systems (bus architecture, bit width, etc.) in consideration of the required processing capacity and the balance between the processor scale and power consumption. Not a few.
[0003]
In such a case, a method using a memory is considered as one of data transfer means between a plurality of processors, and the following two configuration methods are known as systems.
[0004]
The first method is to develop the memory on a share and place the memory for data exchange on the share.
FIG. 20 is a diagram showing a configuration example of a multiprocessor system employing the first method.
As shown in FIG. 20, the multiprocessor system 10 includes a first processor (PRC-A) 11, a second processor (PRC-B) 12, a shared memory (SRAM) 13 composed of, for example, an SRAM, and a shared bus (SBS). 14, a first processor bus (BS-A) 15, a second processor bus (BS-B) 16, a shared bus bridge (SBRG) 17, and a shared access arbiter (ARBTR) 18.
[0005]
In the multiprocessor system 10 of FIG. 20, a bus from each of the processors 11 and 12 is provided with a bridge circuit 17 for connecting to the shared bus 16, and the memory access itself is expanded on the shared bus 16 to divide access requests in a time-division manner. This is the method of assigning.
[0006]
The second method is a method that is also used in a pre-designed type using a dual-port RAM as a memory for transferring data between processors.
[0007]
FIG. 21 is a diagram illustrating a first configuration example of a multiprocessor system employing the second method.
[0008]
As shown in FIG. 21, the multiprocessor system 20 includes a first processor (PRC-A) 21, a second processor (PRC-B) 22, a first shared memory (SRAM1) It has a second shared memory (SRAM2) 24 composed of a port SRAM, a first processor bus (BS-A) 25, and a second processor bus (BS-B) 26.
[0009]
The multiprocessor system 20 of FIG. 21 is a case where two 1-port / 1-read (1 Write / 1 Read) dual-port SRAMs are used as a shared memory.
In the multiprocessor system 20, the first shared memory 23 is dedicated for writing (writing) from the second processor 22 via the second processor bus 26 and the write port (WPO) 23W, and the read port ( It is configured to function as a read-only RAM via an RPO 23R. Similarly, the second shared memory 24 is dedicated to writing from the first processor 21 via the first processor bus 25 and the write port (WPO) 24W, and from the second processor 22 to the second processor bus 26 and the read port (WPO). It is configured to function as a read-only RAM via an RPO (RPO) 24R.
[0010]
FIG. 22 is a diagram showing a second configuration example of the multiprocessor system employing the second method.
[0011]
The multiprocessor system 20A shown in FIG. 22 is a case where one dual-port SRAM of 2 write / 2 read (2 Write / 2 Read) is used as the shared memory 27.
In the multiprocessor system 20A, the shared memory 27 is read or written by the first processor 22 via the first processor bus 25 and the read / write port (R / WPO) 27RW-1. Data is read or written from the second processor 22 via a read / write port (R / WPO) 27RW-2.
[0012]
Further, as a conventional multiprocessor system, two memories in a shared memory establish a master-slave relationship in a closed functional block called a shared memory, and write / read (Write / Read) from one of the processors. Is compared and transmitted to another processor to guarantee the access data (Patent Document 1).
[0013]
Another conventional multiprocessor system employs an arbitration system that switches access to a shared memory in the order of arrival of requests (Patent Document 2).
[0014]
[Patent Document 1]
JP-A-11-312126
[Patent Document 2]
JP 2000-10901 A
[0015]
[Problems to be solved by the invention]
However, the multiprocessor system shown in FIG. 20 has the following disadvantages.
An arbiter function for bus access must be provided for control when requests overlap. Arbiters become more complex and more difficult to design as the number of processors increases.
Further, since the bus is time-divided, the overhead (inaccessible time) increases as the number of processors increases.
In addition, it is necessary to design the bridge between the bus from each processor and the shared bus in accordance with each processor bus, which increases the design labor.
[0016]
The multiprocessor systems shown in FIGS. 21 and 22 have the following disadvantages.
In each case, the biggest problem is the solution when the write address of one processor and the read address of the other processor overlap.
It is relatively easy to avoid simply avoiding the case where access addresses completely overlap, because it is only necessary to wait for one of them.
However, in a bus system having different access rates, if accesses overlap at a certain moment, a situation occurs in which data update is switched from that moment. To avoid this, the processors must understand each other's access status.
As a solution, it is easy means to determine the access timing of each processor by software. In addition, the dual-port RAM naturally has a larger area (scale) than the single-port RAM. Further, the dual-port RAM often has different functions and access specifications depending on the ASIC vendor and process technology. Even if this example is applied as it is, 1 write / 1 read (1 Write / 1 Read) or 2 write / 2 read ( If there is no dual-write (2Write / 2Read) RAM, the configuration and the specifications of the RAM controller must be reconsidered.
[0017]
Further, in the multiprocessor system described in Patent Literature 1, since two memories in the shared memory have a master-slave relationship in a closed functional block called a shared memory, a bus between the shared memories is required. Since each memory must be accessed and complicated processing such as comparison / transfer processing is required, there is a disadvantage that the degree of freedom and flexibility of access control is poor.
[0018]
Further, the multiprocessor system described in Patent Document 2 must have an arbiter function, similarly to the system of FIG. 20 described above. Therefore, as the number of processors increases, the multiprocessor system becomes more complicated and design becomes difficult.
[0019]
SUMMARY OF THE INVENTION An object of the present invention is to suppress data mix-up due to simultaneous access of write and read from different processors when data is transferred between processors, and have excellent flexibility and flexibility in access control. An object of the present invention is to provide a multiprocessor system that can be easily designed.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a first aspect of the present invention is a multiprocessor system in which a plurality of processors share a memory, wherein the memory includes at least two or more banks and the plurality of processors Is set to determine which one of the plurality of banks is to be accessed. The control data is rewritable control data setting means, and the processor has access to the memory having the bank configuration from each of the processors. When the error occurs, there is provided control means for performing control so that each processor inevitably can access only the bank assigned by the control data set in the control data setting means.
[0021]
In the present invention, the control data set in the control data setting means is such that one of the plurality of banks is accessed by one of the processors, and the other one of the banks is controlled by a different processor. It includes data instructing the control means to accept the access.
[0022]
In the present invention, only one of the plurality of processors has a right to determine access to each bank, and the control data is sent to the control data setting means only from the one processor having the superiority. After the setting, the other processor accesses the bank assigned by the control data set in the control data setting means.
Preferably, the determination of the superiority of the one processor is determined as a chip architecture.
The determination of the superiority of the one processor is controlled by the settings of the processors.
[0023]
Preferably, each of the above-mentioned processors has means for issuing an instantaneous signal to another processor and transmitting information relating to access control.
[0024]
Further, each of the processors has a transmission register that can write and read from its own processor and can only read from another processor, and transmits transmission information relating to access control to another processor. Write to register
[0025]
Preferably, each of the above processors has an interrupt register for issuing an interrupt signal to another processor, and a transmission register that can write and read from its own processor and can only read from another processor. Respectively.
[0026]
Preferably, each of the processors writes transmission information relating to access control to another processor in the corresponding transmission register, and then sets an interrupt signal in the interrupt register to indicate that the other processor has the transmission information. Notify.
[0027]
Preferably, when switching access to the bank from each processor, the control means switches all signals related to the bank, including the clock signal.
Each of the processors operates in synchronization with a different clock.
[0028]
A multiprocessor system according to a second aspect of the present invention includes a first processor, a second processor, a first bank and a second bank in which a shared memory is partitioned, and the first processor and the second bank divided by the first processor. An access bank control register in which control data for determining whether one of the two banks is accessed by the own processor and the second processor is written, and only the control data can be read from the second processor; Alternatively, when an access to the first bank from the second processor occurs, the first or second processor inevitably allocates the data by the control data set in the access bank control register. Memory controller that performs control so that only the first bank can be accessed When an access to the second bank from the first or second processor occurs, the control data set in the access bank control register is inevitably sent from the first or second processor. And a second memory controller for performing control so that only the second bank assigned by the second memory can be accessed.
[0029]
Preferably, a first transfer register capable of writing and changing the content to be transmitted from the first processor to the second processor, and capable of reading the content from the second processor, And a second transmission register capable of writing and changing the content to be transmitted to the first processor and reading the content from the first processor.
[0030]
Preferably, a first transfer register capable of writing contents to be transmitted from the first processor to the second processor and capable of only reading contents from the second processor, A first interrupt signal generation register for issuing an interrupt to two processors; and a second interrupt signal generating register capable of writing contents to be transmitted from the second processor to the first processor and reading only contents from the first processor. 2 transmission register and a second interrupt signal generation register for issuing an interrupt from the second processor to the first processor.
[0031]
Preferably, the first or second processor writes, in the corresponding first or second transmission register, transmission information relating to access control to another second or first processor, and then writes the first or second transmission register. (2) An interrupt signal is set in the interrupt register to notify the other second or first processor that there is information to be transmitted.
[0032]
According to the present invention, for example, the control data for determining which one of the plurality of banks each of the plurality of processors accesses is set in the control data setting means by one processor having superiority. This control data is provided to the control means.
In the control means, when an access to a memory having a bank configuration from each processor occurs, each processor inevitably accesses only the bank assigned by the control data set in the control data setting means. The switching control that can be performed is performed.
Specifically, control is performed so that one of the plurality of banks receives an access from one processor and the other bank receives an access from a different processor.
With this control, the address area of the shared memory viewed from each processor has no distinction between banks on the address map.
[0033]
As described above, according to the present invention, data is guaranteed in a plurality of banks constituting a shared memory by a configuration defining a processor to be accessed at that time, for example, by setting from a processor. As described above, the definition of the access target is made by setting from the processor whose superiority is determined in advance. This superiority itself may be determined as a system specification or may be defined by software.
In addition, since the processor is responsible for switching access rights, the arbitration of access is controlled by software, and it is necessary to switch the order of arrival of requests, as well as the state of the system at the time of the access request. Accordingly, it is possible to increase the degree of freedom such as the timing, order, and order of switching of the access right.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0035]
First embodiment
FIG. 1 is a configuration diagram showing a first embodiment of a multiprocessor system according to the present invention.
In the first embodiment, an example will be described in which two processors are mounted and the bank configuration of the shared memory is two.
[0036]
As shown in FIG. 1, the multiprocessor system 100 includes a first processor (PRC-A) 101, a second processor (PRC-B) 102, a first memory bank (BNK1) 103 composed of a single-port SRAM, for example, A second memory bank (BNK2) 104 composed of a port SRAM, a first processor bus (BS-A) 105, a second processor bus (BS-B) 106, a first interrupt signal generation register (IRPTREG1) 107, a second interrupt signal Generation register (IRPTREG2) 108, first parameter transmission register (TRFREG1) 109, second parameter transmission register (TRFREG2) 110, access bank control register (CTLREG) 111, first memory controller (MCTL1) 112, second memory controller Rollers (MCTL2) 113, and has a local bus 114-127.
Among these components, a control data setting unit is configured by the access bank control register (CTLREG) 111, and a control unit is configured by the first memory controller (MCTL1) 112 and the second memory controller (MCTL2) 113.
[0037]
In the multiprocessor system 100 according to the first embodiment, the first processor 101 can read (read) and write (write) the first parameter transfer register 109 and the access bank control register 111, and The parameter transfer register 110 can be read only (Read Only).
On the other hand, the second processor 102 can only read (Read Only) the first parameter transfer register 109 and the access bank control register 111, and can read and write the second parameter transfer register 110.
[0038]
In the present embodiment, the first processor 101 and the second processor 102 operate in synchronization with clocks having different frequencies. For example, the first processor 101 operates in synchronization with the clock CLK-A, and the second processor 102 operates in synchronization with the clock CLK-B.
In the present embodiment, the bus architecture of the first processor 101 is different from the bus architecture of the second processor.
Also, for example, the first processor 101 and the second processor 102 can be mounted in a form in which the clock frequency is variable and can operate at different frequencies.
[0039]
When an access to the shared memory having the bank configuration from the first and second processors 101 and 102 occurs, the multiprocessor system 100 is inevitably assigned from the processors 101 and 102 at that time. It is configured to perform control so that only the bank in which the data is stored can be accessed. With this control, the address area of the shared memory viewed from each processor has no distinction between banks on the address map.
The setting of the access right to the first and second memory banks (hereinafter, simply referred to as banks) 103 and 104 of the shared memory is performed by one processor (first processor 101 in the present embodiment) whose superiority is determined. And the second processor 102 does not control the memory access right.
As described above, by controlling the access right by the processor setting, the timing control and the order control of the access right switching can be freely controlled by software.
[0040]
The first processor 101 sends one of the two first bank 103 and second bank 104 to the access bank control register 111 via the local bus 114, the first processor bus 105, and the local bus 120. The control data for determining whether or not the processor 101 and the second processor 102 access is written.
The control data written in the access bank control register 111 is read by the second processor 102 via the local bus 121, the second processor bus 106, and the local bus 126. The second processor 102 recognizes an accessible bank based on the read control data.
[0041]
For example, when the first processor 101 allocates the first bank 103 to its own processor 101 and allocates the bank 104 to the second processor 102 for the access bank control register 111, as shown in FIG. Can access (read and write) the bank 103 through the local bus 114, the first processor bus 105, the local bus 122, and the first memory controller 112, and the second processor 102 can use the local bus 126, the second processor The bank 104 can be accessed (read and written) through the bus 106, the local bus 125, and the second memory controller 113.
When data is actually transferred between processors, the first processor 101 is realized by repeatedly performing bank switching based on the control data.
[0042]
The first processor 101 sets a signal with immediacy, in this embodiment, a first interrupt signal, in the first interrupt signal generation register 107 via the local bus 114, the first processor bus 105, and the local bus 115. Issue a first interrupt signal to the second processor 102.
The first processor 101 issues a first interrupt signal to the second processor 102, for example, when starting access to the first bank 103 or the second bank 104, which is a shared memory for data transfer, There is a case where the access to the bank 103 or the second bank 104 is completed and a case where the setting of the access right to the first bank 103 or the second bank 104 is changed.
[0043]
In addition, the first processor 101 sends, to the first parameter transfer register 109, a parameter for transmitting detailed information, such as the status of the own processor and the content of the request, on the local bus 114, the first processor bus 105, and the local bus 116. Write through. The transfer parameters written in the first parameter transfer register 109 are read out by the second processor 102 to which the first interrupt signal is issued, via the local bus 117, the second processor bus 106, and the local bus 126.
The first processor 101 uses the first interrupt signal generation register 107 and the first parameter transmission register 109 together.
Specifically, the first processor 101 issues a corresponding first interrupt signal to the second processor 102 after rewriting the contents of the first parameter transfer register 109. After that, the second processor 102 can read the contents of the first parameter transfer register 109, thereby transmitting detailed information such as the state of the own processor 101 and the contents of the request to the second processor 102.
[0044]
The second processor 102 sets the second interrupt signal in the second interrupt signal generation register 108 via the local bus 126, the second processor bus 106, and the local bus 127, and issues a second interrupt signal to the first processor 101. Issue a signal.
The case where the second processor 102 issues the second interrupt signal to the first processor 101 is, for example, when starting access to the first bank 103 or the second bank 104 which is a shared memory for data transfer. There are times when the access to the bank 103 or the second bank 104 is completed, and times when the access right setting for the first bank 103 or the second bank 104 is to be changed.
[0045]
Further, the second processor 102 transmits, to the second parameter transmission register 110, a parameter for transmitting detailed information such as the state of the own processor and the content of the request, and the like to the local bus 126, the second processor bus 106, and the local bus 119 Write through. The transfer parameters written in the second parameter transfer register 110 are read out by the first processor 101 to which the second interrupt signal is issued, via the local bus 118, the first processor bus 105, and the local bus 114.
The second processor 102 uses the second interrupt signal generation register 108 and the second parameter transmission register 110 together.
Specifically, the second processor 102 issues a corresponding second interrupt signal to the first processor 101 after rewriting the contents of the second parameter transfer register 110. After that, the first processor 101 reads the contents of the second parameter transfer register 110, so that detailed information such as the state of the own processor 102 and the contents of the request can be transmitted to the first processor 101.
[0046]
The first interrupt signal generation register 107 and the access bank control register 111 correspond to a control register of the first processor 101.
[0047]
FIG. 3 is a diagram illustrating a configuration example of a control register of the first processor.
As shown in FIG. 3, this control register is composed of eight bits, bits 0 to 7, and uses only two bits, bit 0 (LSB) and bit 7 (MSB).
Bit 7 is a bit corresponding to the first interrupt signal generation register 107, and bit 0 is a control bit corresponding to the access bank control register 111.
[0048]
Bit 7 (INT) is a bit that generates an interrupt request to the second processor 102 and indicates that data transfer has been completed.
For example, when the bit 7 is set to “0”, it is invalid, and when it is set to “1”, it is when an interrupt request to the second processor 102 is generated. For example, bit 7 automatically returns to "0" after setting "1".
[0049]
Bit 0 (BNK) is a bit that controls which of first bank 103 and second bank 104 is accessed.
FIG. 4 is a diagram showing an example of allocation of two banks to two processors according to control data set in a bank access control bit.
As shown in FIG. 4, for example, in the first embodiment, when the first processor 101 sets “0” as control data in bit 0, the first processor 101 accesses the first bank 103 side. , The second processor 102 accesses the second bank 104 side.
On the other hand, when the first processor 101 sets “1” to the bit 0 as control data, the first processor 101 accesses the second bank 104 and the second processor 102 accesses the first bank 103. .
[0050]
Note that when switching banks, the second processor interface must be on by the second processor interface on register.
[0051]
FIG. 5 is a diagram illustrating a configuration example of the second processor interface on register.
As shown in FIG. 5, the second processor interface on register is composed of eight bits, bits 0 to 7, and uses only bit 0 (LSB).
Bit 0 controls ON / OFF of the second processor interface.
For example, in the present embodiment, as shown in FIG. 6, the second processor interface is off when "0" is written to bit 0, and the second processor interface is on when "1" is written to bit 0. It is.
When the second processor interface is not used, writing “0” to this bit 0 can reduce power consumption in the second processor interface.
[0052]
The second interrupt signal generation register 108 and the access bank control register 111 correspond to a control register of the second processor 102.
[0053]
FIG. 7 is a diagram illustrating a configuration example of a control register of the second processor.
As shown in FIG. 7, this control register is composed of 16 bits of bits 0 to 15, and uses only two bits of bit 0 and bit 7.
Bit 7 is a bit corresponding to the second interrupt signal generation register 108, and bit 0 is a control bit corresponding to the access bank control register 111.
[0054]
Bit 7 (INT) is a bit for generating an interrupt request to the first processor 101.
For example, when the bit 7 is set to “0”, it is invalid, and when it is set to “1”, it is when an interrupt request to the first processor 101 is generated. For example, if bit 7 is set to “1”, it automatically returns to “0” when a pulse is generated.
[0055]
Bit 0 (BNK) is a bit that controls which of first bank 103 and second bank 104 is accessed. This bit 0 is read-only. Therefore, the first bank 103 and the second bank 104 cannot be switched from the second processor 102 side.
FIG. 8 is a diagram illustrating an example of allocation of a selected bank of a shared memory to a second processor according to control data set in a bank access control bit.
As shown in FIG. 8, for example, in the first embodiment, when "0" is set as the control data in bit 0, it is determined that the second bank 104 is selected by the second processor 102. Show.
On the other hand, when “1” is set to the bit 0 as the control data, it indicates that the first bank 103 is selected by the second processor 102.
[0056]
The first memory controller 112 transfers access to the first bank 103 to the first processor 101 connected to the first processor bus 105 according to the control data set in the access bank control register 111 by the first processor 101. Alternatively, switching control is performed so that the second processor 102 is connected to the second processor bus 106.
In the example associated with FIG. 4, when the control data is “0”, the first memory controller 112 sends an access to the first bank 103 to the first processor 101 connected to the first processor bus 105. Switch. On the other hand, when the control data is “1”, the first memory controller 112 switches the access to the first bank 103 to the second processor 102 connected to the second processor bus 106.
The first memory controller 112 switches access to the first bank 103 from the first processor 101 or the second processor 102 by switching all signals related to the first bank 103 including the clock signal. Thus, there is no restriction on the bus system and clock synchronization of the first processor 101 or the second processor 102.
After performing the switching control, the first memory controller 112 controls transmission and reception of addresses, data, control signals, and the like between the first processor 101 or the second processor 102 in charge and the first bank 103.
[0057]
In response to the control data set in the access bank control register 111 by the first processor 101, the second memory controller 113 changes the access to the first bank 103 to the first processor 101 connected to the first processor bus 105. Alternatively, switching control is performed so that the second processor 102 is connected to the second processor bus 106.
In the example associated with FIG. 4, when the control data is “0”, the second memory controller 113 sends an access to the second bank 104 to the second processor 102 connected to the second processor bus 106. Switch. On the other hand, when the control data is “1”, the second memory controller 113 switches the access to the second bank 104 to the first processor 101 connected to the first processor bus 105.
The second memory controller 113 switches all the signals related to the second bank 104 including the clock signal when switching the access from the first processor 101 or the second processor 102 to the second bank 104. Thus, there is no restriction on the bus system and clock synchronization of the first processor 101 or the second processor 102.
After performing the switching control, the second memory controller 113 controls transmission and reception of addresses, data, control signals, and the like between the assigned first processor 101 or second processor 102 and the second bank 104.
[0058]
The first memory controller 112 and the second memory controller 113 having the above functions have basically the same configuration.
[0059]
FIG. 9 is a diagram illustrating a specific configuration example of the memory controller according to the first embodiment.
As shown in FIG. 9, the memory controller 200 (112, 113) includes a first bank controller (BNKCTL-A) 201, a second bank controller (BNKCTL-B) 202, a first switch 203, and a second switch. It has a switch 204.
[0060]
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is performed by the first processor 101, the first bank controller 201 A first bank to be accessed at a predetermined timing upon receiving an address ADR, write data WDT, a control signal WE (Write Enable), an IH (Chip Enable), etc., supplied by the first processor 101 supplied through a bus (BS-A) 105; The data is output to the third bank 103 or the second bank 104, and the data read from the first bank 103 or the second bank 104 is transmitted to the first processor bus (BS-A) 105 at a predetermined timing.
[0061]
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is performed by the second processor 102, the second bank controller 202 Upon receiving an address ADR, write data WDT, control signals WE, IH, and the like from the second processor 102 supplied through the bus (BS-B) 106, the first bank 103 or the second bank 104 to be accessed at a predetermined timing. And outputs the data read from the first bank 103 or the second bank 104 to the second processor bus (BS-B) 106 at a predetermined timing.
[0062]
The first switch 203 has a terminal a connected to a bus 205 connected to an input terminal of the first bank 103 or the second bank 104, and a terminal b connected to an output terminal of the first bank controller 201 on the bank side. The terminal c is connected to a bus 207 connected to a bank-side output terminal of the second bank controller 202.
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is to be performed by the first processor 101, the first changeover switch 203 sets the terminal a, the terminal A is connected, and the address ADR, the write data WDT, the control signals WE, IH, and the like by the first processor 101 sent to the bus 206 by the first bank controller 201 at a predetermined timing are propagated to the bus 205. The input is made to the first bank 103 or the second bank 104.
On the other hand, when the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is performed by the second processor 102, the first switch 203 a and the terminal c are connected, and the address ADR, the write data WDT, the control signals WE, IH, and the like by the second processor 102 sent from the second bank controller 202 to the bus 207 at a predetermined timing are propagated to the bus 205. The input is made to the first bank 103 or the second bank 104.
[0063]
The second switch 204 has a terminal “a” connected to the clock input terminal of the first bank 103 or the second bank 104, a terminal “b” connected to a clock CLK-A supply line for the first processor 101, and a terminal “c” connected thereto. The clock CLK-B for the second processor 102 is connected to a supply line.
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is to be performed by the first processor 101, the second changeover switch 204 sets the terminal The clock CLK-A is input to the first bank 103 or the second bank 104 by connecting the terminal a to the terminal b.
On the other hand, when the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is performed by the second processor 102, the second switch 204 The clock CLK-B is input to the first bank 103 or the second bank 104 by connecting a to the terminal c.
[0064]
As described above, the bank controller 200 according to the present embodiment selects whether the corresponding bank receives control from the first processor 101 or the second processor 102, and also outputs the clock to the bank to each of the banks. A clock synchronized with the processor (bus) is selected and distributed to the banks. Therefore, even if the bus architectures of the two processors are completely different, it is easy to cope with the change and control can be switched regardless of clock synchronization / asynchronization.
[0065]
As described above, the first bank 103 and the second bank 104 constituting the shared memory are constituted by the single-port SRAM.
[0066]
FIG. 10 is a block diagram showing a specific configuration example of a single-port SRAM.
As shown in FIG. 10, the single-port SRAM 300 includes a memory cell array (MCARY) 301, a word line buffer (WLB) 302, a column selector (CSEL) 303, a row decoder (RDEC) 304, a column decoder (CDEC) 305, and an address. Register (AREG) 306, clock buffer (CBUF) 307, pulse generator (PGEN) 308, input data register (IDG) 309, output data buffer (ODB) 310, write amplifier (WAMP) 311, and sense amplifier (SAMP) 312 Having.
In FIG. 10, IA is an address input to the address register 306, CK is a clock input to the clock buffer 307, IH is a low level active chip enable signal, WE is a low level active write enable signal, and I Denotes a data input to the input data register 309, and A denotes a data output from the output data buffer 310, respectively.
[0067]
As shown in FIG. 11, the single-port SRAM 300 has four operation modes: read, write, setup, and standby.
[0068]
As shown in FIG. 11, when the chip enable signal IH is at the high level, the standby mode is set regardless of the levels of the clock CK and the write enable signal WE. At this time, the address IAx is latched in the address register 306, the input data (write data) Ix is latched in the input data register 309, and the data at the time of the previous read is latched in the output data buffer 310.
[0069]
As shown in FIG. 11, when the chip enable signal IH is at low level and the clock CK is at low level, the setup mode is set regardless of the level of the write enable signal WE. At this time, the input address IAx is fetched into the address register 306, the input data (write data) Ix is fetched into the input data register 309, and the data at the previous read is latched in the output data buffer 310.
[0070]
In the read mode, the chip enable signal IH supplied to the clock buffer 307 is at a low level, and the write enable signal WE is at a high level as shown in FIGS.
At this time, as shown in FIGS. 12A, 12B, and 12D, the clock CK is at a low level, and enters the setup mode for a time tSA from the rising timing of the write enable signal WE. The address IAx is fetched.
Then, as shown in FIGS. 12A and 12B, the read mode is set at the rising timing of the clock CK, and the address IAx is latched in the address register 306 during the time tHA from the rising of the clock CK. The address latched by the address register 306 is supplied to the row decoder 304 and the column decoder 305.
The chip enable signal IH, the write enable signal WE, and the clock CK are buffered in the clock buffer 307. Then, the clock CK is supplied to the pulse generator 308 to shape the waveform, and is supplied to the row decoder 304 and the sense amplifier 312.
The row decoder 304 operates in synchronization with the supplied clock CK, decodes a row address from an input address, and supplies the row address to the word line buffer 302. Then, the word line to which the memory cell addressed by the word line buffer 302 is connected is activated for a predetermined time.
The column decoder 305 operates in synchronization with the supplied clock CK, decodes a column address from an input address, and supplies the column address to the column selector 303. Then, the column switch of the bit line to which the addressed memory cell is connected is turned on.
Thereby, the storage data of the addressed memory cell is supplied to the sensor amplifier 312 through the bit line and the column switch, where it is sense-amplified and buffered in the output data buffer 310.
Then, as shown in FIGS. 12A and 12C, after a lapse of a predetermined time tpd from the rise of the clock CK, read data from the memory cell at the current address is output from the output data buffer 310 and becomes valid.
[0071]
In the write mode, the chip enable signal IH supplied to the clock buffer 307 is at a low level, and the write enable signal WE is at a low level as shown in FIGS.
At this time, as shown in FIGS. 13A to 13D, the clock CK is at the low level, and the setup mode is set for a time tSI from the falling timing of the write enable signal WE, and the address IAx is stored in the address register 306. The input data (write data) Ix is input to the input data register 309.
Then, as shown in FIGS. 13A to 13C, the write mode is set at the timing of the rise of the clock CK, and the address IAx is latched in the address register 306 during the time tHA from the rise of the clock CK. The address latched by the address register 306 is supplied to the row decoder 304 and the column decoder 305. Similarly, input data (write data) Ix is latched in input data register 309 during time tHI from the rise of clock CK.
The chip enable signal IH, the write enable signal WE, and the clock CK are buffered in the clock buffer 307. Then, the clock CK is supplied to the input data register 309, and the input data (write data) Ix is held in the input data register 309 as shown in FIGS. Further, the clock CK is supplied to the pulse generator 308 to be shaped, and then supplied to the row decoder 304 and the write amplifier 311.
The address IAx is held in the address register 306 and is supplied to the row decoder 304 and the column decoder 305.
The row decoder 304 operates in synchronization with the supplied clock CK, decodes a row address from an input address, and supplies the row address to the word line buffer 302. Then, the word line to which the memory cell addressed by the word line buffer 302 is connected is activated for a predetermined time.
The column decoder 305 operates in synchronization with the supplied clock CK, decodes a column address from an input address, and supplies the column address to the column selector 303. Then, the column switch of the bit line to which the addressed memory cell is connected is turned on.
The write data held in the input data register 309 is amplified by the write amplifier 311 in synchronization with the clock CK, and is supplied to the column selector 303. As a result, the write data is written to the addressed memory cell through the column switch and the bit line.
In the write mode, as shown in FIG. The output data buffer 310 holds data from the previous read.
[0072]
FIGS. 14A to 14F are timing charts showing timings at which clocks become active in the read mode and the write mode.
FIGS. 15A to 15F are timing charts showing timings at which the clocks in the read mode and the write mode become inhibit.
[0073]
In the read mode, the timing at which the clock CK becomes active is the rising timing of the clock CK during the period when the chip enable signal IH is at the low level, as shown in FIGS.
As shown in FIGS. 14A to 14C, the input address IAx is held in the address register 306 according to the rising timing of the clock CK.
Further, as shown in FIGS. 15A and 15B, in the read mode, the clock is set to the inhibit state while the chip enable signal IH is at the high level.
At this time, as shown in FIG. 14C, the input address IAx is invalid.
[0074]
In the write mode, the clock CK becomes active at a time when the chip enable signal IH and the write enable signal WE are at a low level as shown in FIGS. 14A, 14B, and 14E. It is the rising timing.
As shown in FIGS. 14A to 14E, the input address IAx is held in the address register 306 and the input data Ix is held in the input data register 309 according to the rising timing of the clock CK.
In the write mode, as shown in FIGS. 14A to 14F, the output data of the output data buffer 310 becomes invalid after a lapse of the time tHD from the rising timing of the clock CK.
Further, as shown in FIGS. 15A to 15E, in the write mode, when the chip enable signal IH is at the high level, the write enable signal WE is at the low level, and the clock becomes an inhibit.
At this time, as shown in FIGS. 14C and 14D, the input address IAx and the input data Ix are invalid.
[0075]
Next, the operation of the multiprocessor system of FIG. 1 will be described with reference to FIG.
Here, a description will be made mainly of an information transmission operation by mutually passing an interrupt signal between the first processor 101 and the second processor 102. Then, in order to facilitate understanding, a case where there is data that the first processor 101 wants to transfer to the second processor 102 will be specifically described.
[0076]
First, as a premise, in step ST101, the first processor 101 having superiority in access right control accesses the first bank 103 to the access bank control register 111 (read and write), and the second processor The control data that allows the second 102 to access (read and write) the second bank 104 has been written. The first processor 101 accesses the first bank 103, and the second processor 102 accesses the second bank 104. And normal processing is performed.
[0077]
Here, for example, when there is data that the first processor 101 wants to transfer to the second processor 102, the data transfer bank is the first bank 103.
Accordingly, in step ST102, the first processor 101 accesses the first bank 103 via the first memory controller 112 and writes the transfer data.
[0078]
Next, in step ST103, the first processor 101 accesses the first bank 103 and writes data (parameter) indicating that the transfer data has been written to the first parameter transfer register (TRFREG1) 109 (contents of TRFREG1). To change).
Next, in step ST104, the first processor 101 sets the first interrupt signal in the first interrupt signal generation register 107, and issues the first interrupt signal to the second processor 102.
After issuing the first interrupt signal, the first processor 101 shifts to a normal process.
[0079]
On the other hand, the second processor 102 that has received the first interrupt signal reads the contents of the access bank control register (CTLREG) 111 and the first parameter transfer register (TRFREG1) 109 in step ST201.
Next, in step ST202, the second processor 102 detects the read contents of the access bank control register (CTLREG) 111 and the first parameter transfer register (TRFREG1) 109. In this case, it is detected (recognized) that there is data to be transferred from the first bank 103, that the data has been written to the first bank 103, and that the bank accessible by the second processor 102 is still the second bank 104.
[0080]
Therefore, in step ST203, the second processor 102 transmits data (parameter) indicating that the access right of the bank should be changed from the second bank 104 to the first bank 103 in order to receive (read) the transfer data. Write to the parameter transfer register (TRFREG2) 110 (change the contents of TRFREG2).
Next, in step ST204, the second processor 102 sets the second interrupt signal in the second interrupt signal generation register 108, and issues the first interrupt signal to the first processor 101.
After issuing the second interrupt signal, the second processor 102 shifts to the normal processing.
[0081]
The first processor 101 that has received the second interrupt signal reads the contents of the second parameter transfer register (TRFREG2) 110 in step ST105.
Next, in step ST106, the first processor 101 detects the content of the read second parameter transfer register (TRFREG2) 110. In this case, it is detected (recognized) that it is desired to change the access right of the bank of the second processor 102 from the second bank 104 to the first bank 103.
[0082]
Therefore, in step ST107, the first processor 101 accesses the access bank control register 111 by the own processor 101 (read and write), and the second processor 102 accesses (read and write) the first bank 103. Write) is written.
Next, in step ST108, the first processor 101 accesses (reads and writes) the second bank 104 in the access bank control register 111, and the second processor 102 accesses (reads) the first bank 103 in the access bank control register 111. And write data (parameters) indicating that the control data permitting the write operation is written into the first parameter transfer register (TRFREG1) 109 (change the contents of TRFREG1).
Next, in step ST109, the first processor 101 sets the first interrupt signal in the first interrupt signal generation register 107, and issues the first interrupt signal to the second processor 102.
After issuing the first interrupt signal, the first processor 101 shifts to a normal process.
[0083]
In step ST205, the second processor 102 that has received the first interrupt signal reads the contents of the access bank control register (CTLREG) 111 and the first parameter transfer register (TRFREG1) 109.
Next, in step ST206, the second processor 102 detects the contents of the read access bank control register (CTLREG) 111 and the first parameter transfer register (TRFREG1) 109. In this case, the access bank is switched, and it is detected (recognized) that the second processor 102 can access the first bank 103.
[0084]
Therefore, in step ST207, the second processor 102 accesses the first bank 103 and reads out the transfer data to receive (read) the transfer data.
Next, in step ST208, the second processor 102 writes data (parameters) indicating that access to the first bank 103 has been completed to the second parameter transfer register (TRFREG2) 110 to receive (read) the transfer data. (Change the contents of TRFREG2).
Next, in step ST209, the second processor 102 sets the second interrupt signal in the second interrupt signal generation register 108, and issues the second interrupt signal to the first processor 101.
After issuing the second interrupt signal, the second processor 102 shifts to the normal processing.
[0085]
The first processor 101 that has received the second interrupt signal reads the contents of the second parameter transfer register (TRFREG2) 110 in step ST110.
Next, in step ST111, the first processor 101 detects the content of the read second parameter transfer register (TRFREG2) 110. In this case, the second processor 102 detects (recognizes) that the transferred data has been read and that the data has been transferred.
Then, the first processor 101 shifts to the normal processing.
[0086]
As described above, in the multiprocessor system 100 according to the present embodiment, when data is transferred between the first processor 101 and the second processor 102, the first processor 101 repeatedly performs the bank switching based on the control data. .
Then, the first processor 101 and the second processor 102 use the "parameter transmission register" and the "interrupt generation register" in combination to obtain "what the other processor has done" and "what the other processor has done." Requesting "and" what state the other processor is in ".
[0087]
In the software control, what is meant by the data written in the “parameter transfer register” is defined in the software specification, so that the first processor 101 can firstly set the bank switching. A flow, secondly, a flow when the second processor 102 issues a bank switching request to the processor 102 is determined, and a data transfer system between processors using a shared memory by this circuit can be established.
[0088]
As described above, according to the first embodiment, the first processor 101, the second processor, the first bank 103 and the second bank 104 that divide the shared memory, and the first processor 101 Control data for determining whether one of the first bank 103 and the second bank 104 is accessed by the own processor 101 and the second processor 102 is written, and only the control data can be read from the second processor 102. An access bank control register 111, a first parameter transfer register 109 capable of writing and changing contents to be transmitted from the first processor 101 to the second processor 102, and capable of reading contents from the second processor 102; To issue an interrupt to the second processor 102 from the A first interrupt signal generation register 107, a second parameter transmission register 110 capable of writing and changing the content to be transmitted from the second processor 102 to the first processor 101, and capable of reading the content from the first processor 101; The provision of the second interrupt signal generation register 108 for issuing an interrupt from the second processor 102 to the first processor 101 has the following effects.
[0089]
That is, when data transfer between processors is performed by the shared memory, it is possible to suppress data mix-up due to simultaneous write / read access from different processors.
Further, it is possible to cope with the case where the bus system is different between the processors, and it is also possible to cope with the case where the clock between the processors is asynchronous.
In addition, since the processing flow of the processor associated with the setting change and the parameters associated with the processing can be defined by software, it is possible to flexibly respond after the hardware is fixed. Conversely, the hardware can be fixed early. There are advantages.
Memory access during parallel processing by a plurality of processors can be dynamically switched by mutual transfer of interrupt signals.
Further, the access overhead after switching (the period until the memory can be accessed) is actually only the overhead for switching the clock and is extremely small.
As a result, frequent data transfer between processors by the shared memory becomes possible, and large data transfer can be realized by repetitive processing.
[0090]
When the number of processors becomes three or more and it is desired to reduce the circuit scale, the configuration around the memory can be configured with a minimum (the number of banks: 2).
To increase the access efficiency, it is also possible to increase the number of banks and eliminate inaccessible processors, that is, the maximum number of banks = the number of processors.
As described above, the configuration can be flexibly selected according to the request.
[0091]
Since the switching is performed by the memory controller and the bank, which depend on the architecture of the processor bus, it is possible to easily cope with an increase in the number of processors only by increasing the number of selectors to be selected.
If the number of processors is increased, only the parameter transfer register and the interrupt generation circuit are required unless the bank configuration of the shared memory is selected to increase, so that the circuit scale increase is very small.
Even when the architecture of the bus changes, it is only necessary to deal with the changed memory controller and register on the bus side.
According to the above contents, there is an advantage that re-use by IP conversion can be easily performed.
[0092]
The superiority of the processor may be determined as a chip architecture, or may be controlled by setting between processors.
[0093]
A typical example of the memory constituting the shared memory is a single-port SRMA, but a dual-port SRAM, DRAM, or the like may be used.
The memory constituting the shared memory may be either synchronous or asynchronous.
[0094]
Second embodiment
FIG. 14 is a configuration diagram showing a second embodiment of the multiprocessor system according to the present invention.
[0095]
The difference between the second embodiment and the first embodiment is that the number of processors becomes three. In order to reduce the circuit scale, the configuration around the memory is minimum, that is, the first embodiment is different. As in the embodiment, the number of banks is two.
[0096]
Specifically, a third processor 128 is provided in addition to the first processor 101 and the second processor 102.
As the number of third processors 128 increases, a third interrupt signal generation register (IRPTREG3) 129, a third parameter transmission register (TRFREG3) 130, and a third processor bus (BS-C) 131 are provided.
The first to third interrupt signal generation registers 107, 108, and 129 and the first to third parameter transmission registers 109, 110, and 130 determine the destination of each signal and data by two "other than the own processor". To increase.
[0097]
Specifically, the first interrupt signal set in the first interrupt signal generation register 107 by the first processor 101 is supplied to the second processor 102 and the third processor 128.
The second interrupt signal set by the second processor 102 in the second interrupt signal generation register 108 is supplied to the first processor 101 and the third processor 128.
The third interrupt signal set in the third interrupt signal generation register 129 by the third processor 128 is supplied to the first processor 101 and the second processor 102.
[0098]
The first processor 101 transmits parameters for transmitting detailed information, such as the status of the own processor and the contents of the request, to the first parameter transmission register 109 via the local bus 114, the first processor bus 105, and the local bus 116. Write. The transfer parameters written in the first parameter transfer register 109 are read out by the second processor 102 to which the first interrupt signal is issued, via the local bus 117, the second processor bus 106, and the local bus 126. Similarly, the third processor 128 to which the first interrupt signal is issued reads out via the local bus 132, the third processor bus 131, and the local bus 140.
[0099]
The second processor 102 transmits, to the second parameter transmission register 110, parameters for transmitting detailed information such as the state of the own processor and the contents of the request via the local bus 126, the second processor bus 106, and the local bus 119. Write. The transfer parameters written in the second parameter transfer register 110 are read out by the first processor 101 to which the second interrupt signal is issued, via the local bus 118, the first processor bus 105, and the local bus 114. Similarly, the third processor 128 to which the second interrupt signal is issued reads out via the local bus 133, the third processor bus 131, and the local bus 140.
[0100]
The third processor 128 transmits parameters for transmitting detailed information, such as the status of the own processor and the contents of the request, to the third parameter transmission register 130 via the local bus 140, the third processor bus 131, and the local bus 134. Write. The transfer parameters written in the third parameter transfer register 130 are read out by the first processor 101 to which the third interrupt signal is issued via the local bus 136, the first processor bus 105, and the local bus 114. Similarly, the second processor 106 to which the third interrupt signal is issued reads out via the local bus 135, the second processor bus 106, and the local bus 126.
[0101]
In addition, the first processor 101 stores one of the two first banks 103 and the second banks 104 in the access bank control register 111 via the local bus 114, the first processor bus 105, and the local bus 120. Is written in the control data for determining whether or not the own processor 101 and the second processor 102 access.
The control data written in the access bank control register 111 is read by the second processor 102 via the local bus 121, the second processor bus 106, and the local bus 126. The second processor 102 recognizes an accessible bank based on the read control data.
Similarly, the control data written in the access bank control register 111 is read by the third processor 128 via the local bus 137, the third processor bus 131, and the local bus 140. The third processor 128 recognizes an accessible bank based on the read control data.
[0102]
In addition, the third processor 128 accesses the first bank 103 via the local bus 140, the third processor bus 131, the local bus 138, and the first memory controller 112. Similarly, the third processor 128 accesses the second bank 104 via the local bus 140, the third processor bus 131, the local bus 139, and the memory controller 113.
[0103]
The control data written in the access bank control register 111 is, for example, 3-bit data obtained by adding bits 1 and 2 in addition to bit 0 of the control register shown in FIG.
[0104]
FIG. 18 is a diagram showing an example of allocating two banks to three processors according to control data set in the bank access control bits.
As shown in FIG. 18, for example, in the second embodiment, when the first processor 101 sets “000” as control data in bit 2, bit 1, and bit 0, the first processor 101 The bank 103 is accessed, and the second processor 102 accesses the second bank 104.
In this case, the third processor 128 cannot access the first bank 103 and the second bank 104.
When the first processor 101 sets “001” as control data in bit 2, bit 1, and bit 0, the first processor 101 accesses the second bank 104, and the second processor 102 Access side.
Also in this case, the third processor 128 cannot access the first bank 103 and the second bank 104.
[0105]
When the first processor 101 sets “010” as control data in bit 2, bit 1 and bit 0, the first processor 101 accesses the first bank 103 and the third processor 128 accesses the second bank 104. Access side.
In this case, the second processor 102 cannot access the first bank 103 and the second bank 104.
When the first processor 101 sets “011” as control data in bit 2, bit 1, and bit 0, the first processor 101 accesses the second bank 104 side, and the third processor 128 Access side.
In this case, the second processor 102 cannot access the first bank 103 and the second bank 104.
[0106]
When the first processor 101 sets “100” as control data in bit 2, bit 1, and bit 0, the second processor 102 accesses the first bank 103 side, and the third processor 128 Access side.
In this case, the first processor 101 cannot access the first bank 103 and the second bank 104.
When the first processor 101 sets “101” as control data in bit 2, bit 1, and bit 0, the second processor 102 accesses the second bank 104 side, and the third processor 128 Access side.
In this case, the first processor 101 cannot access the first bank 103 and the second bank 104.
[0107]
The first memory controller and the second memory controller according to the second embodiment have substantially the same functions as those of the first embodiment. However, the first memory controller and the second memory controller are different from the circuits in FIG. Thus, the configuration is such that one bank controller is added.
[0108]
FIG. 19 is a diagram illustrating a specific configuration example of the memory controller according to the second embodiment.
As shown in FIG. 19, the memory controller 400 (112, 113) includes a first bank controller (BNKCTL-A) 401, a second bank controller (BNKCTL-B) 402, and a third bank controller (BNKCTL-C) 403. , A first switch 404, and a second switch 404.
[0109]
When the control data set in the access bank control register 111 indicates that the first bank 103 or the second bank 104 is to be accessed by the first processor 101, the first bank controller 401 Upon receiving an address ADR, write data WDT, control signals WE, IH, and the like from the first processor 101 supplied through the bus (BS-A) 105, the first bank 103 or the second bank 104 to be accessed at a predetermined timing. And outputs the data read from the first bank 103 or the second bank 104 to the first processor bus (BS-A) 105 at a predetermined timing.
[0110]
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is performed by the second processor 102, the second bank controller 402 Upon receiving an address ADR, write data WDT, control signals WE, IH, and the like from the second processor 102 supplied through the bus (BS-B) 106, the first bank 103 or the second bank 104 to be accessed at a predetermined timing. And outputs the data read from the first bank 103 or the second bank 104 to the second processor bus (BS-B) 106 at a predetermined timing.
[0111]
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is performed by the third processor 128, the third bank controller 403 Upon receiving an address ADR, write data WDT, control signals WE, IH, and the like from the third processor 128 supplied through a bus (BS-C) 131, the first bank 103 or the second bank 104 to be accessed at a predetermined timing. And outputs the data read from the first bank 103 or the second bank 104 to the third processor bus (BS-C) 131 at a predetermined timing.
[0112]
The first switch 404 has a terminal a connected to a bus 406 connected to an input terminal of the first bank 103 or the second bank 104, and a terminal b connected to an output terminal of the first bank controller 401 toward the bank. The terminal c is connected to the bus 408 connected to the bank-side output terminal of the second bank controller 402, and the terminal d is connected to the bank-side output terminal of the third bank controller 403. Connected to a bus 409.
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is to be performed by the first processor 101, the first changeover switch 403 sets the terminal a and terminal b are connected, and the first bank controller 401 transmits the address ADR, write data WDT, control signals WE, IH, and the like from the first processor 101 sent to the bus 407 at a predetermined timing to the bus 406. The input is made to the first bank 103 or the second bank 104.
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is to be performed by the second processor 102, the first switch 404 sets the terminal a to The terminal c is connected to the second bank controller 402 to transmit an address ADR, write data WDT, control signals WE, IH, and the like from the second processor 102 sent to the bus 408 at a predetermined timing to the bus 406, and The input is made to the bank 103 or the second bank 104.
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is to be performed by the third processor 128, the first changeover switch 404 sets the terminal a to The terminal d is connected to the third bank controller 403 to transmit the address ADR, the write data WDT, the control signals WE, IH, and the like by the third processor 128 sent to the bus 409 at a predetermined timing to the bus 406, and The input is made to the bank 103 or the second bank 104.
[0113]
The second switch 405 has a terminal a connected to the clock input terminal of the first bank 103 or the second bank 104, a terminal b connected to a supply line of the clock CLK-A for the first processor 101, and a terminal c connected to the terminal c. The terminal d is connected to the supply line of the clock CLK-C for the third processor 128, and the terminal d is connected to the supply line of the clock CLK-B for the second processor 102.
When the control data set in the access bank control register 111 indicates that the access to the first bank 103 or the second bank 104 is to be performed by the first processor 101, the second changeover switch 405 is connected to the terminal The clock CLK-A is input to the first bank 103 or the second bank 104 by connecting the terminal a to the terminal b.
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is performed by the second processor 102, the second switch 405 sets the terminal a The clock CLK-B is input to the first bank 103 or the second bank 104 by connecting to the terminal c.
When the control data set in the access bank control register 111 indicates that access to the first bank 103 or the second bank 104 is to be performed by the third processor 128, the second switch 405 is connected to the terminal a. The terminal d is connected to input the clock CLK-C to the first bank 103 or the second bank 104.
[0114]
As described above, the bank controller 400 according to the second embodiment selects which of the first processor 101, the second processor 102, and the third processor 128 receives control from the corresponding bank, and As for the clock to the bank, a clock synchronized with each processor (bus) is selected and distributed to the bank. Therefore, even if the bus architectures of the three processors are completely different, it is easy to cope with the change and control can be switched regardless of clock synchronization / asynchronization.
[0115]
According to the second embodiment, the same effects as those of the above-described first embodiment can be obtained.
[0116]
As described above, since there are two banks despite the fact that the number of processors is three, some processors cannot be accessed.
In order to eliminate the inaccessible processor, the number of banks of the shared memory may be increased as the number of processors increases.
[0117]
【The invention's effect】
As described above, according to the present invention, when data is exchanged between processors by the shared memory, it is possible to suppress data mix-up due to simultaneous write / read access from different processors.
Further, it is possible to cope with a case where the bus system between processors is different, and to cope with a case where the clock between processors is asynchronous.
In addition, since the processing flow of the processor associated with the setting change and the parameters associated with the processing can be defined by software, it is possible to flexibly respond after the hardware is fixed. Conversely, the hardware can be fixed early. There are advantages.
By mutually passing interrupt signals, it is possible to dynamically switch RAM access during parallel processing by a plurality of processors.
Further, the access overhead after switching (the period until the memory can be accessed) is actually only the overhead for switching the clock and is extremely small.
As a result, frequent data transfer between processors by the shared memory becomes possible, and large data transfer can be realized by repetitive processing.
[0118]
When the number of processors becomes three or more and it is desired to reduce the circuit scale, the configuration around the memory can be configured with a minimum (the number of banks: 2).
To increase the access efficiency, it is also possible to increase the number of banks and eliminate inaccessible processors, that is, the maximum number of banks = the number of processors.
As described above, the configuration can be flexibly selected according to the request.
[0119]
Since the switching is performed by the memory controller and the bank, which depend on the architecture of the processor bus, it is possible to easily cope with an increase in the number of processors only by increasing the number of selectors to be selected.
If the number of processors is increased, only the parameter transfer register and the interrupt generation circuit are required unless the bank configuration of the shared memory is selected to increase, so that the circuit scale increase is very small.
Even when the architecture of the bus changes, it is only necessary to deal with the changed memory controller and register on the bus side.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of a multiprocessor system according to the present invention.
FIG. 2 is a diagram showing an access path when a first bank is assigned to an access bank control register by a first processor and a second bank is assigned to a second processor.
FIG. 3 is a diagram illustrating a configuration example of a control register of a first processor.
FIG. 4 is a diagram showing an example of allocating two banks to two processors according to control data set in a bank access control bit.
FIG. 5 is a diagram illustrating a configuration example of a second processor interface on register.
FIG. 6 is a diagram illustrating a setting example of a second processor interface on register.
FIG. 7 is a diagram illustrating a configuration example of a control register of a second processor.
FIG. 8 is a diagram showing an example of assigning a selected bank of a shared memory to a second processor according to control data set in a bank access control bit.
FIG. 9 is a diagram illustrating a specific configuration example of a memory controller according to the first embodiment.
FIG. 10 is a block diagram illustrating a specific configuration example of a single-port SRAM.
FIG. 11 is a diagram for explaining an operation mode and an input / output state of a single-port SRAM.
FIGS. 12A to 12D are timing charts for explaining processing in a read mode;
FIGS. 13A to 13E are timing charts for explaining processing in a write mode.
14A to 14F are timing charts showing timings at which clocks become active in the read mode and the write mode.
FIGS. 15A to 15F are timing charts showing timings at which a clock in a read mode and a write mode becomes an inhibit;
FIG. 16 is a diagram for explaining the operation of the multiprocessor system of FIG. 1;
FIG. 17 is a diagram showing a second embodiment of the multiprocessor system according to the present invention.
FIG. 18 is a diagram showing an example of allocating two banks to three processors according to control data set in a bank access control bit.
FIG. 19 is a diagram illustrating a specific configuration example of a memory controller according to a second embodiment;
FIG. 20 is a diagram illustrating a configuration example of a multiprocessor system employing a first conventional method.
FIG. 21 is a diagram illustrating a first configuration example of a multiprocessor system employing a second conventional method.
FIG. 22 is a diagram showing a second configuration example of a multiprocessor system employing a second conventional method.
[Explanation of symbols]
100, 100A multiprocessor system, 101 first processor (PRC-A), 102 second processor (PRC-B), 103 first memory bank (BNK1), 104 second memory bank (BNK2), 105: first processor bus (BS-A), 106: second processor bus (BS-B), 107: first interrupt signal generation register (IRPTREG1), 108: second interrupt signal generation register (IRPTREG2), 109 ... 1st parameter transfer register (TRFREG1), 110 ... second parameter transfer register (TRFREG2), 111 ... access bank control register (CTLREG), 112 ... 1st memory controller (MCTL1), 113 ... 2nd memory controller (MCTL2), 114-127: Loka Bus 128, third processor (PRC-C), 129 third interrupt signal generation register (IRPTREG3), 130 third parameter transmission register (RTFREG3), 131 third processor bus (BS-C) 132- 141 local bus, 200 memory controller, 201 first bank controller (BNKCTL-A), 202 second bank controller (BNKCTL-B), 203 first switch, 204 second switch, 400 Memory controller, 401: first bank controller (BNKCTL-A), 402: second bank controller (BNKCTL-B), 403: third bank controller (BNKCTL-C), 404: first changeover switch, 405: second Selector switch.

Claims (15)

A multiprocessor system in which a plurality of processors share a memory,
The memory includes at least two or more banks,
Each of the plurality of processors is set with control data for determining which of the plurality of banks to access, and the control data is rewritable control data setting means;
When an access to the memory having the bank configuration occurs from each processor, each processor inevitably accesses only the bank assigned by the control data set in the control data setting means. And a control means for performing control so as to be possible. The control data set in the control data setting means is such that one of the plurality of banks receives access from one of the processors and the other one of the banks receives access from a different processor. 2. The multiprocessor system according to claim 1, further comprising data for instructing said control means. Only one of the plurality of processors has the right to determine access to each bank, and sets the control data to the control data setting means only from the one processor having the superiority,
2. The multiprocessor system according to claim 1, wherein the other processor accesses a bank assigned by the control data set in the control data setting means. 4. The multiprocessor system according to claim 3, wherein said superiority of said one processor is determined as a chip architecture. 4. The multiprocessor system according to claim 3, wherein the determination of the superiority of the one processor is controlled by setting between the processors. 2. The multiprocessor system according to claim 1, wherein each of said processors has means for issuing an instantaneous signal to another processor and transmitting information relating to access control. Each of the above processors has a transmission register that can write and read from its own processor and can only read from another processor,
2. The multiprocessor system according to claim 1, wherein transmission information relating to access control to another processor is written in the corresponding transmission register. Each of the processors includes an interrupt register for issuing an interrupt signal to another processor,
2. The multiprocessor system according to claim 1, further comprising a transmission register capable of writing and reading from its own processor and only reading from another processor. Each of the processors writes transmission information relating to access control to another processor to the corresponding transmission register,
9. The multiprocessor system according to claim 8, wherein an interrupt signal is set in the interrupt register to notify other processors that there is transmission information. 2. The multiprocessor system according to claim 1, wherein said control means switches all signals related to the bank, including a clock signal, when switching access to the bank from each processor. 10. The multiprocessor system according to claim 9, wherein each of the processors operates in synchronization with a different clock. A first processor;
A second processor;
A first bank and a second bank dividing the shared memory;
The first processor writes control data for determining whether one of the first bank and the second bank is accessed by the own processor and the second processor, and only reads control data from the second processor. An access bank control register capable of
When an access to the first bank from the first or second processor occurs, the first or second processor inevitably receives control data set in the access bank control register. A first memory controller that performs control so that only the assigned first bank can be accessed;
When the first or second processor accesses the second bank, the first or second processor inevitably receives the control data set in the access bank control register. A multiprocessor system having a second memory controller that performs control so that only the assigned second bank can be accessed. A first transmission register capable of writing and changing the content to be transmitted from the first processor to the second processor, and capable of reading the content from the second processor;
13. The multiprocessor system according to claim 12, further comprising a second transmission register capable of writing and changing contents to be transmitted from said second processor to said first processor, and capable of reading contents from said first processor. A first transmission register capable of writing content to be transmitted from the first processor to the second processor, and capable of only reading content from the second processor;
A first interrupt signal generation register for issuing an interrupt from the first processor to the second processor;
A second transfer register capable of writing contents to be transmitted from the second processor to the first processor and capable of only reading contents from the first processor;
13. The multiprocessor system according to claim 12, further comprising a second interrupt signal generation register for issuing an interrupt from said second processor to said first processor. The first or second processor writes, in the corresponding first or second transmission register, transmission information relating to access control to another second or first processor,
15. The multiprocessor system according to claim 14, wherein an interrupt signal is set in said first or second interrupt register to notify that said other second or first processor has transmission information.

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