JP2004127123A - Data transmitter, data transmission method, program, storage medium, data receiver and data reception method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce costs and enhance compatibility of a disk drive. <P>SOLUTION: The disk drive 1 which transmits data read from a disk and held in a buffer RAM to a D/A converter 10 determines data quantity to be stored in a packet based on a control signal CNT to be transmitted from the D/A converter 10. In addition, the control signal CNT is the one for instructing variability of data transfer rate according to D/A conversion processing speed. Then, the disk drive is constituted so that data for the determined data quantity is read from the buffer RAM, the packet is generated and transmitted to the D/A converter 10. In the case of this packet transmitting operation, the data transfer rate from the disk drive 1 becomes the one conforming to speed of D/A conversion processing of the D/A converter 10. Thus, as the disk driver 1, structure for continuously reproducing the data from the disk, for example, by providing a circuit for generating a master clock, etc. becomes unnecessary. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data transmission device and method for transmitting digital data, for example, a program executed by such a data transmission device, and a storage medium on which the program is stored. In addition, the present invention relates to a data receiving device and a method corresponding to such a data transmitting device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, audio discs, such as a CD-DA (Digital Audio) on which audio data is recorded, are widely used as disc media. Further, with the spread of, for example, DVDs, disk media on which video data having a larger capacity than audio data is recorded have also become widespread. The audio data and video data recorded on such a disk medium are different from, for example, data of a file such as a document or a still image generally handled by a personal computer or the like, and are continuously reproduced so that temporal continuity is maintained. Data to be done.
[0003]
FIG. 12 shows a configuration example of a system for reproducing audio data recorded on a CD-DA as an example of a system for reproducing a disk medium on which audio data and video data are recorded as described above.
In this figure, a disk drive 100 capable of reproducing a CD-DA, and data reproduced from the CD-DA by the disk drive 100 are input via a data transmission path, for example, D / A converted and converted into an analog audio signal. Is output.
[0004]
The disk drive 100 shown in this figure includes a disk reproducing unit 101 and a clock generator 102.
In this case, the disc reproducing unit 101 performs EFM demodulation processing, error correction processing by CIRC, and the like on the signal read from the CD-DA by, for example, an optical pickup, and a format in which the sampling frequency is 44.1 KHz and the sampling bit is 16 bits. To play digital audio data.
In this case, the reproducing process in the disk reproducing unit 101 is executed at a timing based on the master clock MCL supplied from the clock generator 102. The clock generator 102 is configured to generate a master clock MCL based on a frequency signal of crystal oscillator accuracy generated by a crystal oscillator 102a as shown in the figure.
[0005]
The digital audio signal reproduced by the disk reproducing unit 101 is transmitted and output to the D / A converter 110 via the digital data transmission line LN.
In this case, for example, IEC60958 is adopted as the digital data transmission line LN.
[0006]
When the digital data transmission line LN is IEC60958, the disc reproducing unit 101 performs bi-phase modulation on the reproduced digital audio data and outputs it as stream data, as is well known.
[0007]
The D / A converter 110 includes a D / A conversion processing unit 111 and a PLL circuit 112.
The D / A conversion processing unit 111 performs D / A conversion on the digital audio data input from the digital data transmission line LN and outputs it as an analog audio signal. The D / A conversion processing unit 111 executes the D / A conversion processing at a timing based on the master clock MCL generated by the PLL circuit.
[0008]
The PLL circuit 112 extracts a clock component (time information) included in the digital audio data stream input from the digital data transmission line LN. Then, based on the clock component, a master clock MCL synchronized with the digital audio data input from the digital data transmission line LN is generated and supplied to the D / A conversion processing unit 111.
[0009]
In recent years, IEEE 1394 has become widespread as an interface for digital data. As is well known, the IEEE 1394 data interface is not a stream transmission but a packet transmission. However, even with such an IEEE 1394 data interface, data transmission is performed such that temporal continuity of digital audio data is maintained. It is possible.
[0010]
FIG. 13 shows a configuration example of a CD reproduction system corresponding to a case where an IEEE 1394 data interface is adopted as the digital data transmission line LN. The system configuration shown in this figure includes a disk drive 100A and a D / A converter 110A. In this figure, the same parts as those in FIG.
The disk drive 100A includes a VCO (Voltage Controlled Oscillator) 103. As is well known, the VCO 103 forms a PLL circuit that receives the EFM signal read from the CD-DA in the disk reproducing unit 101 and generates a clock.
That is, the disk drive 100A is provided with a PLL circuit that receives the EFM signal reproduced from the CD-DA by the disk reproducing unit 101 and generates a clock. As is well known, the disk rotation servo control operation in the disk reproducing unit 101 is performed based on a frequency signal output from the VCO 103. The demodulation of the signal read from the CD-DA is executed at a timing based on the master clock MCL generated from the oscillation signal output from the VCO 103.
[0011]
In this case, the digital audio data reproduced by the disk reproducing unit 101 is input to the interface unit 104 corresponding to the IEEE 1394 data interface. The interface unit 104 packetizes the input data according to an isochronous packet format. Then, the isochronous packets are sequentially transmitted to the D / A converter 110A via the digital data transmission line LN at a predetermined timing.
[0012]
The D / A converter 110A in this case includes a clock generator 114 as a circuit part for generating the master clock MCL. The clock generator 114 generates a master clock MCL with crystal oscillator accuracy using the oscillation frequency of the crystal oscillator 114a, and supplies the master clock MCL to the D / A conversion processing unit 111.
[0013]
The D / A conversion processing unit 111 performs signal processing at a timing based on the master clock MCL having the above-described crystal oscillator accuracy. In this case, the D / A conversion processing unit 111 includes a buffer RAM 113 as a work area in response to data transmission via the digital data transmission path LN being packet transmission.
The D / A conversion processing unit 111 receives and inputs an isochronous packet transmitted from the digital data transmission line LN, extracts digital audio data from the isochronous packet, writes the digital audio data in the buffer RAM 113, and holds the buffer RAM 113. Note that writing / reading to / from the buffer RAM 113 in this case is performed so as to obtain an operation as a so-called ring buffer.
Then, the D / A conversion processing unit 111 continuously reads the data written and accumulated in the buffer RAM 113 in accordance with the timing of the master clock MCL supplied from the clock generator 114, and executes the D / A conversion processing. And outputs it as an analog audio signal.
[0014]
In addition, the D / A conversion processing unit 111 detects the remaining amount of the buffer RAM 113 when writing / reading data to / from the buffer RAM 113 as described above. Then, based on the detected remaining amount, a control signal CNT for controlling the data transfer rate transmitted from the disk drive 100A side is generated so that the buffer RAM 113 does not overflow or underflow, and is sent to the disk drive 100A side. Send and output. Note that the remaining amount of the buffer RAM 113 corresponds to the data processing speed (timing) in the D / A conversion processing unit 111. That is, a state in which the remaining amount increases and approaches an overflow corresponds to a state in which the data processing speed in the D / A conversion processing unit 111 is slow. A state in which the remaining amount is decreasing and approaching an underflow corresponds to a state in which the data processing speed in the D / A conversion processing unit 111 is increasing.
[0015]
The disk drive 100A operates so that the master clock MCL generated based on the oscillation frequency of the VCO 103 varies within a range of, for example, ± 1% according to the received control signal CNT.
In this manner, by changing the master clock MCL of the disk drive 100A, the disk rotation speed is changed in the disk playback unit 101, and the signal processing speed for signals read from the disk is also reduced to the disk rotation speed. It will be changed correspondingly. Thereby, the data rate of the digital audio data reproduced by the disk reproducing unit 101 is changed.
[0016]
In the interface unit 104, the input digital audio data is packetized and transmitted and output as an isochronous packet. However, in response to the input of the digital audio data at the data rate varied as described above, For example, the data size of digital audio data to be stored in an isochronous packet to be transmitted at regular intervals is changed.
As a result, the data transfer rate per unit time of the data transmitted from the disk drive 100A to the D / A converter 110A can be varied. Thus, overflow and underflow in the buffer RAM 113 of the D / A converter 110A are prevented from occurring. As a result, the D / A conversion processing unit 111 can continuously read data from the buffer RAM 113 and continue the process of D / A conversion, and the D / A conversion processing unit 111 Is maintained so that the analog audio signal is output.
[0017]
Here, comparing the system configuration shown in FIGS. 12 and 13 with the configuration for synchronizing the disk drive and the D / A converter, the following can be said.
First, in the system shown in FIG. 12, on the disk drive 100 side, data is continuously read from the CD-DA and transmitted to the D / A converter 110 by the master clock MCL fixed with the crystal oscillator accuracy. The / A converter 110 is configured to generate a master clock MCL synchronized with transmitted digital audio data and execute signal processing.
[0018]
On the other hand, in the case of the system shown in FIG. 13, in the disk drive 100A, digital audio is continuously output from the CD-DA in synchronization with the disk rotation speed by the master clock MCL generated by the PLL circuit (VCO 103). The data is reproduced and transmitted to the D / A converter 110A.
On the D / A converter 110A side, signal processing such as D / A conversion processing is executed by a master clock MCL fixed with crystal oscillator accuracy. Then, in the D / A converter 110A, the master clock MCL (oscillation frequency of the VCO 103) on the disk drive 100A side is varied according to the remaining amount of the buffer RAM 113, and the disk reproduction speed (that is, the data transfer speed to the D / A converter 110A) is changed. ). That is, the disk playback speed is synchronized with the processing timing of the D / A converter 110A.
[0019]
That is, in the system configuration shown in FIG. 12, the disk drive 100 is a clock master, and the D / A converter 100 is configured to execute signal processing in synchronization with the data transfer speed transmitted from the disk drive 100. .
On the other hand, in the system shown in FIG. 13, the D / A converter 110A side is used as a clock master, and the disk drive 100A side synchronizes with the processing timing of the D / A converter 110A so as to synchronize the data transfer speed. Is made to be variable.
[0020]
[Problems to be solved by the invention]
As described above, the systems shown in FIG. 12 and FIG. 13 have the difference that the devices that become the clock masters are different from each other. However, in each of the disk drives 100 and 100A, the disk reproducing unit 101 The common point is that digital audio signals are continuously read from the CD-DA and reproduced and output at processing timing based on the master clock MCL.
Such a configuration of the disc reproducing unit 101 is, for example, a configuration employed in a conventional CD player or the like because it is necessary to continuously reproduce digital audio signals.
[0021]
On the other hand, in recent years, mounting a disk drive on a personal computer, such as a CD-ROM drive, has become widespread.
However, the disk drive mounted on the personal computer as described above is originally configured to read data as a file recorded on a CD-ROM or the like. It is not assumed that data required to be continuously reproduced is read.
For this reason, the basic configuration of a disk drive mounted on a personal computer includes an operation of reading data from a loaded disk in a predetermined data unit and transferring the data to a RAM, a cache memory, or the like by packet transmission, for example. Has been to be. In other words, there is no need to continuously reproduce data from the disk in synchronization with the master clock as in the disk drives 100 and 100A shown in FIG. 12 or FIG. 13, so that the clock generator 102 and the VCO 103 ( A circuit portion for generating the master clock MCL, such as a PLL circuit, is not originally provided.
[0022]
As a current personal computer, it is possible to continuously reproduce digital audio data from a CD-DA using a disk drive such as the above-described CD-ROM drive.
However, this is possible because, in order to cope with continuous reproduction of CD-DA and the like, a clock generator and a PLL circuit as described above are additionally provided to continuously read a signal read from a disk. This is because it is configured to be reproducible.
[0023]
In other words, under the present circumstances, in order to continuously reproduce digital audio data by a disk drive such as a CD-ROM drive that performs a data read operation that does not require a master clock and that originally supports packet transmission, the above-described method is used. Thus, a circuit for generating a master clock is additionally provided.
[0024]
In this case, first, there is a problem that the cost of the device as a disk drive is increased by adding a circuit for generating a master clock.
[0025]
In recent years, not only CD-DAs, but also DVD media of various formats, and types of disk media tend to increase. Various types of digital audio data and digital video data can be recorded on such various types of discs as data to be continuously reproduced.
However, the frequency of the master clock at the time of continuously reproducing data differs between the various types of disks described above according to the data format, the disk format, and the like.
For this reason, when adopting a configuration in which data can be continuously played back by a disk drive in correspondence with various types of disk media, masters having different frequencies according to the standards for the corresponding disk media and data format are used. The configuration must be such that a clock can be generated. Specifically, for example, a plurality of clock generators and PLL circuits are provided so that a master clock corresponding to each disk medium or data format is generated, or a circuit that divides a plurality of clocks is provided. .
[0026]
As described above, even if a disk drive capable of continuously reproducing data is adapted to various disk media, it is necessary to adopt a configuration corresponding to a master clock having various frequencies as described above.
It is actually difficult to adopt such a configuration, and even if it is realized, the cost also increases. In addition, it is very difficult in practice to respond to a disk or digital audio / video data in a newly defined format because of the additional change of hardware. In other words, the conventional disk drives capable of continuous reproduction have poor compatibility, and lack expandability and versatility such as support for new formats.
[0027]
[Means for Solving the Problems]
Therefore, the present invention is configured as follows as a data transmission device in consideration of the above-described problem.
That is, a receiving means which receives a control signal transmitted from the data receiving apparatus to enable continuous reproduction of digital data by the data receiving apparatus and which controls a data transfer rate of data to be transmitted by the data transmitting apparatus. Reading means for reading digital data in a predetermined data unit from a recording medium, storage means for temporarily storing and holding digital data read by the reading means, and a control signal received by the receiving means, Determining means for determining the amount of data to be stored in the packet; and a packet for reading the digital data of the amount of data determined by the determining means from the storage means and storing the read data in the packet to generate a packet. Generating means for receiving the packet generated by the packet generating means, It was possible to configure the data transmitting apparatus and a transmitting means for transmitting to the device.
[0028]
The data transmission method is configured as follows.
That is, a receiving procedure for receiving a control signal transmitted from the data receiving apparatus to enable continuous reproduction of digital data in the data receiving apparatus and for controlling a data transfer rate of data to be transmitted from the data transmitting apparatus. A read control procedure for reading digital data from a recording medium in a predetermined data unit, a storage control procedure for temporarily holding digital data read by the read control procedure in a storage area, and a reception procedure Determining a data amount to be stored in the packet in accordance with the control signal received by the controller, reading digital data of the data amount determined by the determining procedure from the storage area, and storing the read data in the packet A packet generation procedure for generating a packet in accordance with The made packets configured to perform a transmission step of transmitting to said data receiving device.
[0029]
In addition, the program includes a control signal transmitted from the data receiving device to enable continuous reproduction of digital data in the data receiving device, and for controlling a data transfer rate of data to be transmitted from the data transmitting device. A receiving procedure for receiving, a read control procedure for reading digital data from the recording medium in a predetermined data unit, and a storage control procedure for temporarily holding digital data read by the read control procedure in a storage area A determining procedure for determining the amount of data to be stored in the packet in accordance with the control signal received in the receiving procedure; and reading out the digital data of the amount of data determined by the determining procedure from the storage area, Packet generation procedure for generating a packet by storing the The generated packet was be configured to perform a transmission step of transmitting to said data receiving device to the data transmission device by preparative generation procedure.
[0030]
Further, the program according to the present invention is stored as a storage medium of the present invention.
[0031]
According to each of the above configurations, the data transmitting apparatus according to the present invention reads out data to be continuously reproduced recorded on the recording medium, temporarily stores the data in the storage means, and reads out the data from the storage means (storage area). A configuration for transmitting by packet transmission is adopted. Then, the data transmitting device receives the control signal transmitted from the data receiving device side, and directly varies the amount of data to be stored in the packet according to the control signal. Thus, the data transfer speed is adapted to the speed timing of the process for continuous data reproduction on the data receiving device side.
With such a configuration, it is not necessary to adapt the data rate of reading data from the recording medium in the data transmitting device to the speed timing of the process for continuous data reproduction on the data receiving device side. That is, it is only necessary to have a function of reading data from the recording medium in a predetermined data unit and transferring the data to the storage means.
[0032]
Further, the data receiving device is configured as follows.
That is, receiving means for receiving a packet transmitted from the data transmitting apparatus, and data stored in the packet received by the receiving means are sequentially input, and continuous reproduction of the input data is performed at a timing based on the master clock. Demodulation means for performing demodulation processing to be performed, signal processing means for performing modulation processing so that an input signal becomes continuous data at a timing based on the master clock, and a signal obtained by the signal processing means. A transmission in which packets generated by storing data of a required data amount are sequentially transmitted at predetermined timing to the data transmission device as control signals for controlling the data transfer rate of data to be transmitted by the data transmission device. Means.
[0033]
The data receiving method is configured as follows.
A reception procedure for receiving a packet transmitted from the data transmission apparatus, and data stored in the packet received by the reception procedure are sequentially input, and the input data is continuously reproduced at a timing based on the master clock. A demodulation procedure for performing demodulation processing, a signal processing procedure for performing modulation processing so that an input signal becomes continuous data at a timing based on the master clock, and data obtained by the signal processing procedure are performed. Transmitting a packet generated by storing a required amount of data as a control signal for controlling a data transfer rate of data to be transmitted by the data transmitting device to the data transmitting device sequentially at a predetermined timing; and To be executed.
[0034]
According to the above configuration, the data receiving apparatus continuously reproduces (demodulates) data received as a packet at a timing based on the master clock. The control signal for controlling the data transfer rate of the data to be transmitted by the data transmitting device includes a sequence of packets storing continuous data obtained by performing a modulation process based on the same master clock as in the continuous reproduction. It becomes.
In this case, since the demodulation processing for continuous reproduction and the modulation processing are performed based on the same master clock, they are in synchronization with each other. Then, on the data transmitting device side, if its own data transfer speed is varied, for example, in accordance with the data transfer speed as this control signal, as a result, it corresponds to the speed timing of the demodulation processing on the data receiving device side. It can be a data transfer rate.
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described. The following description will be made in the following order.
1. First embodiment
1-1. System configuration
1-2. Isochronous packet
1-3. Disk drive packet transmission operation
1-3-1. Packet transmission operation (blocking transmission)
1-3-2. Packet sending operation (non-blocking transmission)
1-3-3. Function processing for packet transmission
1-3-4. Data size determination processing (blocking transmission)
1-3-5. Data size determination processing (non-blocking transmission)
2. Second embodiment
[0036]
1. First embodiment
1-1. System configuration
FIG. 1 shows a configuration example of a data reproduction system according to a first embodiment of the present invention. The data reproduction system shown in this figure has a configuration capable of reproducing an SACD (Super Audio CD).
SACD is a medium using a 1-bit digital audio signal system (DSD: Direct Stream Digital) using ΣΔ modulation. This DSD signal has a sampling frequency of 2.8224 MHz, which is 64 times higher than the sampling frequency fs (fs = 44.1 KHz) of the digital audio signal recorded on the CD-DA, and is ΔΣ modulated 1-bit quantization. Digital audio signal. The frequency band is a wide range from a DC component to 100 KHz, and enables signal reproduction beyond the audible frequency band. The dynamic range is a data format that can realize 120 (dB) over the entire audio band.
[0037]
The data reproduction system shown in FIG. 1 includes a disk drive 1 and a D / A converter 10.
The disk drive 1 includes a disk reproducing unit 2, a system controller 3, a buffer RAM 4, and an interface unit 5.
The disc reproducing unit 2 has a configuration in which a signal can be read in accordance with the SACD. However, the disc reproducing unit 2 does not have a function of continuously reproducing a digital audio signal (DSD signal) recorded on the SACD. That is, no clock generator or PLL circuit for generating a master clock required for continuous reproduction of the DSD signal is provided.
[0038]
The disc reproducing unit 2 reads a signal recorded on the SACD in a fixed data unit, and performs EFM-Plus demodulation (right to fourteen demodulation Plus) corresponding to the SACD format on the signal thus read. And a decoding process such as an error correction process based on a product code is performed. Then, in this case, the reproduced data after the decoding process is transmitted to the system controller 3.
In this case, the data reading and decoding processing by the disk reproducing unit 2 is executed at least at a double speed higher than the normal speed. Further, the reading of data from the disk by the disk reproducing unit 2 can be executed intermittently.
[0039]
The system controller 3 writes the reproduced data transmitted from the disk reproducing unit 2 to the buffer RAM 4 to temporarily store the data. That is, the reproduction data transmitted from the disk reproduction unit 2 is temporarily stored in the buffer RAM 4. In this case, the system controller 3 executes writing / reading control on the buffer RAM 4 so that the buffer RAM 4 can operate as a so-called ring buffer.
[0040]
Further, the system controller 3 reads out the reproduction data accumulated in the buffer RAM 4 as described above at a required timing, transfers the read data to the interface unit 5, and instructs the transmission of the reproduction data. The interface unit 5 transmits reproduced data to the D / A converter 10 via the digital data transmission line LN.
[0041]
Here, in the present embodiment, transmission of reproduction data through the digital data transmission line LN is performed by isochronous (Isochronous) communication using an IEEE1394 data interface. As is well known, the isochronous communication according to IEEE 1394 is a communication method that guarantees that a required data size is periodically transmitted and received. When transmitting data to be continuously reproduced, such as a digital audio signal and a digital video signal, it is common to store the data in an isochronous packet and packetize the data, and perform data transmission in units of the isochronous packet. On the other hand, a method of performing asynchronous communication irrespective of the cycle of isochronous communication is referred to as asynchronous communication.
[0042]
Transmission of reproduced data by isochronous communication under such an IEEE 1394 data interface is roughly as follows.
As described above, the buffer RAM 4 stores the reproduction data reproduced from the SACD. At a predetermined timing, the system controller 3 reads out the required amount of reproduced data required for packetization from the data stored in the buffer RAM 4. Then, the read data thus read is transmitted to the interface unit 5 to instruct transmission.
In the interface 5, the reproduced data input together with the transmission instruction is packetized by storing it in an isochronous packet as described above, and the isochronous packet is sequentially output to the digital data transmission line LN. You.
[0043]
Here, in the isochronous communication, it is assumed that a packet can be transmitted every 8 KHz cycle period. Therefore, the packet generation processing and the packet transmission processing in the interface unit 5 described above are executed at a timing corresponding to the cycle period of 8 KHz. In addition, the read processing of the system controller 3 for reading the reproduction data to be transmitted from the buffer RAM 4 and transmitting the reproduction data to the interface unit 5 is also executed at a timing corresponding to the cycle period of 8 KHz.
[0044]
The D / A converter 10 includes a D / A conversion processing unit 11, a clock generator 12, and a buffer RAM 13.
The clock generator 12 generates a master clock MCL based on the oscillation frequency generated by the crystal oscillator 12a, and supplies the master clock MCL to the D / A conversion processing unit 11. In this case, the frequency of the master clock MCL is set, for example, in correspondence with executing D / A conversion processing on the DSD signal. Specifically, since the DSD signal is 1-bit quantized data at a sampling frequency of 2.8224 MHz, it has a clock frequency corresponding to 1 (bit) × 2.8224 MHz = 2.8224 MHz.
[0045]
The D / A conversion processing unit 11 receives the isochronous packet transmitted through the digital data transmission line LN and executes unpacketization. That is, the reproduction data stored in the received isochronous packet is extracted. Then, the extracted reproduced data is transferred to the buffer RAM 4 and written therein, where it is temporarily stored.
The buffer RAM 13 can also operate as a ring buffer by the write / read processing by the D / A conversion processing unit 11.
[0046]
Then, the D / A conversion processing unit 11 continuously reads the reproduction data (DSD signal) stored in the buffer RAM 13 at a timing based on the master clock MCL output from the clock generator 12. Then, D / A conversion is performed on the data thus read out, and the data is output as an analog audio signal.
[0047]
Further, the D / A conversion processing unit 11 monitors the remaining amount of data in the buffer RAM 13. The remaining data amount can be obtained, for example, by calculating the difference between the value of the write address and the value of the read address for the buffer RAM 13.
Then, the D / A conversion processing unit 11 generates a control signal CNT for controlling the data transfer speed per unit time from the disk drive 10 based on the remaining amount of data in the buffer RAM 13.
That is, for example, when the remaining amount of data in the buffer RAM 13 increases beyond a certain amount, an instruction is issued to lower the data transfer speed in accordance with the increase amount. A control signal CNT instructing to increase the data transfer rate according to the amount is generated and transmitted to the disk drive 1 side.
Here, the remaining amount of data in the buffer RAM 13 corresponds to the jitter of the speed timing of the data processing in the D / A conversion processing unit 11. That is, a state in which the remaining data amount is more than a certain amount and is approaching an overflow corresponds to a state in which the data processing speed in the D / A conversion processing unit 11 is slow. On the other hand, a state in which the remaining data amount is smaller than the fixed amount and approaches an underflow corresponds to a state in which the data processing speed in the D / A conversion processing unit 11 is increasing.
[0048]
Then, the disk drive 1 operates so as to vary the data transfer rate to be transmitted to the digital data transmission line LN in accordance with the received control signal CNT, so that the data remaining in the buffer RAM 13 of the D / A conversion processing unit 11 is changed. The amount will always be controlled to be approximately appropriate. That is, control is performed so that overflow or underflow does not occur in the buffer RAM 13.
[0049]
The control signal CNT may be defined under, for example, an IEEE 1394 data interface, and transmitted as a command through an IEEE 1394 data bus by asynchronous communication. In this case, the transmission path for the control signal CNT and the digital data transmission path LN for the reproduction data are actually a common IEEE 1394 bus.
[0050]
In this case, in the disk drive 1, the control signal CNT is received by the interface unit 5 and acquired by the system controller 3.
The system controller 3 executes a control process based on the received and obtained control signal CNT so as to vary the data transfer rate transmitted from the digital data transmission line LN. That is, the present embodiment adopts a configuration in which the D / A converter 10 is a clock master and the disk drive 1 is synchronized with the operation timing of the D / A converter 10.
In the present embodiment, when changing the data transfer rate for synchronization, conceptually, the size (data amount) of the reproduction data stored in the isochronous packet and transmitted at an interval of 8 kHz is dynamically changed. The control process is executed so as to change to.
[0051]
It should be noted that, for the sake of confirmation, in the conventional system shown in FIG. 13, the D / A converter 110A is a clock master, and the disk drive 100A follows the D / A converter 110A and synchronizes. is there. Also in the system of FIG. 13, as a result, the size of the reproduction data in the isochronous packet transmitted from the digital data transmission line LN changes.
[0052]
However, in the disk drive 100A of FIG. 13, what is directly controlled in accordance with the control signal CNT is the frequency of the master clock MCL (that is, the oscillation frequency of the VCO 13). As a result, the size of the reproduction data in the isochronous packet transmitted periodically changes.
[0053]
On the other hand, in the present embodiment, what is directly varied by the disk drive 1 according to the control signal CNT is the data size to be read from the buffer RAM 4 and stored in the isochronous packet.
As a result, according to the present embodiment, in the configuration in which the D / A converter 10 is used as a master clock, the disk drive 1 does not have a configuration (for example, a PLL circuit) for generating a clock corresponding to continuous data reproduction. The drive 1 can change the data transfer speed in synchronization with the processing timing of the D / A converter 10.
[0054]
1-2. Isochronous packet
Here, prior to describing a packet transmission operation involving a variable data size in an isochronous packet in the disk drive 1, an IEEE 1394 transmission format related to the present embodiment will be described.
First, the structure of the isochronous packet will be described with reference to FIG.
The isochronous packet is also called CIP (Common Isochronos Packet).
The first 32 bits (1 quadlet) of the CIP are a 1394 packet header.
In the 1394 packet header, a 16-bit area is data_Length, a 2-bit area is tag, a 6-bit area is channel, a 4-bit area is tcode, and a 4-bit area is sy.
Then, a header_CRC is stored in an area of 1 quadlet following the 1394 packet header.
[0055]
An area of 2 quadlets following the header_CRC is a CIP header. In the upper two bits of the upper quadlet of the CIP header, '0' and '0' are stored, and the subsequent 6-bit area indicates an SID (transmission node number). An 8-bit area following the SID is a DBS (data block size), and indicates the size of the data block (unit data amount of packetization). Subsequently, areas of FN (2 bits) and QPC (3 bits) are set, FN indicates the number of divisions at the time of packetization, and QPC indicates the number of quadlets added for division. Is shown.
SPH (1 bit) indicates a flag of the header of the source packet, and DBC stores a counter value indicating the number of data blocks in the packet. Missing data in block units can be detected based on the value of DBC.
[0056]
The upper two bits of the lower quadlet of the CIP header respectively store '0' and '0'. Subsequently, areas of FMT (6 bits) and FDF (24 bits) are provided. The signal format (transmission format) is shown in the FMT, and the type of data (data format) stored in the CIP can be identified by the value shown here. Specifically, it becomes possible to identify MPEG stream data, Audio stream data, digital video camera (DV) stream data, and the like.
The FDF is a format-dependent field, and is an area indicating a further subdivided classification of the data format classified by the FMT. If the data is related to audio, for example, it is possible to identify whether the data is linear audio data or MIDI data.
[0057]
Here, for example, when the FMT indicates that it is MPEG, the FDF stores synchronization control information called TSF (time shift flag). When the FMT indicates that the camera is a DVCR (digital video camera), the FDF is defined as shown in the lower right of FIG. Here, the number of fields per second is defined by 50/60 (1 bit) in order from the top, and STYPE (5 bits) indicates whether the video format is SD or HD, and SYT indicates the frame format. A time stamp for synchronization is shown.
[0058]
Also, when FMT indicates that the data is reproduction data (DSD signal) from the SACD according to the present embodiment, SYT is to be stored in the field of FDF. Frame synchronization can be obtained.
[0059]
Following the CIP header, a data block area is arranged. In this data block area, data indicated by FMT and FDF is stored in a sequence of n data blocks (quadlets). In the present embodiment, reproduction as a DSD signal read by the buffer RAM 4 is performed. Data will be stored as this sequence of data blocks.
After the data block, data_CRC is finally placed.
[0060]
1-3. Disk drive packet transmission operation
1-3-1. Packet transmission operation (blocking transmission)
Subsequently, an operation of transmitting an isochronous packet of the reproduction data (DSD signal) from the SACD by the disk drive 1 will be described.
First, in this embodiment, when transmitting SACD data (DSD signal) under the IEEE 1394 data interface standard, a basic data size to be stored in one isochronous packet is determined as follows. And Note that SACD data (DSD signal) is defined as one of data types that can be transmitted in TA Document 2001003 as a standard of the IEEE 1394 data interface.
[0061]
Since the DSD signal is an audio signal having a sampling frequency of 2.8224 MHz, the data rate of this audio signal is:
1 bit x 2.82224 MHz = 2.8224 M bit per sec
It becomes.
As described above, the transfer cycle in isochronous communication is 8 KHz, so the data size to be transferred by one isochronous packet is as follows.
2.8224 Mbit / 8k = 352.8 bit per cycle
Can be expressed as
[0062]
As shown in FIG. 11, the unit of the data block in the isochronous packet is 1 quadlet = 32 bits. As for the DSD signal, 24 bits out of 1 quadlet = 32 bits are used.
The amount of data that can be transmitted for each transfer cycle is in quadlet units. Therefore, when the data size to be transferred by one isochronous packet is treated as a quadlet unit,
352.8 bits / 24 bits = 14.7 quadlet per cycle
It is expressed as That is, it is derived that ideally, data of a DSD signal having a data block size of 14.7 quadlets should be stored for an isochronous packet transmitted every 8 KHz cycle.
[0063]
Based on the above, the disk drive 1 of the present embodiment stores the DSD signal, which is reproduction data, in an isochronous packet and sends it out, as described below.
By the way, according to the standard of the IEEE 1394 data interface, data transmission by isochronous packets is defined in two well-known methods, blocking transmission and non-blocking transmission.
The blocking transmission is a transmission method in which the data size stored for each isochronous packet is fixed, but a transfer cycle period during which no data is transmitted is permitted. On the other hand, non-blocking transmission is a transmission method in which the data size to be stored for each isochronous packet is allowed to be changed, but data is always stored and transmitted for each transfer cycle. .
[0064]
First, a case where a DSD signal is transmitted by blocking transmission will be described with reference to FIG.
FIG. 2A shows a SYT timing pulse. The SYT timing pulse is a pulse synchronized with the time stamp stored in the SYT in the FDF field in the CIP header in the structure of the isochronous packet shown in FIG. 11, and has a frequency of 7.35 KHz, for example. Here, a period corresponding to one cycle of the SYT timing pulse is referred to as a SYT period.
[0065]
FIG. 2B shows an event sequence of the DSD signal. In this event sequence, as can be seen from the fact that the timing of each event corresponds to one quadlet of data, the reproduced data (DSD signal) reproduced from the SACD and stored in the buffer RAM 4 is converted into a data block (quadlet = It corresponds to a data string arranged in units of 24 bits). In this figure, events (data blocks) updated by the SYT time stamp are indicated as R2, R3, and R4 according to the lapse of time. Here, these R2, R3, R4... Also indicate the value of the SYT time stamp. The playback data portion of the event corresponding to the SYT is the head data of the frame synchronized with the SYT.
As can be seen with reference to FIGS. 2A and 2B, 16 events correspond to each SYT period. That is, when the transmission data is a DSD signal, 16 quadlets should be transmitted corresponding to each cycle of the SYT timing pulse.
[0066]
The DSD signal in the buffer RAM 4 schematically shown as an event sequence in FIG. 2B is read out by the system controller 3 and stored in an isochronous packet by the interface unit 5 to be packetized. become.
FIG. 2C shows the reproduction data (DSD signal) stored in the isochronous packet for each transfer cycle in data block (quadlet) units. As described above, the transfer cycle of the isochronous packet (nominal isochronous cycle) is 8 KHz, which is 0.65 KHz higher than the above-mentioned frequency of the SYT timing pulse, 7.35 KHz.
[0067]
If the DSD signal is transmitted in packets, as described above, ideally, data having a size of 14.7 quadlets should be transmitted for each cycle period. However, the data size actually stored and transmitted in the isochronous packet is defined as an integer multiple of the number of quadlets. This is the same in non-blocking transmission described later.
[0068]
Therefore, in the present embodiment, in storing the DSD signal in the isochronous packet in the blocking transmission, the data size to be stored is fixed at 16 quadlets.
As described with reference to FIGS. 2A and 2B, this is a relationship in which 16 quadlets of reproduced data are transmitted as the data rate of the DSD signal with respect to the timing of one cycle of the SYT timing pulse. Based on that. If the transmission is performed by 16 quadlets in this way, the reproduction data transmitted for each transfer cycle can be frame units. This can be understood from the fact that the first quadlet of the 16-quadlet playback data shown in FIG. 2C corresponds to the update timing of the SYT time stamp.
[0069]
In FIG. 2C, first, in the first transfer cycle (nominal isochronous cycle) corresponding to the period t2 to t3, it is assumed that SYT = R1 in the 1 SYT period immediately before the time t1 shown in FIG. 2B. DSD signals for 16 quadlets are stored in an isochronous packet and transmitted.
FIG. 2D shows the DBC stored in the CIP packet header of the isochronous packet transmitted in the transfer cycle of the period t2 to t3. In this case, 0 which is the initial value is shown. Here, DBC is a value obtained by integrating the number of quadlets of data transmitted by one isochronous packet.
The value stored in the SYT of this isochronous packet is R1, as shown in FIG.
[0070]
In the subsequent transfer cycle as periods t3 to t5, in FIG. 2B, a DSD signal for 16 quadlets corresponding to the SYT period of periods t1 to t4 is stored in an isochronous packet and transmitted.
The DBC of the isochronous packet transmitted in the transfer cycle during the period t3 to t5 is counted up in response to the transmission of the 16 quadlet DSD signal in the immediately preceding transfer cycle, and as shown in FIG. ), The value 16 is stored. As shown in FIG. 2E, the SYT of the isochronous packet indicates R2.
[0071]
Then, in the transfer cycle of the periods t5 to t7 subsequent to the periods t3 to t5, an empty packet or an isochronous packet of NO-DATA is transmitted. That is, in the period from t5 to t7, the reproduction data (DSD signal) is not read out from the buffer RAM 4 and transmitted.
In this case, since the entity of the DSD signal is not stored in the transmission packet, SYT shown in FIG. 2E is set to No Info, and a meaningful value is not stored. However, as long as the packet is transmitted, the DBC of the isochronous packet shown in FIG. 2D stores the counted up value. Here, a value 32 is stored, which is 16 more counted up from the DBC value 16 of the isochronous packet transferred in the immediately preceding transfer cycle.
[0072]
In the transfer cycle of the period t7 to t9 following the period t5 to t7, in FIG. 2B, the DSD signal of 16 quadlets starting from SYT = R3 corresponding to the period t4 to t6 is stored in the isochronous packet. Sent out. In other words, in the period t7 to t9, the DSD signal read from the buffer RAM 4 and packetized in the previous period t3 to t5 is packetized with the subsequent 16 quadlet DSD signal.
The DBC of the isochronous packet in the transfer cycle during the period t7 to t9 is further counted up by 16 to show the value 48 as shown in FIG. SYT stored in this isochronous packet indicates R3.
[0073]
Further, in the transfer cycle starting from the time point t9 following the time periods t7 to t9, the DSD signal for 16 quadlets starting from SYT = R4 corresponding to the time period t6 to t8 in FIG. Is to be.
As shown in FIG. 2D, the DBC of the isochronous packet in the transfer cycle started from the time point t9 has a value 64 obtained by counting up from the value 48 by 16. Shows the value 48. The SYT stored in the isochronous packet indicates R4 as shown in FIG.
[0074]
In this way, in the present embodiment, in blocking transmission, a data size fixed at 16 quadlets is stored in an isochronous packet and transmitted in principle.
However, during the period from t5 to t7 in FIG. 2C, an empty packet or a NO-DATA isochronous packet is transmitted, and the actual DSD signal is not transmitted. In other words, in the blocking transmission according to the present embodiment, an empty packet or a NO-DATA isochronous packet is intermittently transmitted, for the following reason.
[0075]
As mentioned above, the transmission of the DSD signal is ideally 14.7 quadlets per cycle period. Further, as described above, the transfer cycle of the isochronous packet (nominal isochronous cycle) is 8 KHz, whereas the frequency of the SYT timing pulse shown in FIG. 2A is 7.35 KHz. The transfer cycle of the isochronous packet is faster. This is because the timing of the transfer cycle shown in FIG. 2C progresses temporally with respect to the timing of the SYT period shown in FIGS. 2A and 2B and the corresponding event sequence. I understand.
[0076]
Therefore, if a DSD signal with a fixed data size of 16 quadlets is always stored and transmitted for an isochronous packet, the data transfer rate per unit time will be higher than the actual data rate of the DSD signal.
As a result, for example, as shown in the event sequence at time t5, which is the start time of the transfer cycle in FIG. 2, the data for 16 quadlets starting from the SYT time stamp R3 to be transmitted next is written into the buffer RAM 4. Not completed. In other words, at the start of the transfer cycle at time t5, data for the next 16 quadlets to be transmitted is not prepared.
[0077]
Therefore, as described above, the blocking transmission according to the present embodiment is performed when the buffer RAM 4 does not store 16 quadlets of data to be transferred next, when an empty packet or NO-DATA By transmitting the isochronous packet, a period of a transfer cycle in which the DSD signal is not transmitted is provided.
By forming a period of the transfer cycle in which the DSD signal is not transmitted at the required timing in this way, as a result, the DSD signal is not transmitted for a certain fixed time width. (2.8224M bit per sec). As a result, synchronization with the data processing speed on the receiving side can be obtained, and data processing on the receiving side can be prevented from being broken. In the present embodiment, “synchronizing with the data processing speed on the receiving side” means that the buffer RAM provided for data processing on the receiving side does not overflow or underflow. Point,
When the blocking transmission according to the present embodiment is regarded as a data size to be stored in an isochronous packet, the data size is variable between a data size corresponding to 16 quadlets and a data size of 0. It can be said that.
[0078]
For example, the reproduction data as the DSD signal stored and transmitted in the isochronous packet as described above is received by the D / A converter 10 and stored in the buffer RAM 13 as described in FIG. Is done. Then, the D / A conversion processing section 11 continuously reads out the reproduction data stored in the buffer RAM 13 and executes the D / A conversion processing.
[0079]
FIG. 2F shows an event sequence corresponding to the D / A conversion processing. This also corresponds to the fact that the reproduction data (DSD signal) read from the buffer RAM 13 for the D / A conversion processing is indicated in quadlet units.
The reproduced data in quadlet units corresponding to the event sequence shown in FIG. 2 (f) is synchronized with the SYT timing pulse reproduced on the D / A converter 10 side as shown in FIG. 2 (g). , SYT period, D / A conversion is performed at a speed timing of 16 quadlets.
It can be seen that the timings of the data processing shown in FIGS. 2F and 2G are the same as those in FIGS. 2A and 2B. That is, the D / A converter 10 performs data processing on the DSD signal reproduced by the disk drive 1 at an appropriate timing based on the data rate and time information (SYT) corresponding to the DSD signal. Will be.
Also, in this figure, as can be seen by comparing FIG. 2B and FIG. 2F, the event sequence timing on the D / A converter 10 side is different from the event sequence timing on the disk drive 1 side. It is also shown that a delay (TRANSFER DELAY) occurs corresponding to the time required for transmission.
[0080]
When the blocking transmission is actually performed as described above, as a necessary minimum, the data transmission by the isochronous packet is performed at a data transfer rate equivalent to the original data rate of the DSD signal. It is necessary to determine whether to store 16 quadlets or 0 quadlets (empty packet or No-Data packet).
Thus, in the present embodiment, the processing shown in the flowchart of FIG. 3 is executed as the processing operation for determining the data size in such blocking transmission.
In the system shown in FIG. 1, the disk drive 1 determines the size of the reproduction data to be stored in the isochronous packet based on the control signal CNT transmitted from the D / A converter 10. . However, here, for simplicity of explanation, a basic process that does not include an element of the data determination process based on the control signal CNT will be described. That is, a data size determination process for simply obtaining a data transfer rate according to the data rate (2.8224 M bit per sec) of the DSD signal when the DSD signal is stream-outputted will be described. The data size determination processing including the control signal CNT as a determination element will be described later.
[0081]
Then, the processing operation shown in FIG. 3 is as follows. When the processing shown in this figure is applied to the disk drive 1 in FIG. 1, the system controller 3 must execute the processing.
Here, when it is determined that the timing to start transmitting the DSD signal as reproduction data has been reached, first, in step S101, initialization is performed.
As the initial setting, first, for a numerical value X indicating an ideal data size to be stored in one isochronous packet and a variable Z indicating a value of a cumulative calculation register,
X = 14.7
Z = 0.0
Initialize to Hereinafter, the numerical value X is referred to as “ideal transmission data size X”, and the variable Z is referred to as “accumulated calculation register value Z”.
As described above, since the ideal value of the data size to be stored in one isochronous packet is 14.7 quadlets, the ideal transmission data size X is the number of quadlets as this ideal value. .7 is set. In the processing shown in this figure, the ideal transmission data size X is a fixed value.
As will be understood from the following description, the cumulative calculation register value Z indicates the actual transmission data size (16 quadlet) and the ideal transmission data size (14.7 quadlet) when 16 quadlet playback data is continuously transmitted. ± 1%), and represents the difference between the originally required data rate and the data transfer rate due to actual data transmission. Therefore, at the start of transmission of the DSD signal as reproduction data, 0.0 is set.
[0082]
After the initialization is performed as described above, the processing shown as steps S102 to S106 is repeatedly executed until the data transmission is completed.
First, according to the cycle start timing at the start of the transfer cycle, in step S102, the current accumulated calculation register value Z
Z <16quadlet
It is determined whether or not the relationship is established.
[0083]
As described above, the cumulative calculation register value Z represents a difference between the originally requested data rate and the data rate by actual data transmission, and the cumulative calculation register value Z is smaller than 16 quadlets. At this point corresponds to a state in which 16 or more quadlets of data to be read are stored in the buffer RAM 4.
Therefore, in step S102, if the cumulative calculation register value Z is less than 16 quadlets and a positive result is obtained, the process proceeds to step S103 and subsequent steps.
[0084]
In step S103, as a variable Y (referred to as “actual transmission data size Y”) indicating the data size to be actually transmitted,
Y = 16
Set. That is, it is determined that the actual data size to be stored in the isochronous packet is 16 quadlets. As a result, for example, at the timing of the next transfer cycle, data of 16 quadlets is read from the buffer RAM 4, stored in an isochronous packet, and transmitted.
[0085]
In the next step S104, the accumulated calculation register value Z is calculated based on the ideal transmission data size X (= 14.7) and the current actual transmission data size Y (here, Y = 16 always).
Z = Z + (Y−X)
Is updated by performing the operation represented by. Then, the process returns to step S102 according to the timing of the next cycle start.
As can be seen from the above equation, when the DSD signal having the size of 16 quadlets is transmitted through the processing from step S102 to S103, the cumulative calculation register value Z is equal to the size of the 16 quadlets actually transmitted and the ideal transmission data size. A value obtained by integrating 1.3, which is a difference value from 14.7 quadlets, which is X, is obtained. That is, as described above, this indicates the error between the original data rate of the DSD signal and the data transfer rate of the data actually transmitted at the present time based on the quadlet (24 bit) unit. It is.
[0086]
In step S102, if a negative determination result is obtained that Z <16 quadlet is not established for the accumulated calculation register value Z, the process proceeds to step S105 and subsequent steps.
A case where a negative determination result is obtained in step S102 is a case where the cumulative calculation register value Z becomes equal to or greater than 16 quadlets. This indicates that, at the present time, the amount of data to be read in the buffer RAM 4 is assumed to be smaller than 16 quadlets.
Therefore, in this case, Y = 0 is set for the actual transmission data size Y in step S105. As a result, an empty packet or a No-Data packet is transmitted depending on the current transfer cycle.
Then, in the subsequent step S106, regarding the current accumulated calculation register value Z,
Z = Z-16
Is performed by performing the calculation represented by.
By transmitting an empty packet or a No-Data packet in accordance with the processing in step S105, it is determined that 16 quadlets of data to be blocked and transmitted are not transmitted in this transfer cycle. The processing in step S106 is performed in response to the fact that it is necessary to substantially subtract 16 quadlets as the cumulative calculation register value Z. In practice, a value close to 0.0 is obtained as the cumulative calculation register value Z depending on the calculation processing in step S106.
After the process of step S106 is performed, the process returns to step S102 at the next cycle start timing.
[0087]
In the present embodiment, as described above, based on the determination result of step S102, the size of the reproduction data (DSD signal) to be stored in the isochronous packet is set to 16 quadlets or 0 quadlet (empty packet or No-Data). Packet). Thus, the actual data transfer rate (data transfer rate) in a certain unit time is made equal to the original data rate of the DSD signal.
[0088]
1-3-2. Packet sending operation (non-blocking transmission)
Next, a description will be given of a case where non-blocking transmission is performed as an operation of transmitting an isochronous packet of reproduction data (DSD signal) from the SACD by the disk drive 1 with reference to FIG.
In the non-blocking transmission, as described above, the data size to be stored for each isochronous packet is allowed to vary. However, it is stated that data must be stored and transmitted every transfer cycle.
[0089]
4A and 4B show a SYT timing pulse and an event sequence of a DSD signal corresponding to the SYT timing pulse, similarly to FIGS. 2A and 2B described above. Have been.
[0090]
In the present embodiment, when transmitting a DSD signal by non-blocking transmission, as shown in FIG. 4C, an isochronous packet storing reproduction data (DSD signal) for 14 quadlets or a 15 quadlet is stored. An isochronous packet storing the reproduction data (DSD signal) is generated and transmitted.
That is, the transmission of the DSD signal is ideally set to 14.7 quadlets for each cycle period. In this case, the reproduced data of 14 quadlets or 15 quadlets, which are the integer numbers of quadlets before and after that, are stored. And send it out accordingly.
As a result, as to the size of the reproduction data to be stored in the isochronous packet, which of 14 quadlets and 15 quadlets is determined appropriately for each transfer cycle, as a result, a certain group is obtained. , The average of the number of quadlets sent out in successive cycles of 14.7 quadlets is 14.7 quadlets. That is, the data transfer rate in a certain time width can be made equal to the data rate (2.8224 M bit per sec) of the DSD signal, and the data transfer rate synchronized with the data processing on the receiving side can be achieved. (Data transfer speed) can be maintained.
[0091]
Here, in FIG. 4C, as a specific example, first, in a transfer cycle (nominal isochronous cycle) of the period t2 to t3, 14 quadlets of reproduction data are stored. In the reproduced data of the 14 quadlets, the data of one quadlet corresponding to SYT = R1 indicated by the event sequence shown in FIG. 4B is the 14th quadlet.
In this case, the DBC of the isochronous packet transmitted in the transfer cycle of the period t2 to t3 is, for example, 3 as shown in FIG.
In addition, in correspondence with the storage of 1 quadlet of data corresponding to SYT = R1 as block data, a value indicating R1 is stored in SYT of this isochronous packet.
[0092]
In the transfer cycle as the subsequent period t3 to t5, 14 quadlets of reproduced data are stored following the 1 quadlet of data corresponding to SYT = R1.
Since the SYT is updated at the timing of every 16 quadlets, the reproduced data of the 14 quadlets does not include the frame head data synchronized with the SYT. Therefore, the SYT shown in FIG. 4E is No Info. In addition, the DBC shown in FIG. 4D indicates 17 by counting up by 14 quadlets from the state where the value in the previous transfer cycle was 3.
[0093]
Then, in the transfer cycle of the next period t5 to t7, 15 quadlets of reproduced data following the reproduced data transmitted in the previous transfer cycle (period t3 to t5) are stored.
The reproduction data for 15 quadlets includes data for 1 quadlet corresponding to the event of SYT = R2. Therefore, a value indicating R2 is stored in the SYT of the isochronous packet as shown in FIG. In this case, the DBC counts up from 14 to 14 in response to the transmission of 14 quadlets in the previous transfer cycle (period t3 to t5). 31) is stored.
[0094]
Further, in the transfer cycle of the next period t7 to t9, the reproduction data for 15 quadlets following the reproduction data transmitted in the previous transfer cycle (period t5 to t7) is stored.
Since the reproduced data of 15 quadlets includes data of 1 quadlet corresponding to the event of SYT = R3, the SYT of the isochronous packet is R3 as shown in FIG. In addition, the DBC in FIG. 4D has been sent out for 15 quadlets in the previous transfer cycle (period t5 to t7), so that the count up of 31 is further performed on 31 and the count becomes 46.
[0095]
Then, in the transfer cycle starting from time point t9, 15 quadlets of reproduced data following the reproduced data transmitted in the previous transfer cycle (period t7 to t9) are stored.
Since the reproduced data for 15 quadlets includes data for 1 quadlet corresponding to the event of SYT = R3, the SYT in FIG. 4E is R4. In the DBC of FIG. 4D, 15 quadlets have been transmitted in the previous transfer cycle (period t7 to t9), so that the count of 15 is performed on 46, and the DBC becomes 61.
[0096]
In the case of non-blocking transmission, the number of quadlets stored in an isochronous packet is 14 or 15. On the other hand, the frame corresponding to SYT is 16 quadlets. For this reason, as shown in FIG. 4C, SYT time stamps (R1, R2, R3, R4...) Are used in the reproduction data of 14 quadlets or 15 quadlets stored in the isochronous packet. ) Does not always exist. Even if it exists, it does not always become the head of a data block as in the case of blocking transmission.
However, even if the reproduction data (DSD signal) is transmitted by the non-blocking transmission in this way, the D / A converter 10 receiving the data extracts the information of the SYT time stamp from the received reproduction data. A SYT timing pulse is generated. As a result, as shown in FIGS. 4F and 4G, the reproduction data (DSD signal) stored in the buffer RAM 13 is appropriately processed in frame units.
[0097]
When the non-blocking transmission shown in FIG. 4 is actually performed, the reproduced data to be stored in the isochronous packet is transmitted at a data transfer rate equivalent to the original data rate of the DSD signal. It is necessary to determine whether the size is 14 quadlet or 15 quadlet.
The processing operation for this is shown in the flowchart of FIG. Note that the processing shown in FIG. 5 is also intended to simply obtain a data transfer rate corresponding to the data rate (2.8224 Mbit per sec) of the DSD signal when the DSD signal is stream-output. Basic data size determination processing will be described. The data size determination processing including the control signal CNT as a determination element in non-blocking transmission will be described later.
[0098]
In FIG. 5 as well, when it is determined that it is time to start sending a DSD signal as reproduction data, first, in step S201, initial settings are performed. This initial setting process is performed for the ideal transmission data size X and the cumulative calculation register value Z in the same manner as in step S101 of FIG.
X = 14.7
Z = 0.0
Initialize to
[0099]
After the initialization is performed in step S201, the current accumulated calculation register value Z is calculated in step S202 according to the cycle start timing.
Z <1 quadlet
It is determined whether or not the relationship is established.
As described above, the cumulative calculation register value Z in this case also indicates the difference between the originally requested data rate and the data rate by actual data transmission. However, the comparison target value in step S202 is 1 quadlet. In the non-blocking transmission, the data size to be transmitted is set to 14 quadlets or 15 quadlets, and is set in response to the difference of 1 quadlet between them. In step S202, the accumulated calculation register value Z is set to If the result is less than 1 quadlet and a positive result is obtained, the process proceeds to step S203.
[0100]
In step S203, as the actual transmission data size Y,
Y = 15
Set. That is, it is determined that the actual data size to be stored in the isochronous packet transmitted in the current transfer cycle is 15 quadlets. After executing the processing in step S203, the process proceeds to step S205.
[0101]
On the other hand, if a negative result is obtained in step S202 that the cumulative calculation register value Z is equal to or larger than 1 quadlet, the process proceeds to step S204.
In step S204, as the actual transmission data size Y,
Y = 14
Is set, and the process proceeds to step S205.
[0102]
In step S205, the cumulative transmission register value Z is calculated based on the ideal transmission data size X (= 14.7) and the current actual transmission data size Y (Y = 16 or Y = 15).
Z = Z + (Y−X)
Is updated by performing the operation represented by. Then, the process returns to step S202 according to the timing of the next cycle start.
[0103]
According to such processing, the data size to be stored in the isochronous packet is determined such that if the cumulative calculation register value Z is less than 1 quadlet, it is 15 quadlets, and if it is 1 quadlet or more, it is 14 quadlets.
As a result, the actual data transfer rate can be set to the same data transfer rate (data transfer rate) as the data rate of the original DSD signal.
[0104]
1-3-3. Function processing for packet transmission
In the present embodiment, the DSD signal is transmitted by blocking transmission or non-blocking transmission as described above. In addition, in the disk drive 1 according to the first embodiment shown in FIG. 1, the data is transmitted from the D / A converter 10 so that the data processing speed timing and synchronization of the D / A converter 10 as the receiving device can be obtained. Based on the control signal CNT, the data size to be stored in the isochronous packet is determined. That is, it controls the data transfer rate (data transfer rate).
[0105]
Therefore, first, a flow of a process for transmitting a packet of the disk drive 1 including a process of determining a data size to be stored in the above-mentioned isochronous packet will be described with reference to FIG.
FIG. 6 shows, as functional blocks, a process for transmitting an isochronous packet realized based on the hardware configuration of the disk drive 1 shown in FIG. The processing flow shown in this figure is common to blocking transmission and non-blocking transmission.
[0106]
As shown in this figure, the functions related to the packet transmission processing realized by the disk drive 1 include a transmission speed determining function 21, a data size determining function 22, a packet generating function 23, a data reading function 24, and a packet transmitting function 25. Will be prepared.
The transmission speed determination function 21 receives the control signal CNT input from the D / A converter 10 and determines the transmission speed of the reproduction data transmitted from the digital data transmission line LN. The data size determination function 22 determines the size of the reproduction data to be stored and transmitted in one isochronous packet in accordance with the transmission speed determined by the transmission speed determination function 21. The data size determination function 22 determines that the size is 16 quadlets or 0 quadlet in response to blocking transmission. In addition, the size is determined to be 14 quadlets or 15 quadlets corresponding to the non-blocking transmission.
The transmission speed determining function 21 and the data size determining function 22 are operations of the system controller 3 that has received the control signal CNT.
[0107]
The packet generating function 23 instructs the data reading function 24 to read a data amount corresponding to the data size determined by the data size determining function 22. The data reading function 24 reads the specified amount of reproduced data from the reproduced data (DSD signal) read from the SACD and stored in the buffer RAM 4. The read timing is in accordance with the transfer cycle (8 KHz) of the isochronous packet, as understood from the above description. Also, the data amount to be read corresponds to 16 quadlets for blocking transmission or 0 quadlets by not performing reading. Also, in the case of non-blocking transmission, it corresponds to 14 quadlets or 15 quadlets.
The packet generation function 23 generates the isochronous packet by storing the read data (DSD signal) read out as described above in the data block area.
The packet generating function 23 and the data reading function 24 are obtained as a process of reading data from the buffer RAM 4 by the system controller 3 and a process of generating a packet by the interface unit 5 under the control of the system controller 3.
[0108]
The packet transmitting function 24 transmits the packet generated by the packet generating function 23 to the receiving side (D / A converter 10) via the digital data transmission line LN, for example, in the next transfer cycle after the generation. .
The packet transmission function 24 is obtained as a packet transmission output process by the interface unit 5 under the control of the system controller 3.
[0109]
1-3-4. Data size determination processing (blocking transmission)
Hereinafter, the processing operation that the system controller 3 should execute to implement the data size determination function 22 shown in FIG. 6 will be described. That is, the data size is determined based on the control signal CNT.
Here, the case of blocking transmission will be described first. The basic operation of the blocking transmission according to the present embodiment is as described above with reference to FIGS. 2 and 3, and the processing for realizing the data size determination function 22 is based on this.
[0110]
The flowchart in FIG. 7 shows processing in the case of blocking transmission as data size determination processing by the data size determination function 22.
Note that, in the process shown in FIG. 7, S301, S302, S303, S308, steps S309, and S310 are the same processes as the steps S101 to S106 previously shown in FIG.
[0111]
Also in the processing shown in FIG. 11, if it is determined that the timing to start transmitting the DSD signal as the reproduction data has come, in step S301, the ideal transmission data size X = 14.7 and the cumulative calculation register value Z
X = 14.7
Z = 0.0
And initialization. Note that the ideal transmission data size X is originally a constant which is fixed at 14.7, and is not changed as a constant in the processing of FIG. However, in the processing shown in this figure, the ideal transmission data size X is treated as a variable that can be changed to a required value according to the value of the control signal CNT as described later.
[0112]
After the initialization is performed as described above, the process is repeatedly executed from step S302 at each cycle start timing until data transmission is completed.
Also in this step S302, similarly to step S302 in FIG.
Z <16quadlet
It is determined whether or not the relationship is established. Then, when a positive result is obtained, the process proceeds to the processes after step S303.
First, in step S303, as the actual transmission data size Y,
Y = 16
Is set, and the process proceeds to step S304.
[0113]
Here, the system controller 3 receives the control signal CNT transmitted from the D / A converter 10 and recognizes the value. Here, as the control signal CNT, a value indicating that the data transfer speed is changed by + 1% (increase by 1%), a value indicating that the data transfer speed is changed by 0% (no change), and a value of −1% (A 1% delay).
Then, in step S304, the value of the control signal CNT obtained at the present time is determined.
[0114]
If it is determined in step S304 that the value indicates a + 1% variable, the process proceeds to step S305. In step S305, X = 14.847 is set for the ideal transmission data size X. The value of X = 14.847 corresponds to + 1% variable,
X = 14.7 × 1.01 = 14.847
This is a value obtained by performing the above operation.
If it is determined in step S304 that the value indicates a 0% variable, the flow advances to step S306 to set X = 14.7, which is the value of the original ideal transmission data size. .
If it is determined in step S304 that the value indicates a -1% variable, the process advances to step S307 to set X = 14.553 for the ideal transmission data size X. This value of X = 14.553 corresponds to a -1% variable,
X = 14.7 × 099 = 14.553
Is obtained by performing the following operation.
After executing any one of the steps S305, S306, and S307, the process proceeds to step S308.
[0115]
In step S308, the cumulative calculation register value Z is calculated based on the current ideal transmission data size X and the current actual transmission data size Y (here, Y = 16 always).
Z = Z + (Y−X)
Is updated by performing the operation represented by.
Then, the process returns to step S302 in accordance with the timing of the next cycle start.
[0116]
If a negative determination result is obtained in step S302, the process proceeds to steps S309 → 310. The processing from step S309 to step S310 is the same as the processing in step S105 and step S106 in FIG. 3, and a description thereof will be omitted.
After the process of step S310 is performed, the process returns to step S302 at the next cycle start timing.
[0117]
According to the above-described processing operation, the value of the ideal transmission data size X is varied according to the variable rate of the data rate indicated by the value of the control signal CNT by the processing of step S304 and steps S305, S306, and S307. Will be. That is, the ideal transmission data size X is changed so as to take a numerical value corresponding to the data rate indicated by the control signal CNT. Then, the cumulative calculation register value Z is updated in step S308 using the ideal transmission data size X changed in this way.
[0118]
According to the above-described processing, the value of the changed ideal transmission data size X is reflected as the cumulative calculation register value Z compared in step S302. That is, the value is the accumulated calculation register value Z changed in accordance with the data rate indicated by the control signal CNT.
Then, by executing the processing in step S302 with the accumulated calculation register value Z as a comparison target, a determination result of the data size in consideration of the data rate indicated by the control signal CNT is obtained as the determination result in step S302. Will be done.
As a result, in the system shown in FIG. 1, it is possible to control the data transfer rate (data transfer rate) of the data transmitted from the disk drive 1 in synchronization with the data processing operation of the D / A converter 10. Has become.
[0119]
1-3-5. Data size determination processing (non-blocking transmission)
Subsequently, as a processing operation performed by the system controller 3 corresponding to the data size determination function 22 shown in FIG. 6, a processing operation in the case of non-blocking transmission will be described.
The processing in this case is also based on the basic operation of the non-blocking transmission described with reference to FIGS.
[0120]
The flowchart of FIG. 8 shows a data size determination process by the data size determination function 22 as non-blocking transmission.
In the processing shown in FIG. 8, S401, S402, S403, and S404 are the same as steps S201, S202, S203, and S204 shown in FIG. Then, after setting Y = 15 or Y = 14 as the actual transmission data size Y by the processing of S403 or S404, the processing from step S405 is executed.
[0121]
The determination processing in step S405 and the processing in steps S406, S407, and S408 based on the determination result are the same as the determination processing in step S304 illustrated in FIG. 7 and the processing in steps S305, S306, and S307 based on the determination result. It is said.
That is, the process is to vary the ideal transmission data size X in accordance with the value of the determined control signal CNT.
[0122]
Then, using the ideal transmission data size X whose value has been changed by any one of the above-described steps S305, S306, and S307,
Z = Z + (Y−X)
Is updated by performing the operation represented by. Then, at the timing of the next cycle start, the process returns to step S402.
[0123]
Even with such processing, the value of the ideal transmission data size X changed according to the data rate indicated by the control signal CNT is reflected as the cumulative calculation register value Z compared in step S409. Then, the process in step S402 is executed using the accumulated calculation register value Z as a comparison target. Accordingly, the determination processing in step S402 determines the data size in consideration of the data rate indicated by the control signal CNT.
That is, even in the case of the non-blocking transmission, it is possible to control the data transfer rate (data transfer rate) of the data transmitted from the disk drive 1 in synchronization with the data processing operation of the D / A converter 10.
[0124]
Then, according to the configuration of the embodiment described above, the continuous reproduction processing of the reproduction data depends on the D / A converter 10 which is the receiving device.
That is, the D / A converter 10 becomes the clock master, and executes the continuous reproduction processing based on the master clock. The variable data transfer speed on the disk drive 1 side for synchronizing with the D / A converter 10 is realized by directly changing the data size to be stored in the isochronous packet. The reproduced data stored in the isochronous packet is data read from the disk by the disk reproducing unit 2 and temporarily stored in the buffer RAM 4.
According to such a configuration, it is not necessary for the disk drive 1 to have a function of continuously reading a signal from a disk at an appropriate data rate and reproducing and outputting the signal. That is, in the disk drive 1, there is no need to provide a clock generator or a PLL circuit for generating a master clock.
This makes it possible to use a disk drive that does not have a clock generation function when reproducing data, such as digital audio signals and digital video signals, that are required to be continuously reproduced from a disk. For example, as an example other than the SACD, at present, a system having a so-called CD-ROM drive without a clock generation function can appropriately and continuously reproduce digital audio signals recorded on a CD-DA. .
[0125]
2. Second embodiment
Subsequently, a second embodiment of the present invention will be described.
FIG. 9 shows a system configuration according to the second embodiment. In this figure, the same parts as those in FIG.
The system shown in FIG. 9 includes a disk drive 1 and a D / A converter 10A. Since the block configuration of the disk drive 1 is the same as that of FIG. 1, the description is omitted here.
[0126]
In the D / A converter 10A, for example, in the configuration of the D / A converter 10 shown in FIG. 1, first, an A / D conversion processing unit 16 is added. The master clock MCL output from the clock generator 12 including the crystal oscillator 12a is supplied to the D / A conversion processing unit 11 and the A / D conversion processing unit 12 as illustrated. I have.
In this case, the input / output unit 14 is provided in response to the addition of the A / D conversion processing unit 16.
The input / output unit 14 is a unit that processes input and output of an input signal input to the D / A converter 10A and an output signal output from the D / A converter 10A. In the present embodiment, the digital data transmission lines LN and LN1 correspond to the IEEE 1394 data interface. Therefore, the input / output unit 14 has an input / output interface function corresponding to IEEE1394. In this case, the input / output unit 14 is provided with a buffer RAM 15.
[0127]
Also in the system shown in this figure, the reproduced data reproduced from the SACD is transmitted as an isochronous packet from the disk drive 1 via the digital data transmission line LN corresponding to the IEEE1394 data interface, and is received by the D / A converter 10A. Will be done.
The input / output unit 14 receives an isochronous packet (reproduced data) transmitted from the disk drive 1 via the digital data transmission line LN. Then, the received isochronous packet is unpacketized, and the reproduction data and SYT (time stamp) information are extracted. Here, the extracted reproduction data is stored in the buffer RAM 15.
The writing / reading of the received and obtained reproduction data to / from the buffer RAM 15 corresponds to the operation as a ring buffer.
[0128]
The D / A conversion processing unit 11 reads the reproduction data from the buffer RAM 15 via the input / output unit 14, executes the D / A conversion processing at a timing based on the master clock MCL, and outputs the analog audio signal. Is output as For the sake of confirmation, the D / A conversion processing unit 11 in the present embodiment has a configuration for D / A converting a DSD signal, which is playback data from an SACD.
[0129]
Conversely, the A / D conversion processing unit 16 receives an analog audio signal from the outside, performs A / D conversion processing at a timing based on the master clock MCL, converts the signal into a digital audio signal, and outputs the digital audio signal. In this case, the A / D conversion processing unit 16 converts the input analog audio signal into a digital audio signal as a DSD signal corresponding to the SACD format.
[0130]
Although the details will be described later, the digital audio signal obtained by the A / D conversion processing unit 16 is not used for reproducing and outputting as audio. The digital audio signal is transmitted to the disk drive 1 in accordance with a data rate (data size in an isochronous packet) at the disk drive 1 in order to vary the data transfer rate of the reproduction data transmitted by the disk drive 1 itself. used. Therefore, the content as an analog audio signal input to the A / D conversion processing unit 16 is not particularly limited.
Further, based on the above, the digital audio signal output from the A / D conversion processing unit 16 and transmitted to the disk drive 1 will hereinafter be referred to as “control data”.
[0131]
The control data (digital audio signal) output from the A / D conversion processing unit 16 is input to the input / output unit 14. In the input / output unit 14, the control data input from the A / D conversion processing unit 16 is written into the buffer RAM 15, and temporarily stored and accumulated. This accumulation operation may be based on the operation as the ring buffer.
The input / output unit 14 reads data of a required size from the control data stored in the buffer RAM 15 as described above, stores the read data in an isochronous packet, and transmits the read data to the digital data transmission line LN1. It is sent to the disk drive 1.
The transmission operation of the control data by the input / output unit 14 is an operation as the blocking transmission described with reference to FIG. 2 or the non-blocking transmission described with reference to FIG.
In this case, in the input / output unit 14, the A / D conversion processing by the A / D conversion processing unit 16 is executed at a timing based on the master clock MCL. Therefore, in the input / output unit 14, the data size of the control data to be stored in the isochronous packet is obtained by the processing shown in FIG. 3 for the blocking transmission and the processing shown in FIG. 5 for the non-blocking transmission. May be determined.
[0132]
The control data transmitted from the input / output unit 14 of the D / A converter 10A via the digital data LN1 in the sequence of the isochronous packet is received and acquired by the interface unit 5 of the disk drive 1.
[0133]
For example, in the case of the system shown in FIG. 1, the disk drive 1 reproduces data based on the control signal CNT transmitted from the D / A converter 10 so as to synchronize with the data processing speed timing of the D / A conversion processing unit 11. The data transfer rate of data was variable.
The disk drive 1 of the second embodiment uses the control data received and obtained as described above to synchronize with the data processing speed timing of the D / A conversion processing unit 11 as follows. In such a case, the data transfer rate of the reproduced data is changed. That is, the size of the reproduction data to be stored in the isochronous packet is determined.
[0134]
FIG. 10 shows, as functional blocks, a process for transmitting an isochronous packet in the disk drive 1 shown in FIG. The same parts as those in FIG. 6 are denoted by the same reference numerals.
10 is different from FIG. 6 in that a data size measuring function 21A is shown in FIG. 10 instead of the sending speed determining function 21 shown in FIG. The data size measurement function 21 inputs control data received and acquired from the digital data transmission line LN1.
The control data is transmitted in cycle units on an isochronous packet basis. Therefore, the data size measurement function 21 measures the data size of the control data stored in the isochronous packet.
As a result of this measurement, if the transmission of the control data is based on blocking transmission, either a 16 quadlet or 0 quadlet result will be obtained. In the case of non-blocking transmission, a result of either 15 quadlets or 14 quadlets is obtained.
[0135]
In this case, the data size determination function 22 uses the measurement result of the data size measurement function 21 to determine the size of the reproduction data to be stored and transmitted in the isochronous packet.
First, the case where the control data is transmitted by the blocking transmission is as follows.
In the case of the blocking transmission, if the data size measurement function 21 outputs 16 quadlets as the measurement result, the data size determination function 22 determines the data size of the reproduced data as being 16 quadlets, which is the same as the measurement result.
When the measurement result is 0 quadlet, the data size of the reproduction data is similarly determined to be 0 quadlet, which is the same as the measurement result.
[0136]
The same applies to the case where control data is transmitted by non-blocking transmission.
That is, if the measurement result of the data size measurement function 21 is 15 quadlets, the data size of the reproduced data is set to the same 15 quadlets. If the measurement result is 14 quadlets, the same 14 quadlets are used.
[0137]
Then, based on the determination result of the data size determination function 22 obtained as described above, the subsequent processing as the packet generation function 23, the data read function 24, and the packet transmission function 25 has been described with reference to FIG. It is executed as follows. Then, such processing is executed for each transfer cycle.
As a result, the disk drive 1 obtains an operation of storing reproduced data having the same data size as the control data in an isochronous packet and transmitting the data to the D / A converter 10A.
By performing such an operation, the data transfer rate of the reproduced data sent from the disk drive 1 always coincides with the data transfer rate of the control data sent from the D / A converter 10. Is done.
Here, the data transfer rate of the control data transmitted from the D / A converter 10 is determined depending on the processing speed timing of the A / D conversion processing unit 16 that outputs a digital audio signal as the control data. . Since the A / D conversion processing unit 16 performs processing based on the same master clock MCL as the D / A conversion processing unit 11, the processing speed of the A / D conversion processing unit 16 and the D / A conversion processing unit 11 The timing will always be the same.
As described above, the fact that the data transfer rate of the reproduced data sent from the disk drive 1 matches the data transfer rate of the control data means that the data transfer rate of the reproduced data from the disk drive 1 is D / A This means that the processing speed is synchronized with the processing speed timing of the conversion processing unit 11. In the second embodiment, the data transfer rate (data transfer rate) of the disk drive 1 and the processing speed timing of the D / A conversion processing unit 11 are synchronized using the control data in this manner. It is made to plan.
[0138]
In the first embodiment and the second embodiment, as described above, the data size to be stored in the isochronous packet is determined. It is possible to respond.
First, in the system configuration according to the first embodiment, the information of the numerical value of the double speed for the current data processing speed is transmitted from the D / A conversion processing unit 11 of the D / A converter 10 to the system controller of the disk drive 1. 3 to be notified. First, the system controller 3 controls the disc reproducing unit 2 to perform disc reproduction at a double speed higher than the notified double speed. Thus, even if data is read from the buffer RAM 4 at a timing corresponding to double-speed data transmission, an underflow is prevented from occurring.
[0139]
Then, the system controller 3 calculates the data size to be stored in the isochronous packet according to the notified value of the double speed as the process of the data size determination function 22 shown in FIG.
As a specific example, a case will be described in which the numerical value of the notified double speed is 2, corresponding to the double speed of the data processing speed of the D / A conversion processing unit 11.
At the time of the blocking transmission, as the processing shown in FIG. 7, first, as an initial setting in step S301, the ideal transmission data size X
X = 14.7 × 2 = 29.4
Set.
Also, in step S302, regarding the cumulative calculation register value Z,
Z> 32 (16 × 2) quadlet
Is determined as to whether or not.
Then, in step S303, the actual transmission data amount Y to be set is
Y = 32 (= 16 × 2)
Set.
Further, in steps S305, S306, and S307,
X = 29.694 (= 29.4 × 1.01)
X = 29.4
X = 29.106 (= 29.4 × 0.99)
Should be set.
In this way, by setting the required parameter to a value twice as fast as that of the 1 × speed corresponding to the value 2 of the double speed, the data transfer rate transmitted from the disk drive 1 can also be set to 2 × speed. it can.
In other words, if the required parameter value used in the data size determination process is set to n times the value corresponding to the n times speed, the variable speed synchronized with the double speed set by the D / A conversion processing unit 11 side Transmission becomes possible.
[0140]
The same applies to non-blocking transmission. For example, by setting a multiple corresponding to the double speed for the value of a required parameter used in the flowchart shown in FIG. 8, variable speed transmission becomes possible. It becomes.
[0141]
In the second embodiment, the following configuration can be considered to enable variable-speed transmission.
First, in the D / A converter 10A, it is assumed that the A / D conversion processing in the A / D conversion processing unit 16 that generates control data is 1 × speed. On the other hand, it is assumed that the D / A conversion processing on the reproduced data in the D / A conversion processing unit 11 is at double speed. For example, the A / D conversion processing section 16 performs A / D conversion processing corresponding to a sampling frequency of 48 KHz and a signal format of 2 ch, and the D / A conversion processing section 11 has a sampling frequency of 96 (= 48 × 2) KHz. A case where D / A conversion processing corresponding to a 2ch signal format is executed can be assumed.
It should be noted here that even if the A / D conversion processing in the A / D conversion processing section 16 and the D / A conversion processing in the D / A conversion processing section 11 are different in the double speed, the A / D conversion processing is performed. As long as the conversion processing unit 16 and the D / A conversion processing unit 11 perform data processing based on the same master clock MCL, the processing speed timings of both are synchronized based on the master clock MCL. It is.
[0142]
Also in this case, the D / A converter 10A notifies the system controller 3 of the disk drive 1 of the information of the numerical value of the double speed. The information of the numerical value of the double speed is obtained by, for example, assuming that the A / D conversion processing speed in the A / D conversion processing unit 16 is 1 ×, and calculating the D / A conversion processing unit 11 / A conversion processing speed. That is, assuming that the A / D conversion processing speed in the A / D conversion processing unit 16 is A and the D / A conversion processing speed in the D / A conversion processing unit 11 is B, B / A is calculated and obtained. The value may be a double speed numerical value.
[0143]
Then, the system controller 3 of the disk drive 1 inputs the control data, measures the data size by the data size measurement function 21A, and sends the measurement result to the data size determination function 22, as described above with reference to FIG. Output.
[0144]
In the above description, it is assumed that the A / D conversion processing speed in the A / D conversion processing unit 16 and the D / A conversion processing speed in the D / A conversion processing unit 11 are equal. For this reason, the data size determination function 22 determines the same data size as the data size (number of quadlets) measured by the data size measurement function 21A as the data size to be stored in the isochronous packet.
On the other hand, when the numerical information of the double speed is notified as described above, the data size determination function 22 determines the data size (the number of quadlets) with respect to the data size (the number of quadlets) measured by the data size measurement function 21A. Based on the value obtained by multiplying the numerical value of the double speed, the data size to be actually transmitted is determined.
[0145]
As a simple example, let us consider a case where the double speed is set for the D / A conversion processing on the reproduction data in the D / A conversion processing unit 11 as described above.
For example, in the case of blocking transmission, depending on the data size measurement function 21A, a measurement result of 16 quadlets or 0 quadlets is obtained. Then, when the measurement result is 16 quadlets, the data size determination function 22 performs the calculation of 16 × 2 = 32 and determines that the data is 32 quadlets. In the case of 0 quadlet, it is determined that 0 × 2 = 0 quadlet, so that an empty packet or No-data packet is transmitted.
[0146]
In the case of non-blocking transmission, a measurement result of 15 quadlets or 14 quadlets is obtained depending on the data size measurement function 21A. Therefore, the data size determination function 22 is configured to determine either 30 (= 15 × 2) quadlets or 28 (= 14 × 2) quadlets in accordance with the measurement result.
[0147]
In the first and second embodiments, the control process for transmitting a packet to be executed by the disk drive 1 is executed according to a program stored in a ROM, which is assumed to be provided in the system controller 3, for example. It is assumed that.
[0148]
Further, such a program is temporarily stored in a removable recording medium such as a flexible disk, a CD-ROM (Compact Disc Only Memory), an MO (Magnet Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory. Alternatively, it can be stored (recorded) permanently. Such a removable recording medium can be provided as so-called package software.
For example, in the present embodiment, the program can be recorded on a disk medium that can be reproduced by the disk reproducing unit 2 and provided as package software. In response to this, the disk driver 1 can install the program by reading the program from the disk and storing the program in the internal ROM of the system controller 3. In addition, by storing such a program in various recording media, it is possible to install and execute the operation according to the present embodiment on a general-purpose personal computer or the like.
The program may be installed from a removable recording medium as described above, or may be configured to be downloaded from a server or the like storing the program via a network such as a LAN (Local Area Network) or the Internet. It is.
[0149]
Further, the present invention is not limited to the configurations described in the above embodiments.
As the first and second embodiments, the system configurations shown in FIGS. 1 and 9 have a configuration in which separate and independent devices are connected to each other by a transmission line or the like in the drawings. However, in actuality, for example, the configuration may be such that it is mounted on various information processing apparatuses such as a personal computer and the like, electronic equipment, and the like.
Further, the disk drive 1 shown in FIGS. 1 and 9 has a configuration capable of reproducing at least an SACD, but the disk medium that can be reproduced is not limited to this. Accordingly, the format of the signal to be transmitted through the digital data transmission line LN may be a format other than the DSD signal corresponding to the SACD, such as a digital audio signal or a digital video signal of another format. May be. Also, the medium on which the reproduction data is recorded need not be limited to a disk medium such as a tape medium.
[0150]
In each of the above embodiments, a D / A converter is used as a receiving device. That is, the modulation processing on the receiving side in the present invention is a D / A conversion processing. However, the present invention is not limited to this, and any device that adopts a configuration that executes required data processing related to continuous reproduction at a timing based on a master clock for data transmitted from the transmission side is possible. It is not limited.
Further, in each of the above embodiments, the IEEE 1394 data interface is used to transmit data from the transmission side to the reception side. However, other data interfaces that can perform packetization to transmit and receive data are used. It can be adopted. Further, the data interface in this case may be a local bus employed in a personal computer or the like.
[0151]
【The invention's effect】
As described above, according to the present invention, the operation of a data transmission device (disk drive) for transmitting data read from a recording medium and held in a storage means (buffer RAM) to a data reception device (D / A converter) side includes: First, a control signal (control signal CNT or control data) transmitted from the data receiving device is received. Then, based on the received control signal, the data amount (data size: number of quadlets) to be stored in the packet (isochronous packet) is determined, and the data corresponding to the determined data amount is read out from the storage means. A packet is generated and transmitted to the data receiving device.
Here, the control signal is generated and transmitted for the purpose of controlling the data transfer rate of the data transmitting device so that the process for continuous reproduction (for example, D / A conversion process) on the data receiving device side does not fail. Is what is done. Therefore, by determining the amount of data to be stored in the packet in accordance with the control signal, the data transfer rate of the data transmitted from the data transmitting device is set to the processing speed timing for the continuous reproduction on the data receiving device. Can be adapted.
[0152]
Then, it can be said that such an operation of the data transmission device directly variably controls the data size to be stored in the packet according to the control signal from the data reception device. In the case of such a configuration, the operation of reading data from the recording medium may be to collectively read data in a predetermined data unit at a required timing and sequentially store the data in the storage unit. That is, there is no need to provide a means for generating a master clock, which is required for continuously reproducing data from a recording medium.
[0153]
As a result, the present invention does not require a configuration for generating a master clock as a reproducing device (data transmitting device) for reading data from a recording medium on which data to be continuously reproduced is recorded. Cost reduction will be achieved.
[0154]
In addition, the reproducing device only needs to execute the operation of reading out the data in a predetermined data unit at a required timing and sequentially holding the data in the storage unit. Dependent.
Therefore, the reproducing apparatus (data transmitting apparatus) according to the present invention can be commonly used regardless of various signal formats recorded on various recording media. That is, wide compatibility with the signal format can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of a system configuration according to a first embodiment of this invention.
FIG. 2 is a timing chart showing an example of data transmission timing by blocking transmission in the embodiment.
FIG. 3 is a flowchart illustrating a basic processing operation for determining a data size in a packet in the blocking transmission according to the embodiment;
FIG. 4 is a timing chart showing an example of data transmission timing by non-blocking transmission in the embodiment.
FIG. 5 is a flowchart illustrating a basic processing operation for determining a data size in a packet in non-blocking transmission according to the embodiment;
FIG. 6 is a block diagram illustrating a flow of a packet transmission process according to the first embodiment.
FIG. 7 is a flowchart illustrating a processing operation for determining a data size in a packet according to the first embodiment;
FIG. 8 is a flowchart illustrating a processing operation for determining a data size in a packet according to a second embodiment.
FIG. 9 is a block diagram illustrating a system configuration example according to a second embodiment;
FIG. 10 is a block diagram illustrating a flow of a packet transmission process according to the second embodiment.
FIG. 11 is an explanatory diagram showing the structure of an isochronous packet.
FIG. 12 is a block diagram showing an example of a conventional system configuration.
FIG. 13 is a block diagram showing another example of a conventional system configuration.
[Explanation of symbols]
1 disk drive, 2 disk playback unit, 3 system controller, 4 buffer RAM, 5 interface unit, 10, 10A D / A converter, 11 D / A conversion processing unit, 12 clock generator, 13 crystal oscillator, 14 input / output unit , 15 buffer RAM, 16 A / D conversion processing unit, 21 transmission speed determination function, 21A data size measurement function, 22 data size determination function, 23 packet generation function, 24 data reading function, 25 packet transmission function, CNT control signal, LN, LN1 Digital data transmission path

Claims (8)

Receiving means for receiving a control signal transmitted from the data receiving apparatus to enable continuous reproduction of digital data in the data receiving apparatus and controlling a data transfer rate of data to be transmitted by the data transmitting apparatus; ,
Reading means for reading digital data in a predetermined data unit from a recording medium;
Storage means for temporarily storing and holding digital data read by the reading means,
Determining means for determining the amount of data to be stored in the packet according to the control signal received by the receiving means;
Packet generation means for reading digital data of the data amount determined by the determination means from the storage means, and generating a packet by storing the read data in the packet;
Transmitting means for transmitting the packet generated by the packet generating means to the data receiving device;
A data transmission device comprising: The receiving means,
As the control signal, a transmission speed control signal for controlling the transmission speed of digital data to be transmitted from the data transmission device is to be received,
The determining means is:
Based on the transmission rate control signal received by the receiving means, determine the amount of data to be stored in the packet,
The data transmission device according to claim 1, wherein: The receiving means,
As the control signal, a packet transmitted from the data receiving device and containing data is received.
The determining means is:
Based on the amount of data stored in the packet received by the receiving means, determine the amount of data to be stored in the packet generated by the packet generating means,
The data transmission device according to claim 1, wherein: A reception procedure for receiving a control signal transmitted from the data reception apparatus to enable continuous reproduction of digital data in the data reception apparatus and for controlling a data transfer rate of data to be transmitted from the data transmission apparatus,
A read control procedure for reading digital data by a predetermined data unit from a recording medium,
A storage control procedure for temporarily holding digital data read by the read control procedure in a storage area,
A determining step of determining an amount of data to be stored in the packet according to the control signal received by the receiving step;
A packet generation procedure of reading digital data of the data amount determined by the determination procedure from the storage area and generating a packet by storing the read data in the packet;
A transmission procedure for transmitting the packet generated by the packet generation procedure to the data receiving apparatus;
And a data transmission method. A reception procedure for receiving a control signal transmitted from the data reception apparatus to enable continuous reproduction of digital data in the data reception apparatus and for controlling a data transfer rate of data to be transmitted from the data transmission apparatus,
A read control procedure for reading digital data by a predetermined data unit from a recording medium,
A storage control procedure for temporarily holding digital data read by the read control procedure in a storage area,
A determining step of determining an amount of data to be stored in the packet according to the control signal received by the receiving step;
A packet generation procedure of reading digital data of the data amount determined by the determination procedure from the storage area and generating a packet by storing the read data in the packet;
A transmission procedure for transmitting the packet generated by the packet generation procedure to the data receiving apparatus;
Which causes a data transmission device to execute the program. A reception procedure for receiving a control signal transmitted from the data reception apparatus to enable continuous reproduction of digital data in the data reception apparatus and for controlling a data transfer rate of data to be transmitted from the data transmission apparatus,
A read control procedure for reading digital data by a predetermined data unit from a recording medium,
A storage control procedure for temporarily holding digital data read by the read control procedure in a storage area,
A determining step of determining an amount of data to be stored in the packet according to the control signal received by the receiving step;
A packet generation procedure of reading digital data of the data amount determined by the determination procedure from the storage area and generating a packet by storing the read data in the packet;
A transmission procedure for transmitting the packet generated by the packet generation procedure to the data reception apparatus;
Storage medium in which is stored. Receiving means for receiving a packet transmitted from the data transmitting device;
Demodulation means for sequentially inputting the data stored in the packet received by the reception means, and performing a demodulation process so that continuous reproduction is performed on the input data at a timing based on the master clock;
At a timing based on the master clock, signal processing means for performing a modulation process so that the input signal becomes continuous data,
A packet generated by storing the data obtained by the signal processing means for a required amount of data, as a control signal for controlling the data transfer rate of the data to be transmitted by the data transmission device, to the data transmission device. On the other hand, transmitting means for sequentially transmitting at a predetermined timing,
A data receiving device comprising: A receiving procedure for receiving a packet transmitted from the data transmitting apparatus;
A demodulation procedure for sequentially inputting the data stored in the packet received by the above-described reception procedure, and performing a demodulation process so that continuous reproduction is performed on the input data at a timing based on the master clock;
At a timing based on the master clock, a signal processing procedure for performing a modulation process so that the input signal becomes continuous data;
A packet generated by storing the data obtained by the signal processing procedure for a required data amount, as a control signal for controlling the data transfer rate of the data to be transmitted by the data transmission device, to the data transmission device. On the other hand, a transmission procedure for sequentially transmitting at a predetermined timing,
A data receiving method.

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