JP2004093626A - Method for controlling driving of plasma display panel and driving controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for controlling driving of a plasma display panel, which method and apparatus prevent a change in an average signal level from adversely affecting contrast and to provide a driving controller for the same. <P>SOLUTION: The erasing/resetting discharge stroke Rc and sustaining light emission discharge stroke Ic occupying in a display period of one field are controlled in accordance with the video signal level displayed within one field. More specifically, when the video signal level is high, the number N of pulses is controlled to a smaller number by making the erasing/resetting discharge stroke Rc occupying in the display period of the one field longer, by making the pulse width T of erasing/resetting pulses RPa and RPb longer, by making the pulse voltage V of the erasing/resetting pulses RPa and RPb lower and by making the sustaining light emission discharge stroke Ic shorter. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to driving control of a plasma display panel.
[0002]
[Prior art]
Conventionally, a so-called plasma display panel (hereinafter sometimes abbreviated as “PDP”) is known as a display panel using gas discharge, and the structure and control method of an AC (AC) type PDP are shown in FIGS. This will be described with reference to FIG.
[0003]
FIG. 10 is a perspective view of a part of an AC PDP, and FIG. 11 is an explanatory diagram of electrodes arranged in a matrix of the AC PDP.
[0004]
The AC type PDP shown in FIG. 10 has a linear display electrode 23 formed on a front glass substrate 21 by a pair of a discharge sustaining electrode Xi and a scanning / discharge maintaining electrode Yi, and a linear display electrode 23 formed on a rear glass substrate 25. Two glass plates 21 and 25 are arranged so that the display electrode 23 and the address electrode 27 face each other and are orthogonal to each other. The two electrodes 23 and 27 are arranged in a matrix. Form the display dots 39 (FIG. 11).
[0005]
The display electrode 23 is formed by etching a vapor-deposited transparent conductive film such as ITO (Indium Tin Oxide) into a stripe shape.
[0006]
As described above, the display electrodes 23 of each pair are composed of the sustain electrodes Xi and the scan / discharge electrodes Yi (1 ≦ i ≦ n), and n pairs of display electrodes 23 are formed on the entire display screen. A dielectric layer 29a functioning as a capacitor is formed on the display electrode 23, and a protective film 31 made of MgO is further formed thereon by vapor deposition or the like.
[0007]
On the other hand, between adjacent address electrodes 27, stripe-shaped barrier ribs 33 are provided by thick-film printing, and each display dot is separated and independent. The phosphor 35 is applied on the dielectric layer 29 b formed on the address electrode 27 and on the side surface of the partition 33, and inside the discharge space 37 surrounded by the partition 33 and the front glass substrate 21. A mixed gas of an inert gas containing Xe is sealed.
[0008]
The display is performed by applying an AC voltage between the sustaining electrode Xi, which is the display electrode 23, and the scanning / sustaining electrode Yi, and the display dot 39 to be displayed is selected between any address electrode 27 and the display electrode 23. And discharge is generated at the intersection of these electrodes 23-27. At this time, the phosphor is mainly emitted by excitation light having a wavelength of 147 (nm) in vacuum ultraviolet rays generated by the discharge of Xe.
[0009]
FIG. 12 and FIG. 13 are diagrams showing a drive format in one field display period of the conventional plasma display. FIG. 12 shows a timing chart of a pulse application voltage to each electrode, and FIG. 13 shows a schematic diagram of one field period in FIG.
[0010]
Conventionally, in order to display a multi-gradation image on a plasma display, one field period is divided into a plurality of subfields and displayed. For example, FIG. 13 shows a case where 16 (= 2 ⁴ ) gray levels are realized, and one field period is divided into four subfields of subfields SF1 to SF4, and each subfield has an erasure. The reset process Rc, the address process (writing process) Wc, and the sustaining light emitting process Ic are continuously performed in this order.
[0011]
FIG. 12 shows application timings of various drive pulse voltages applied to the address electrode 27, the sustain electrode Xi, and the scan / discharge electrode Yi of the PDP when performing each of the steps (Rc, Wc, Ic). ing. In FIG. 12, an address pulse applied to the address electrode 27, a pulse commonly applied to all the discharge sustaining electrodes X1 to Xn, and a pulse applied to each scanning / discharge maintaining electrode Yi (in FIG. Y3) is shown on the horizontal axis as the time axis t.
[0012]
In the erasing / resetting process Rc, in displaying an image, since the amount of wall charges of each display dot (discharge cell, pixel) 39 is different due to the previous image, all the display dots ( This is a step of equalizing the condition (for example, the amount of charge) of the wall charge of the discharge cell (39). In general, for erasing (resetting) the wall charge remaining on each of the electrodes Xi and Yi, for example, 12, erase / reset pulses RPa and RPb of opposite polarities are applied to the electrode Xi and the electrode Yi.
[0013]
In the address step (writing step) Wc, following the erasing / resetting step Rc, wall charges are discharged by an address discharge to such an extent that a sustain discharge can be performed on the display dots (discharge cells, pixels) 39 to be lit later. This is a step for storing (selecting and writing dots to be displayed). For example, while applying a predetermined negative scanning pulse SP line-sequentially from the electrode Y1 to the electrode Yn, the scanning pulse SP for each electrode Yi is applied. By applying a positive address pulse AP to the address electrode 27 corresponding to the display dot 39 to be lighted at the timing, an address discharge is generated between the electrode Y of the selected pixel and the address electrode 27 (data writing). Such an address discharge is an AC discharge that ends in a very short time.
[0014]
In the sustain emission discharge step Ic, a wall voltage is induced by the discharge in the address step Wc, and the wall emission is applied by alternately applying positive sustain emission discharge pulses PP to all the electrodes Xi and Yi as shown in FIG. This is a period in which the discharge is maintained by adding the sustain emission discharge pulse PP to the charge, and the light emission amount is controlled. When the sustain emission discharge period Ic ends, the process proceeds to the reset process Rc of the next subfield.
[0015]
In displaying an image of one field, the above steps Rc, Wc, and Ic are repeated in each of the subfields SF1 to SF4 according to pixel data.
[0016]
By the way, when performing so-called ABL (auto brightness level) control for controlling luminance according to the average signal level of the video signal constituting one field, the light emission frequency ratio for each of the sub-fields according to the average signal level In addition, the power consumption is limited by changing the number of times of light emission. At this time, the setting of the number of sustain emission discharges in each subfield is performed by reading table data stored in advance in a RAM or the like into a control circuit in accordance with the average signal level. Specifically, the number of discharges in the sustain emission discharge period Ic for light emission is controlled in accordance with the average signal level, and when the average signal level is high, control is performed to reduce the total number of discharge pulses in the sustain emission discharge step Ic. By doing so, the power consumption was kept low.
[0017]
[Problems to be solved by the invention]
In the conventional control method for reducing the total number of discharge pulses in the sustain emission discharge step (period) Ic when the average signal level is high, the maximum luminance is reduced due to the decrease in the total number of discharges. That is, in the case of the plasma display of the above-mentioned control method, the maximum luminance at the time when the level of the signal is low is about 400 (cd / m ² ). It decreases to about 100 (cd / m ² ).
[0018]
However, the state of the wall charges after the erasing / resetting process Rc for substantially erasing (resetting) the wall charges of all the display dots 17 is not controlled by the average signal level and is always constant. Is constant irrespective of the average signal level and is about 1 (cd / m ² ). When the average signal level is low, the contrast is 400: 1. When the average signal level is high, the contrast is 100: 1. There is a problem that the contrast is greatly reduced by the increase in the level.
[0019]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object of the present invention is to provide a control method and a control apparatus for a plasma display in which a change in an average signal level does not adversely affect contrast.
[0020]
[Means for Solving the Problems]
According to the gist of the present invention, one image display such as one field of a video signal is constituted by a plurality of sub-image displays (sub-fields) in order to perform multi-gradation display. In the drive control of the plasma display panel performing the light emission discharge process, the erase / reset discharge process occupying in the display period of one image display is controlled based on a video signal (video signal level) displayed in one image display.
[0021]
Specifically, it controls the length of the erase / reset discharge process and the sustain emission discharge process, the application time of the erase / reset pulse voltage, and the erase / reset pulse voltage.
[0022]
For example, when the average signal level of the video signal displayed in one image display is high, the erase / reset discharge process is lengthened, the sustain emission discharge process is shortened, and the erase / reset pulse voltage is applied as compared with the case where the average signal level is low. Increase the time and lower the erase / reset pulse voltage.
[0023]
According to the gist of the present invention, since the black luminance level changes depending on the erase / reset pulse voltage value in the erase / reset discharge process, the contrast change is suppressed by controlling the erase / reset pulse voltage value based on the average signal level. It is possible to do.
[0024]
In other words, the average signal level is increased, and control is performed to reduce the total number of discharge pulses in the sustain emission discharge period Ic in order to maintain low power consumption. By performing the control, it is possible to suppress a decrease in contrast.
[0025]
Since the application time of the erase / reset pulse voltage changes by controlling the erase / reset pulse voltage value, the same operation and effect as described above can be obtained by controlling the application time (erase / reset discharge process). Further, since the change in the erase / reset discharge process also changes the length of the sustain emission discharge process, the same operation and effect can be obtained by controlling the reverse length.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Since the structure of the plasma display panel itself is the same as that described above, the description will be omitted, and the same parts as those in the above configuration will be denoted by the same reference numerals, and the description will be omitted.
[0027]
In the present embodiment, the black luminance level is controlled by the average signal level by controlling the sustain emission discharge process Ic and the erasure / reset process Rc based on the average signal level of pixel data in a predetermined image display range (one field or the like). It controls and suppresses a change in contrast, and enables a sharp image display.
[0028]
FIG. 1 shows a timing chart of a pulse application voltage to each electrode, and FIG. 2 shows a schematic diagram of one field period in FIG. In the present embodiment, in order to facilitate comparison with the conventional technique shown in FIG. 13, one field period is divided into four subfields consisting of subfields SF1 to SF4, and each subfield has an erasing / resetting process Rc , The address process Wc and the sustain emission process Ic will be described. The number of subfields is not limited, and may be increased to about 20 subfields.
[0029]
In the present embodiment, based on the average signal level, the length (period) of the sustaining light emission process Ic and the number of pulses of the sustaining pulse PP in each subfield, the discharge sustaining electrode Xi in the erase / reset process Rc, and the scanning are performed. The pulse width T (FIG. 1) of the erase / reset pulses RPa and RPb of the sustain electrode Yi and the pulse voltage V (FIG. 1) of the erase / reset pulse RPa of the electrode Xi are controlled.
[0030]
(Black brightness control)
First, black luminance level control by reset discharge process control in the erase / reset process Rc will be described.
FIG. 3 shows the relationship between the erase / reset pulse width (application time) and the erase / reset discharge voltage in the erase / reset process Rc. The width T on the horizontal axis represents the pulse width T of the erase / reset pulses RPa and RPb of the electrodes Xi and Yi in FIG. 1, and the voltage V on the vertical axis represents the erase / reset discharge start voltage V. It becomes the pulse voltage V of the erase / reset pulse RPa applied to the one electrode X1 to Xn.
[0031]
As shown in FIG. 3, as the pulse width T of the erase / reset pulses RPa and RPb increases, the erase / reset discharge start voltage V for generating the erase / reset discharge decreases. This is because the discharge phenomenon is a phenomenon based on the statistical probability.When a high voltage is applied, a sufficient discharge probability can be obtained even with a short pulse width, and when the voltage is low, the discharge probability is low. Therefore, a short pulse width does not provide a sufficient probability, but a sufficiently large value is obtained as the time integral of the discharge probability by increasing the erase / reset discharge pulse width T, so that a sufficient erase / reset discharge is generated. It is possible to do.
[0032]
FIG. 4 shows the relationship between the pulse width T of the erase / reset pulses RPa and RPb and the black luminance BN. In general, in a plasma display, since a predetermined erase / reset discharge is performed in each of the subfields SF1 to SF4, the black luminance BN becomes a finite value and is about 1 (cd / m ² ). On the other hand, as shown in FIG. 4, as the pulse width T of the erase / reset pulses RPa and RPb increases, the black luminance BN decreases accordingly. This is due to a decrease in the light emission amount due to a decrease in the erase / reset discharge start voltage V shown in FIG. According to experiments, it was found that by increasing the pulse width T, the black luminance BN could be reduced to about 0.5 (cd / m ² ), which is about half that of the related art.
[0033]
Therefore, in the present embodiment, for example, by increasing the pulse width T of the erase / reset pulses RPa and RPb applied to the electrodes X1 to Xn and the electrodes Y1 to Yn in the erase / reset process Rc, for example, the black luminance BN is reduced by about half compared to the conventional art. Of about 0.5 (cd / m ² ), and when the peak luminance is constant, the contrast can be doubled as compared with the related art. For example, when the average signal level is low, the peak luminance is 400 (cd / m ² ) and the black luminance level is 1 (cd / m ² ) as before, and when the average signal level is high, the peak luminance is the conventional one. Similarly, 100 (cd / m ² ) and the black luminance level are 0.5 (cd / m ² ). That is, when the average signal level is low, the contrast is 400: 1, and when the average signal level is high, the contrast is 200: 1. It becomes possible.
[0034]
(Sustain luminescence discharge process control)
Next, the control of the sustain emission discharge process Ic based on the average signal level will be described.
In FIG. 5, the vertical axis represents the number of sustain emission discharges (the number of sustain emission discharge pulses PP) N, the horizontal axis represents the display gray scale M, and the number of sustain emission discharges N and the display gray scale M when the average signal levels are different. Shows the relationship.
[0035]
In the present embodiment, as shown in FIG. 5, when the average signal level is low (reference L), the number N of the sustain emission discharge pulses PP is increased, and when the average signal level is high (reference H), the sustain light emission discharge pulse PP is maintained. The number N of the light emission discharge pulses PP is controlled to be small.
[0036]
FIG. 6 shows an example in which the average signal level is divided into three levels, large, medium, and small, and the number of pallets of the sustain emission discharge pulse PP for each subfield within one field period for each level. In the present embodiment, as shown in FIG. 6, the number of sustain discharge pulses in a subfield is changed according to the average signal level. However, even if the average signal level changes, the ratio of the number of sustain discharge pulses in each subfield within one field period does not change. This is because even if the average signal level changes, the γ characteristic on display (secondary electron emission coefficient due to ion collision) does not change.
[0037]
Although FIG. 6 shows a case where the average signal level is divided into three levels using two thresholds, the number of levels (the number of thresholds) can be appropriately selected in consideration of processing efficiency and the like. .
[0038]
FIG. 7 illustrates the relationship of FIG. 6, in which the average signal levels are shown as (a), (b), and (c) in the order of small, medium, and large, and within the subfield within one field period. 3 shows a state of time division in each step. In the present embodiment, control is performed to change the length of each sustain emission discharge process Ic of each subfield in one field according to the average signal level. The length of each sustain emission discharge process Ic by such control is controlled such that the sustain emission discharge pulse shown in FIG. 6 falls within the process Ic. That is, control is performed such that the number N of the sustain emission discharge pulses PP in the subfield is changed according to the average signal level, and the length of the sustain emission discharge process Ic is changed.
[0039]
(Erase / reset process control)
Further, in the present embodiment, when the average signal level is high, the control is performed such that the period of the erasure / reset process Rc becomes longer by utilizing the fact that the total process period in one field of the sustain emission discharge process Ic becomes shorter. I do. In FIG. 7, according to (a), (b) and (c), the period of the erase / reset step Rc is lengthened, and the period of the sustain emission discharge step Ic is shortened.
[0040]
Further, along with controlling the length of the period of the erase / reset step Rc, the pulse width T and the voltage V of the erase / reset pulses RPa and RPb are also controlled. When the average signal level is high, the erase / reset pulse is controlled. Control is performed such that the width T of RPa and RPb is increased and the discharge voltage V is reduced.
[0041]
As described above, the black luminance level can be controlled by the average signal level by controlling the erase / reset step Rc and / or the sustain emission discharge step Ic by the average signal level in one field by the above-described control method. Changes can be suppressed.
[0042]
FIG. 9 shows a conventional plasma display drive control method for comparison, in which the time division of each step Rc, Wc, Ic in a sub-field depends on the case where the average signal level is small, medium, and large. It shows the situation.
[0043]
In the conventional method of driving a plasma display, the length of each sustain emission discharge process Ic of each subfield in one field is not changed according to the average signal level. Only the sustain emission pulse PP shown in FIG. 6 is allocated to each process. That is, the period (length) of the sustain emission discharge process Ic is the same, and the density of the sustain emission discharge pulse PP in the sustain emission discharge process Ic is set to change. Further, the period of the erase / reset process Rc and the width T and the voltage V of the erase / reset pulses RPa and RPb are not changed according to the average signal level, and are constant. Therefore, the black luminance level was always constant.
[0044]
(Control device)
FIG. 9 shows a block diagram of a drive control device for a plasma display according to the present embodiment. The drive control device includes an average signal level detector 3, a sustain discharge controller 5, an X and Y electrode driver 7, an address signal controller 9, and an address driver 11.
[0045]
The average signal level detector 3 receives the video signal 1 and detects an average signal level 3a of pixel data in a predetermined image display range, for example, one field. The average signal level 3a means the average of the signal levels of the pixel data in the predetermined area.
[0046]
Based on the average signal level 3a, the sustain discharge control unit 5 determines the period in each of the sub-fields SF1 to SF4 in the sustain emission discharge step Ic, the number N of the sustain emission discharge pulses PP, and the pulse application timing. , The pulse width T and voltage V of the erase / reset pulses RPa, RPb, the pulse application timing, and the application timing of the pulses are determined, and the determined content data 5a is stored in the electrodes Xi, Yi (display electrode 23). The X, Y electrode driver 7 controls the electrodes Xi, Yi based on the determined content data 5a.
[0047]
The method of determining the decision content data 5a is that, when the average signal level 3a is low, the period ratio of the sustain emission discharge step Ic in one field is increased, the number of pulses N is increased, and the average signal level is high. In this case, the period ratio of the sustain emission discharge step Ic in one field is reduced, and the number of pulses N is controlled to be small. When the average signal level 3a is high, the ratio of the period of the erasure / reset process Rc is controlled to be long by utilizing the fact that the period ratio of the sustain emission discharge step Ic in one field is short. When the average signal level is high, control is performed so that the width T of the erase / reset pulses RPa and RPb is increased and the discharge voltage V is reduced.
[0048]
The address driver 9 creates display signal data (address data) according to the pixel data of each field from the video signal 1 and also changes the start timing of the address step Wc according to the average signal level 3a. , And performs a timing adjustment control of the address pulse AP, and outputs a timing adjustment control signal 9 a to the address driver 11. The address driver 11 controls the address electrodes 27 based on the timing adjustment control signal 9a.
[0049]
With the above configuration, the black luminance level is controlled by the average signal level, the change in contrast is suppressed, and a sharp image can be displayed.
[0050]
(Other embodiments)
Although the preferred embodiment of the present invention has been described in the above embodiment, the present invention is of course not limited to this.
For example, in the embodiment of FIG. 1, the control of the erase / reset discharge voltage V of the pulse width T is performed only by the drive pulse 11 of the X electrode, and the Y electrode drive pulse 12 controls only the pulse width T. Although an example is shown, the present invention is not limited to this, and the voltage V can be appropriately controlled for both the erase / reset pulse applied to the X and Y electrodes.
[0051]
Although the image display range for obtaining the average signal level has been described with one field in the above embodiment, it can be obtained from, for example, one frame, a plurality of fields, a plurality of frames, and their approximate areas.
[0052]
Further, as described above, in the present embodiment, the average signal level is divided into three stages of large, medium and small, and the above-mentioned parameters of the sustain emission discharge step Ic and the erase / reset step Rc are changed corresponding to the average signal level. May be divided into any number of stages, and can be appropriately selected in consideration of processing efficiency and the like.
[0053]
【The invention's effect】
As described above, according to the gist of the present invention, it is possible to suppress a decrease in display contrast even when the average signal level of a signal input to the plasma display increases. Therefore, it is possible to maintain a sharp display state with high contrast in all display signals.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a drive pulse waveform of each electrode according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a subfield according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram of a black luminance control method according to the embodiment of the present invention.
FIG. 4 is an explanatory diagram of a black luminance control method according to the embodiment of the present invention.
FIG. 5 is an explanatory diagram illustrating a relationship between a display gray scale M and a sustain emission discharge pulse N according to the embodiment of the present invention.
FIG. 6 is an explanatory diagram showing allocation of sustain emission discharge pulses in each subfield when the average signal level changes according to the embodiment of the present invention.
FIG. 7 is an explanatory diagram showing changes in an erase / reset process Rc, an address process Wc, and a sustain emission process Ic in a subfield when the average signal level changes according to the embodiment of the present invention.
FIG. 8 is an explanatory diagram showing changes in an erase / reset process Rc, an address process Wc, and a sustain emission process Ic in a subfield when the average signal level changes in the related art.
FIG. 9 is a schematic block diagram of a drive control device for a plasma display panel according to an embodiment of the present invention.
FIG. 10 is a perspective view showing a conventional AC type PDP.
FIG. 11 is an explanatory diagram showing pixels of a conventional AC PDP.
FIG. 12 is an explanatory diagram showing a conventional drive pulse waveform for each electrode.
FIG. 13 is an explanatory diagram of a conventional subfield.
[Explanation of symbols]
SF1 to SF4 Subfield Rc Erase / Reset Step Wc Address Step Ic Sustain Light Emission Discharge Period Xi Discharge Sustain Electrode Yi Scan / Discharge Sustain Electrodes RPa, RPb Erase / Reset Pulse PP Sustain Light Emission Discharge Pulse T Pulse Width V Erase / Reset Discharge Start Voltage BN Black luminance M Display gradation N Number of sustain emission discharges

Claims (7)

A single image display of a video signal is composed of a plurality of sub-image displays, and the sub-image display includes a plasma display panel having an erasure / reset discharge process for eliminating or substantially equalizing wall charges inside the plasma display panel. In the drive control method,
A drive control method for a plasma display panel, comprising: controlling the erase / reset discharge process occupying in a display period of the one-image display based on a video signal displayed in the one-image display. The method according to claim 1, wherein the control of the erase / reset discharge process is a control of the length of the erase / reset discharge process. The erase / reset discharge step includes an application step of applying an erase / reset pulse voltage to the plasma display panel,
2. The method according to claim 1, wherein the control of the erase / reset discharge process is a control of the length of the application step. The erase / reset discharge step includes an application step of applying an erase / reset pulse voltage to the plasma display panel,
The method according to claim 1, wherein the control of the erase / reset discharge process is control of the erase / reset pulse voltage. One image display of a video signal is composed of a plurality of sub-image displays, and the sub-image display is a plasma display panel that performs an erasure / reset discharge process that erases or substantially equalizes wall charges inside the plasma display panel. In the drive control device,
When the average signal level of the second video signal is higher than the average signal level of the first video signal,
A drive control device for a plasma display panel, wherein the length of the erase / reset discharge process period for the second video signal is controlled to be longer than the length of the erase / reset discharge process period for the first video signal. . One image display of a video signal is composed of a plurality of sub-image displays, and the sub-image display is a plasma display panel that performs an erasure / reset discharge process that erases or substantially equalizes wall charges inside the plasma display panel. In the drive control device,
When the average signal level of the second video signal is higher than the average signal level of the first video signal,
The voltage value of the erase / reset pulse applied to the plasma display panel during the erase / reset discharge process for the second video signal is applied to the plasma display panel during the erase / reset discharge process for the first video signal. A driving control device for a plasma display panel, wherein the driving control is performed to be lower than the voltage value of the reset pulse. One image display of a video signal is composed of a plurality of sub-image displays. The sub-image display includes an erasing / resetting discharge process for erasing or substantially equalizing wall charges inside the plasma display panel and a pixel of the image signal. In a plasma display panel drive control device that performs a sustain emission discharge process of performing emission discharge by the number of times of emission corresponding to the data,
An average signal detection unit that detects an average signal of the video signal,
A drive control device for a plasma display panel, comprising: a control unit configured to change a length of the erase / reset discharge process and a sustain emission discharge process in an image display period of one image display based on the average signal.

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