JP2004048991A - Capacitor controlling device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the numer of circuits in a circuit where a plurality of capacitors are connected in series. <P>SOLUTION: This capacitor controlling device is provided with a unit capacitor row in which a plurality of the capacitors are connected in series and that is divided into units, a fundamental withstand-voltage circuit that is connected to the topmost positive terminal and the bottommost negative terminal of the unit capacitor row, and a low withstand-voltage circuit whose withstand-voltage is lower than the fundamental withstand-voltage circuit. The fundamental withstand-voltage circuit has a fundamental withstand-voltage differential amplifier, which converts the voltage of each capacitor with reference to the bottommost terminal of the unit capacitor row and input it to the low withstand-voltage circuit. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a power storage device such as a lithium secondary battery and an electric double layer capacitor, a power storage device in which a large number of power storage devices are connected in series, an evaluation device for evaluating these, and a power storage control device for a manufacturing device for these devices.
[0002]
[Prior art]
Conventionally, there has been a battery protection circuit that detects each voltage of a series-connected secondary battery and stops charging when any of the secondary batteries reaches a full charge. Such a technique is described, for example, in JP-A-8-78060.
[0003]
FIG. 13 shows a conventional battery protection circuit. In the figure, 1301 is a secondary battery, 1302 is a voltage detection circuit, 1303 is a resistor, 1304 is a comparator, and 1305 is a FET.
[0004]
Two secondary batteries 1301 are connected in series, and a voltage detection circuit 1302 and two series-connected resistors 1303 are connected to both ends of each secondary battery 1301. The resistor 1303 connected in series divides the voltage of the secondary battery 1301 to create a reference voltage.
[0005]
The power supplies of the two comparators 1304 are connected to both ends of the secondary battery 1301 connected in series, and the input of the comparator 1304 is connected to the reference voltage based on resistance voltage division and the output of the voltage detection circuit 1302, respectively. I have. Further, both outputs of the comparator 1304 were inserted in series with the secondary battery 1301.
It is connected to the gate of FET1305.
[0006]
In this case, the voltage of the secondary battery 1301 is detected by the voltage detection circuit 1302, and the detected value is compared with a reference voltage by resistance division by the comparator 1304. Then, when one of the secondary batteries 1301 reaches full charge and the detection value of the voltage detection circuit 1302 exceeds the reference voltage, the output of the comparator 1304 becomes low, the FET 1305 is turned off, and charging is stopped.
[0007]
[Problems to be solved by the invention]
In the conventional battery protection circuit, the detection values of the respective voltage detection circuits 1302 have different potential levels with respect to the lowest negative terminal of the secondary battery 1301 connected in series. For this reason, it is necessary to provide each of the secondary batteries 1301 with a resistor 1303 connected in series for generating a reference voltage for defining a full charge. As described above, a circuit that performs the same function for each secondary battery also requires a circuit suitable for each potential level for each secondary battery. In addition, the withstand voltage of the comparator 1304 that connects them requires the total voltage of the batteries 1301 connected in series.
[0008]
If a plurality of batteries 1301 are further connected in series, the number of circuits corresponding to each potential level increases, and the cost, size, and power consumption for realizing this increase. Further, components such as the withstand voltage comparator 1304 that satisfies the total voltage of the batteries connected in series do not actually exist, and this circuit cannot be realized.
[0009]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a battery control device capable of reducing the number of circuits in a circuit in which a plurality of capacitors are connected in series.
[0010]
[Means for Solving the Problems]
A battery control device according to the present invention includes a plurality of capacitors connected in series, a unit capacitor row divided into a certain unit, and a basic withstand voltage circuit connected to the highest plus terminal and the lowest minus terminal of the unit capacitor row. And a low-withstand voltage circuit having a lower withstand voltage than the basic withstand voltage circuit, wherein the basic withstand voltage circuit has a basic withstand voltage differential amplifier, and the basic withstand voltage differential amplifier determines the voltage of each capacitor at the bottom of the unit capacitor row. The signal is converted with the minus terminal as a reference and input to the low withstand voltage circuit.
[0011]
The basic withstand voltage circuit includes a level shift circuit for converting a voltage level, the basic withstand voltage differential amplifier includes a power cutoff circuit, and the low withstand voltage circuit includes the power cutoff circuit via the level shift circuit. May be controlled.
[0012]
Alternatively, both ends of the capacitor are connected to the low withstand voltage circuit via a constant voltage generating circuit for generating a constant voltage.
[0013]
Furthermore, the upper and lower low-voltage circuits are connected via a high-voltage differential amplifier that satisfies the total withstand voltage of the unit capacitor row and the low-voltage circuit.
[0014]
Alternatively, both ends of the battery are respectively connected to analog inputs of an A / D converter, and a digital output of the A / D converter is connected to the low withstand voltage circuit via a digital level shift.
[0015]
Then, the upper and lower low-voltage circuits are connected via a digital level shift that satisfies the total withstand voltage of the unit capacitor row and the low-voltage circuit.
[0016]
In these, it is preferable to add a current detection circuit for detecting a current flowing through the unit battery array, and to input the input of the low withstand voltage circuit in synchronization with a change in the current detected by the current detection circuit.
[0017]
Further, these low-voltage circuits may be formed by a CMOS process or a bipolar process, and circuits other than the unit capacitor row may be formed into ICs by a bipolar process.
[0018]
Further, a temperature detection circuit is added, the low voltage circuit has a microcomputer, and the microcomputer has charge / discharge time at the time of charge / discharge and data of the voltage of the capacitor at each current and each temperature. The detected value is compared with the data to calculate and correct.
[0019]
In the case where the current flowing through the capacitor row is a current including a ripple having a cycle of tc, the low withstand voltage circuit has a circuit for sequentially reading the voltage of each capacitor in the unit capacitor row in a cycle of a cycle of tr. And tr, a relationship of tc ≧ 2tr is established.
[0020]
In the battery control device having the above-described configuration, the voltages of the capacitors having different potential levels are converted by the basic withstand voltage differential amplifier with reference to the lowest negative terminal of the unit battery row, and input to the low withstand voltage circuit having a low withstand voltage.
[0021]
When it is not necessary to input the voltage of the capacitor to the low withstand voltage circuit, the power cutoff circuit is controlled via the level shift circuit based on the signal of the low withstand voltage circuit to cut off the power consumption of the basic withstand voltage differential amplifier.
[0022]
When both ends of the capacitor are connected to a low withstand voltage circuit via a constant voltage generating circuit, the potential level of the low withstand voltage circuit is changed by the constant voltage generating circuit without changing the potential difference between both ends of the capacitor. Lower to the level.
[0023]
Alternatively, when both ends of the capacitor are connected to the analog input of the A / D converter, and the digital output of the A / D converter is connected to the low-voltage circuit via the digital level shift, the voltage of each capacitor is set to the respective voltage. The potential levels are converted into digital values, and these potential levels are converted into the potential levels of the low breakdown voltage circuit by digital level shift.
[0024]
Furthermore, when connecting between the low withstand voltage circuits of the upper and lower unit capacitor arrays, a high withstand voltage differential amplifier that satisfies the total withstand voltage of the unit capacitor array and the low withstand voltage circuit, or a digital level shift is used to determine the difference in the potential level. Convert.
[0025]
Then, the input of the voltage of each capacitor to the low withstand voltage circuit is input in synchronization with the fluctuation of the current detected by the current detection circuit.
[0026]
Further, the detected value of each battery voltage is compared with the data of the charge / discharge time and the voltage of the battery at each current and each temperature and corrected.
[0027]
As a result, it becomes possible to realize a low-cost, small-sized, low-power-consumption, high-precision, high-noise margin, high-reliability battery control device with a small number of circuits.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the figure, the same reference numerals are given to those having two or more identical parts, and the description is omitted.
[0029]
FIG. 1 is a diagram showing a first embodiment of the present invention. In the figure, 101 is a capacitor, 102 is a unit capacitor row, 103 is the highest plus terminal, 104 is the lowest minus terminal, 105 is a basic withstand voltage circuit, 106 is a low withstand voltage circuit, 107 is a basic withstand voltage differential amplifier, and 108 is a basic withstand voltage differential amplifier. It is a low voltage source.
[0030]
Four power storage devices 101 are connected in series to form a unit power storage device array 102. Then, the unit battery array 102 is connected via a basic withstand voltage circuit 105 to a low withstand voltage circuit 106 powered by a low voltage source 108.
[0031]
The basic withstand voltage circuit 105 includes four basic withstand voltage differential amplifiers 107, and the power supplies of these basic withstand voltage differential amplifiers 107 are all connected to the highest plus terminal 103 and the lowest minus terminal 104. Both ends of each capacitor 101 are connected to the input of the basic withstand voltage differential amplifier 107. The basic withstand voltage differential amplifier 107 converts the inter-terminal voltage of each battery 101 having a different potential level with reference to the potential level of the lowest minus terminal 104. These outputs are connected to the low breakdown voltage circuit 106, respectively.
[0032]
The low withstand voltage circuit 106 compares the converted inter-terminal voltage with a reference value, outputs a charge / discharge control signal, and compares the inter-terminal voltages. A control signal for eliminating the variation is output.
[0033]
Assuming that the battery 101 is a lithium secondary battery, its average voltage is 3.6 V, and the potential of the highest positive terminal 103 is based on the lowest negative terminal 104.
It becomes 13.6V. When the low-voltage circuit 106 is composed of an A / D converter having a general power supply voltage rating of 5 V and an MCU (microcomputer), the low-voltage source 108 generates a voltage of 5 V and supplies it to these. As is apparent here, if the highest positive terminal 104 is directly connected to the low withstand voltage circuit 106, a voltage exceeding the withstand voltage of the low withstand voltage circuit 106 will be applied, and the low withstand voltage circuit 106 will be destroyed. However, in the present invention, the voltage of each capacitor 101 is reduced by the basic withstand voltage differential amplifier 107 to the lowest negative terminal.
Since the voltage between the terminals is converted based on the potential level of the capacitor 104 and the average voltage of 3.6 V between the terminals of each capacitor 101 is input, there is no problem with a general A / D converter or MCU having a low power supply voltage rating of 5 V and a low withstand voltage. It becomes possible to connect. Then, the detected inter-terminal voltage is processed by the common low withstand voltage circuit 106, so that the number of circuits can be reduced. Further, since the power supply voltage of the low withstand voltage circuit 106 is low, power consumption can be reduced. Further, in general, a circuit with a low withstand voltage can be configured at a lower cost and smaller in size than a circuit with a high withstand voltage.
[0034]
Further, the basic withstand voltage differential amplifier 107 directly receives the voltage between the terminals of the battery 101 in a differential manner, converts only the potential level, and outputs it. The terminal voltage is not converted in the conversion process. For this reason, an error included in the converted inter-terminal voltage is small and accurate voltage detection can be performed. Further, since an average voltage of 3.6 V and a voltage close to the full input voltage of 5 V of the low withstand voltage circuit 106 are input, noise resistance of the detected value is ensured.
[0035]
Thus, according to the present invention, an inexpensive, small-sized, low-power-consumption, low-power, high-accuracy, high-accuracy, high-reliability battery control device can be realized.
[0036]
Here, in the figure, the four unit capacitors 101 are connected in series in the unit capacitor column 102, but the unit capacitor array 102 can also be realized by other number of connected units. However, the basic withstand voltage circuit 105 can be inexpensively configured if the number of the series connected unit capacitor rows 102 is set so that the voltage of the unit capacitor row 102 is within the rating of a general semiconductor device. For example, in the case of a lithium secondary battery, the maximum electromotive voltage is 4.2 V, which is 16.8 V in four series and 33.6 V in eight series, and is suitable for use of a general semiconductor device of 18 V and 36 V. If the number of these circuits is less than the number of series connections, these circuits can be easily realized by the same chip IC or hybrid IC, the number of components can be reduced, and the cost can be further reduced.
[0037]
In particular, in the case of an IC, since the low withstand voltage circuit 106 has a low withstand voltage, a CMOS process can be employed. In addition, the other circuits except for the battery array 102 may employ a bipolar process having a relatively high withstand voltage.
[0038]
FIG. 2 is a diagram showing a second embodiment of the present invention. In the figure, reference numeral 201 denotes a MUX (multiplexer).
[0039]
The low withstand voltage circuit 106 includes a MUX 201, an A / D converter, and an MCU. One output of each of the basic withstand voltage differential amplifiers 107 is sequentially selected by the MUX 201 and input to the A / D converter. According to this, the inputs of the A / D converter and the MCU are limited to one channel, and the number of channels can be reduced.
[0040]
As described above, since the detected inter-terminal voltage is converted to a common potential level, circuits that perform similar functions can be shared, and the number of circuits can be reduced. In addition, a general-purpose circuit configuration can be employed for the low-withstand-voltage circuit 106, and variations in the circuit configuration can be expanded.
[0041]
FIG. 3 is a diagram showing a third embodiment of the present invention. In the figure, 301 is a level shift circuit, and 302 is a power cutoff circuit.
[0042]
The basic withstand voltage differential amplifier 107 is a P-type MOS transistor as its constant current source.
Q <b> 1 also serves as the power cutoff circuit 302. The MUX 201 included in the low withstand voltage circuit 106 includes a transfer gate including a P-type MOS transistor QT,
The decoder DEC selects the QT and drives the gate of the QT. Further, the output of the DEC, that is, the gate of the QT is connected to the power cutoff circuit 302 via the level shift circuit 301.
[0043]
The level shift circuit 301 includes resistors RUH and RUL and an N-type MOS transistor
The QU is connected in series between the highest plus terminal 103 and the lowest minus terminal 104, the gate of the QU is input, and the common connection point of RUH and RUL is output. Then, when the QU is turned on and off, an amplitude corresponding to the division ratio of RUH and RUL is output. That is, the low voltage potential level of the low breakdown voltage circuit 106 is converted into the voltage and potential level of the basic breakdown voltage circuit 105.
[0044]
Thus, the MUX 201 and the power cutoff circuit 302 are linked. When the voltage between terminals of the battery 101 is not read, that is, when the MUX 201 is not selected, the current consumption of the basic withstand voltage differential amplifier 107 is cut off. Thus, low power consumption is achieved.
[0045]
FIG. 4 is a diagram showing a fourth embodiment of the present invention. In the figure, reference numeral 401 denotes a constant voltage generation circuit, which is composed of a plurality of diodes here. When the diode is energized in the forward direction, the built-in potential causes the
A constant voltage of 0.7V results. Similarly, a circuit using the breakdown voltage of the Zener diode can be used as a circuit for generating a constant voltage.
[0046]
Both ends of the capacitor 101 are connected to the low breakdown voltage circuit 106 via a constant voltage generation circuit 401 composed of diodes having the same number of elements. Further, the common part of the constant voltage generation circuit 401 connected to the common connection point of the capacitors 101 is integrated into one.
[0047]
As a result, the potential level between the terminals of the capacitors 101 is dropped to the potential level of the low breakdown voltage circuit 106 without changing the voltage between the terminals.
[0048]
For this reason, it is possible to realize a low-cost, small-sized, low-power-consumption, highly-accurate, highly-tolerant, and highly-reliable capacitor control device with a small number of circuits.
[0049]
FIG. 5 is a diagram showing a fifth embodiment of the present invention. In the figure, 501 is a unit unit, and 502 is a high voltage differential amplifier.
[0050]
The high withstand voltage differential amplifier 502 is composed of a differential amplifier having a total withstand voltage of the unit battery array 102 and the low withstand voltage circuit 106.
[0051]
The unit unit 501 includes a unit battery array 102 and a basic withstand voltage circuit 105 and a low withstand voltage circuit 106 having the lowermost negative terminal 104 as a reference potential.
[0052]
Then, the low withstand voltage circuits 106 in the two unit units 501 having different potential levels are converted only by the high withstand voltage differential amplifier 502 and connected.
[0053]
Similarly, even when a plurality of unit units 501 are further connected in series, it is possible to connect the low withstand voltage circuit 106 by providing a plurality of stages of the high withstand voltage differential amplifier 502.
[0054]
In this way, by connecting the unit units 501 by the high-withstand-voltage differential amplifier 502, it is possible to integrate the outputs of the plurality of low-withstand-voltage circuits 106 into one output of the low-withstand-voltage circuit 106 in the final stage. . This is particularly suitable when the low breakdown voltage circuit 106 includes an analog element.
[0055]
FIG. 6 is a diagram showing a sixth embodiment of the present invention. In the figure, reference numeral 601 denotes an A / D converter, and 602 denotes a digital level shift.
[0056]
An A / D converter 601 is connected to both ends of each capacitor 101, and an analog terminal voltage of the capacitor 101 is converted into a digital value. The output of each A / D converter 601 is connected to the low withstand voltage circuit 106 via a digital level shift 602.
[0057]
In the digital level shift 602, a P-type MOS transistor QD and resistors RDH and RDL are connected in series between the highest plus terminal 103 and the lowest minus terminal 104, the gate of QD is input, and the common connection point of RUH and RUL is connected. Output. When the QD is turned on and off, an amplitude corresponding to the division ratio of RUH and RUL is output. That is, the digital outputs having different potential levels of the respective A / D converters 601 are converted and unified into the potential levels of the low breakdown voltage circuit 106.
[0058]
Here, since the A / D converter 601 is connected to both ends of the battery 101, the withstand voltage of the A / D converter 601 can be a small value corresponding to the voltage between terminals of the battery 101. Further, since the analog value of the voltage between terminals of the battery 101 is converted into a digital value, the noise resistance and reliability until the value is transmitted to the low withstand voltage circuit 106 are improved.
[0059]
FIG. 7 is a diagram showing a seventh embodiment of the present invention. In the figure, reference numeral 701 denotes a digital level shift, which is constituted by a series connection of a P-type MOS transistor QDO and resistors RDH and RDL, and a series connection of resistors RUH and RUL and an N-type MOS transistor QUAO.
[0060]
The unit unit 501 includes a unit battery array 102 and a basic withstand voltage circuit 105 and a low withstand voltage circuit 106 having the lowermost negative terminal 104 as a reference potential.
[0061]
Then, the digital level shift 701 receives the gates of QDO and QUAO as inputs,
A common connection point of RDH and RDL and a common connection point of RUH and RUL are output, and bidirectionally connect the low breakdown voltage circuits 106.
[0062]
In these operations, when QDO turns ON and OFF, the voltage drops to an amplitude and a voltage level corresponding to the voltage division ratio of RDH and RDL. When the QUAO is turned ON and OFF, the voltage is increased to an amplitude and a voltage level corresponding to the division ratio of RUH and RUL.
[0063]
Similarly, when a plurality of unit units 501 are further connected in series, it is possible to connect the low withstand voltage circuits 106 by providing a plurality of stages of digital level shifts 701.
[0064]
In this way, by connecting the unit units 501 by the digital level shift 701, it is possible to connect the outputs of the plurality of low-voltage circuits 106. In particular, when the low withstand voltage circuit 106 includes an MCU, it is possible to communicate with each other.
[0065]
FIG. 8 is a diagram showing an eighth embodiment of the present invention. Battery in this embodiment
The configuration of 101 is almost the same as that of FIG. That is, an A / D converter 601 is provided for each unit battery array 102 in which the battery 101 is connected in series, and the output of the A / D converter 601 is connected to the lowest minus terminal 104 via the digital level shift 602. It is converted into a digital signal that is used as a reference potential. The output of the digital level shift 602 is selectively transmitted to the MCU in the MUX 201.
[0066]
The feature of this embodiment lies in how to take timing when the MUX 201 selectively transmits the voltage of the unit battery array 102 to the MCU. That is, a series of unit capacitors connected in series
The current of 102 is measured using a shunt resistor RS provided in a current detection circuit 801, and the voltage drop of the shunt resistor RS is amplified by an amplifier AMPS provided in 801,
The selection using the MUX 201 or the MCU is performed according to the output of the AMPS.
[0067]
There is an impedance inside the unit battery array 102, and this impedance shows an inductive characteristic at a high frequency. For this reason, when a charging current or a discharging current having a large current time change (di / dt) flows through the unit capacitor array 102, a noise voltage determined by the product of the impedances di / dt is generated. There was a problem that the voltage could not be measured.
[0068]
In the present embodiment, the timing at which the charging current or the discharging current flows is detected by the current detection circuit 801, and the MUX 201 takes in the voltage of the battery 101 according to this timing as shown in FIG.
[0069]
The current detection means provided in the current detection circuit 801 may be a method such as a current transformer instead of the shunt resistor.
[0070]
Alternatively, as will be described later, since the current flowing through the unit battery array 102 is controlled by a charge / discharge device provided outside the battery 101, the timing at which the charge / discharge device controls the current (ie, modulation such as pulse width control or the like) A method may be adopted in which the MUX 201 takes in the voltage of the battery 101 according to the wave frequency).
[0071]
In the embodiment of FIG. 8, there is a temperature detecting circuit 802 as a newly provided circuit means other than the current detecting circuit 801. The temperature detecting circuit 802 measures the temperature around the unit battery array 102 and transmits it to the MCU. How to use the temperature detection circuit 802 will be described later.
[0072]
FIG. 9 shows a specific example of the MUX selection timing. In this figure, V1 to V4 displayed as MUX signals represent the capacitors 101 whose voltages are respectively measured, and the selection operation is periodically repeated with tr being the time involved in selecting V1 to V4.
[0073]
The current I is a charging current or a discharging current flowing through the unit battery array 102, and a control cycle of the charging / discharging device that externally controls the current I is represented by tc. Here, it is assumed that the charge / discharge device controls the current I by general pulse width control (PWM control).
[0074]
The embodiment of FIG. 9 illustrates a case where the pulse width of the PWM control is approximately 50%. The current I increases in the first half of tc, and decreases in the second half of tc. In this example, if the time tr relating to the selection of V1 to V4 is about の of the charge / discharge control cycle tc, the voltage information selected by the MUX and transmitted to the MCU in the first half of tc is stored in the battery 101. Is superimposed on the noise voltage ΔV determined by the product of the internal impedance and di / dt. Also, since the current in the latter half 50% tends to decrease, di / dt becomes a negative value, and a noise voltage of -ΔV is superimposed on the voltage information transmitted to the MCU during this period. Therefore, the MCU compares the voltage information received within the period of the charge / discharge control cycle tc, and removes the noise voltage component included in each.
[0075]
As this method, the voltage information of the unit capacitor in the period of tc is calculated by calculating from the voltage information related to the same capacitor 101 (for example, taking an average value), or selecting one according to charging and discharging. To one. This method uses the time tr related to the selection of the MUX or the charge / discharge control cycle tc as a kind of filter period. In a situation where the current I pulsates, the influence of the transient phenomenon can be obtained by using this filter period. Detecting with excellent accuracy is possible.
[0076]
FIG. 10 shows charge / discharge characteristics of a lithium secondary battery as an example of the battery 101. In the charge / discharge characteristics, a cycle of charge, pause, discharge, pause, and charge is repeated. Here, the battery voltage rapidly increases with time when shifting from pause to charging, and conversely, when shifting from discharge period to discharging, the battery voltage sharply decreases with time. These are all because the voltage drop of the internal impedance of the battery due to the flow of the charging current or the discharging current is superimposed. That is, the battery voltage measured during the charging period is measured with a higher voltage by the voltage drop of the internal impedance, and the battery voltage measured during the discharging period is measured with the voltage lower by the voltage drop of the internal impedance. It indicates that The charge / discharge control cycle tc described above corresponds to a case where the charge or discharge period is further divided into minute times. That is, in the minute charge / discharge control cycle tc (for example, 0.1 ms), the internal impedance shows inductive characteristics, and in the time in minutes as shown in FIG. 10, the impedance becomes resistive. .
[0077]
In FIG. 9, it has been described that the voltage measurement accuracy is increased by the filtering effect in the charge / discharge control cycle tc. However, in order to remove the influence of the resistive impedance over a long time as shown in FIG. The current detection circuit 801 measures the absolute value of the current I, transmits this current value to the MCU, calculates the product of the absolute value of the current I and the internal resistance of the battery in which data is stored in advance, and then obtains the voltage transmitted from the MUX. It is desirable to subtract or add to the information.
[0078]
FIG. 11 shows a control flow relating to the correction of the internal resistance and the correction of the temperature effect for the charge / discharge characteristics of FIG. The temperature detection circuit 802 shown in the embodiment of FIG. 8 is provided for measuring the temperature used in this control flow.
[0079]
In FIG. 11, first, a current flowing through the unit battery array 102 is detected by the current detection circuit 801. Next, it is determined from the detected polarity and absolute value of the current whether any of the idle period, the charging period, and the discharging period in FIG. Here, in the case of the suspension period, the voltage information of the battery 101 transmitted from the MUX to the MCU is used as it is. Next, in the case of the charging period or the discharging period, as described above, the product of the absolute value of the current I and the internal resistance of the battery in which data has been stored in advance is obtained, and then subtracted from the voltage information transmitted from the MUX. Or add. Here, the above processing is referred to as pause, charging, and discharging pattern processing.
[0080]
Next, the ambient temperature of the unit capacitor is measured by the temperature detecting circuit 802, and the influence of the internal resistance, the characteristic change due to the temperature, and the like are corrected in the voltage correction operation by adding or subtracting the voltage information of the unit capacitor. I do. This control flow is repeatedly performed in each cycle of charge, pause, discharge, and pause shown in FIG.
[0081]
FIG. 12 is a diagram showing a twelfth embodiment of the present invention. In the figure, 1201 is a commercial power supply, 1202 is a photovoltaic power generator, 1203 is a load device, 1204 is a control converter, and 1205 is a switch.
[0082]
A plurality of power storage devices 101 are connected in series, A / D converters 601 are connected to both ends of the power storage device 101, and their outputs are connected to a low withstand voltage circuit 106 via a digital level shift 602. In addition, a control converter is provided at both ends of the unit capacitor row 102.
1204 is connected, the MCU in the low withstand voltage circuit 106 and the control converter 1204 are connected.
The MCUs are interconnected.
[0083]
Further, the photovoltaic power generator 1202, the load device 1203, and the control converter 1204 are connected to a common commercial power supply 1201 via a switch 1205, respectively. At the same time, the photovoltaic power generation device 1202, the load device 1203, the control converter 1204, the switch 1205, and the low voltage circuit 106 are connected by a bidirectional signal system.
[0084]
The solar power generation device 1202 is a device that converts sunlight into DC power using a solar cell and outputs AC power using an inverter device.
[0085]
The load device 1203 is a home appliance such as an air conditioner, a refrigerator, a microwave oven, and lighting, and an electric device such as a motor, a computer, and a medical device. The control converter 1204 is a charge / discharge device that converts AC power into DC power or converts DC power into AC power. Further, it also functions as a controller for controlling these charge / discharge controls and devices such as the above-described solar power generation device 1202 and load device 1203.
[0086]
Here, these devices may include a switch 1205 in the device. Further, the power storage device of the present invention can take a connection form of a control converter 1204 other than the illustrated configuration and other devices.
[0087]
According to this configuration, when the electric power required by the load device 1203 cannot be covered by the commercial power supply 1201 or the photovoltaic power generation device 1202, the electric storage device is controlled via the control converter 1204.
Power is supplied from 101. Then, when the power supply from the commercial power supply 1201 or the solar power generation device 1202 is excessive, the power is stored in the power storage device 101 via the control converter 1204.
[0088]
In these operations, when the voltage between the terminals of the battery 101 reaches the discharge stop or charge stop level, the low withstand voltage circuit 106 sends the signal to the control converter 1204, and the control converter 1204 controls charging and discharging. .
[0089]
In these configurations, the contract power and power consumption of the commercial power supply 1201 and the power generation rating of the photovoltaic power generator 102 can be reduced, so that equipment costs and running costs can be reduced.
[0090]
In addition, when the power consumption is concentrated in a certain time zone, power is supplied from the power storage device 101 to the commercial power supply 1201, and when the power consumption is low, the power is stored in the power storage device. Electric power can be leveled.
[0091]
Furthermore, since the control converter 1204 monitors the power consumption of the load device 1203 and controls the load device 1203, energy saving and effective use of power can be achieved.
[0092]
FIG. 14 shows a thirteenth embodiment of the present invention. In a unit battery array 102 in which four capacitors are connected in series, the positive and negative electrodes of each battery 101 are provided with switch elements S1A to SD, respectively. Here, each of the terminals other than the highest plus terminal 103 and the lowest minus terminal 104 is provided with two switch elements arranged in parallel. The output terminal of each switch means connects resistors R1 to R8, and each resistor is connected to a resistor R9 or R10 connected to a reference potential. Here, the voltages of the capacitors 101 connected from the lowermost negative terminal 104 to the higher order are defined as V1, V2, V3, and V4 in this order.
[0093]
With such a configuration, for example, when the switch means S2A and S2B are turned on and the remaining switch elements are selected to be in the OFF state, the (+) input potential VP of the differential amplifier 1401 as the voltage detection circuit becomes (V1 + V2). Is divided by R4 and R10, and the (-) input potential VN is a voltage obtained by dividing the voltage of V1 by R3 and R9.
[0094]
As described above, the switch means S1A to S2D function as a multiplexer for commonly using the differential amplifier 1401 for the plurality of capacitors 101. However, most of the multiplexer (MUX) described above has the same low withstand voltage as the microcomputer (MCU), but the S2D of this embodiment is a high withstand voltage element having a withstand voltage higher than the voltage (V1 + V2 + V3 + V4) of the unit capacitor array 102. is there. For example, when S2D is ON and S2A is OFF, a reverse breakdown voltage of (V2 + V3 + V4) is applied to S2A. Therefore, S1A to S2D are desirably switch elements that allow a high reverse voltage.
[0095]
Next, a control method for selectively turning on the switch elements S1A to S2D will be described.
[0096]
When measuring an arbitrary capacitor voltage, for example, V4, connected in series as in the present embodiment, the negative potential (V1 + V2 + V3) of the capacitor to be measured becomes the common mode voltage for the differential amplifier 1401 from the lowest negative potential.
[0097]
The effect of this voltage on the accuracy of the differential amplifier 1401 is described in IEICE Transactions (C-II Vol. J74-C-II, No. 1, pp 1-10, 1991). The common mode sampling feedback method is introduced as a method of removing.
[0098]
This embodiment is characterized in that the common mode sampling feedback method introduced in this paper is applied to battery control. That is, a parallel switch element S3 is provided at the input of the differential amplifier 1401, and an integrator 1402 is connected to the output side via a series switch element S4, and the output is negatively fed back to the OFF set adjustment terminal of the differential amplifier 1401. Configuration.
[0099]
The present embodiment is characterized in that the common mode sampling feedback method is combined with a high voltage multiplexer type voltage divider circuit of S1A to S2D.
[0100]
FIG. 15 shows the order in which the switch elements are turned on. ON switching of each switch element is controlled according to a clock signal. Taking the case where the voltage of the lowest battery 101 having the voltage V1 is detected as an example, first, S1A is turned on for one clock period, and S3 and S4 are turned on at the same time. During this time, the other switch elements are in the OFF state. This period is a sample and hold period of the common mode voltage. That is,
With the input short-circuited by S3, only the common mode voltage (in this case, the reference potential) is input to the differential amplifier 1401. Further, since S4 is also ON, the OFF set voltage of the differential amplifier 1401 is negatively fed back via the integrator 1402 and works to make the OFF set voltage zero. During the period when the next clock becomes 0, S3 and S4 are turned off, and S1A and S2A are turned on. As a result, the input voltage of V1 is amplified with the common mode voltage removed.
[0101]
FIG. 15 shows a method of selecting and detecting the voltage of V2 following V1 in the same order. The feature of this embodiment is that the sample hold period is performed prior to the multiplexer operation by S1A to S2D. The sample hold period for each capacitor is a kind of reset period for the differential amplifier 1401. By providing such a reset period, the voltage of each battery 101 can be accurately detected without being affected by OFF set, temperature drift, and the like.
[0102]
【The invention's effect】
As described above, according to the present invention, in a circuit in which a plurality of capacitors are connected in series, the number of circuits is small, the cost is small, the power consumption is low, the control accuracy, the noise margin is high, and the reliability is high. A control device can be realized.
[0103]
Therefore, the present invention is particularly useful for a storage device such as a lithium secondary battery or an electric double layer capacitor, a storage device in which a large number of storage devices are connected in series, an evaluation device for evaluating these, and a storage control device for these manufacturing devices.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram showing a second embodiment of the present invention.
FIG. 3 is a diagram showing a third embodiment of the present invention.
FIG. 4 is a diagram showing a fourth embodiment of the present invention.
FIG. 5 is a diagram showing a fifth embodiment of the present invention.
FIG. 6 is a diagram showing a sixth embodiment of the present invention.
FIG. 7 is a diagram showing a seventh embodiment of the present invention.
FIG. 8 is a diagram showing an eighth embodiment of the present invention.
FIG. 9 is a diagram showing a specific example regarding a MUX selection timing.
FIG. 10 is a diagram showing charge / discharge characteristics of a lithium secondary battery.
FIG. 11 is a diagram showing a flow of control relating to correction of internal resistance and correction of temperature effect for charge / discharge characteristics.
FIG. 12 is a diagram showing a twelfth embodiment of the present invention.
FIG. 13 is a diagram showing a conventional battery protection circuit.
FIG. 14 is a diagram showing a thirteenth embodiment of the present invention.
FIG. 15 is a diagram showing an order in which each switch element is turned on.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Battery, 102 ... Unit capacitor row, 103 ... Highest positive terminal, 104 ... Lowest negative terminal, 105 ... Basic withstand voltage circuit, 106 ... Low withstand voltage circuit, 107 ... Basic withstand voltage differential amplifier, 108 ... Low voltage source, 201 .. MUX, 301 level shift circuit, 302 power cutoff circuit, 401 constant voltage generation circuit, 501 unit unit, 502 high voltage differential amplifier, 601 A / D converter, 602, 701 digital level shift , 801: current detection circuit, 802, temperature detection circuit, 1201: commercial power supply, 1202, photovoltaic power generation device, 1203, load device, 1204, control converter, 1205, switcher, 1301, secondary battery, 1302, voltage Detection circuit, 1303: resistor, 1304: comparator, 1305: FET, 1401: differential amplifier, 1402: integrator.

Claims (2)

A plurality of capacitors are connected in series, comprising a unit battery array divided into a certain unit, a low withstand voltage circuit having a withstand voltage lower than the voltage of the unit battery array, and a constant voltage generating circuit for generating a constant voltage, Both ends of each of the capacitors are connected to the low withstand voltage circuit via the constant voltage generating circuit. A plurality of capacitors are connected in series, a unit battery column divided into a certain unit, an A / D converter, a digital level shift for converting a voltage level, and a low withstand voltage lower than the voltage of the unit battery column. A voltage withstand circuit, both ends of the battery being connected to an analog input of an A / D converter, and a digital output of the A / D converter being connected to the low withstand voltage circuit through the digital level shift. A battery control device characterized by the above-mentioned.

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