JP2004045884A - Apparatus and method for image processing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To variably set an operation frequency corresponding to the bandwidth of image data when the image data in signal format differing in bandwidth are processed into an image and to make power consumption less than when image processing etc., is evenly performed according to a clock signal of fixed operation frequency. <P>SOLUTION: An apparatus is equipped with a frame memory 8 which stores image data in signal format including specified resolution and bandwidth, an image format detecting circuit 5 which detects the signal format of the image data stored in the frame memory 8, computes the bandwidth of the image data, and outputs pieces N and M of operation frequency setting information, a clock generating circuit 6 which generates a clock signal of desired operation frequency from a reference clock signal CLK according to the pieces N and M of operation frequency setting information outputted by the detecting circuit 5, and a memory control part 7 which controls writing to and reading from the frame memory 8 according to the clock signal outputted from the generating circuit 6. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus and an image processing method suitable for being applied to a video display control device that handles image data of a signal format having a different image data bandwidth, a battery-driven portable display terminal device equipped with the video display control device, and the like. Things.
[0002]
More specifically, when processing image data in a signal format including a predetermined resolution and bandwidth, a signal detection unit that detects the signal format, calculates the bandwidth of the image data, and outputs operating frequency setting information is provided. When image data of a signal format having a different bandwidth is subjected to image processing by generating a clock signal having a desired operating frequency from a reference clock signal based on the operating frequency setting information, the bandwidth of the image data may be reduced. The corresponding operating frequency can be set variably, and wasteful power consumption can be reduced as compared with the case where image data with different bandwidths are uniformly processed based on a clock signal with a fixed operating frequency. It is.
[0003]
[Prior art]
In recent years, with the realization of high-density mounting of semiconductor integrated circuit devices and multi-functionality of information processing devices, not only the AC drive power supply system but also battery-driven portable devices such as mobile phones, portable game machines, and portable computers. Display terminal devices are also often used.
[0004]
In these portable display terminal devices, information processing devices, and the like, digital image data in various signal formats is often handled due to the development of information media. As the signal format, 480i / 480p / 720p / 1080i, which is an image data format for BS digital broadcasting, one QVGA (320 pixels × 240 pixels / 60 fps) which is a streaming image data format transmitted via the Internet, It is diversified as seen in image data formats such as CIF (352 pixels × 288 pixels) and QCIF format (176 pixels × 144 pixels / 10 fps).
[0005]
A video display control IC chip (hereinafter, referred to as a video processor) for processing image data of a plurality of image data formats is manufactured, and this IC chip is mounted on a portable display terminal device, an information processing device, or the like. Done. In this type of video processor, a frame memory for holding the image data is usually mounted in the video processor in order to handle image data of signal formats of various resolutions and frame rates. The video processor reads image data from the frame memory and performs image quality adjustment processing such as resolution conversion, frame rate conversion, brightness, contrast, gamma, and sharpness (capture processing).
[0006]
[Problems to be solved by the invention]
By the way, according to the conventional video processor, there are the following problems when performing the capture processing of the image data stored in the frame memory.
[0007]
{Circle around (1)} The operating frequency (speed) of the memory clock signal at the time of memory access is set to a clock speed capable of processing image data of a signal format having the largest amount of information among the corresponding image formats. Moreover, the clock speed is fixed.
[0008]
Therefore, even when a display format in which a sub-screen is displayed on the main screen or when image data in a low-resolution, low-frame-rate signal format is input, the extra memory clock speed is fixed. Consumes power.
[0009]
{Circle around (2)} When the video processor is applied to a battery-driven portable display terminal or the like, image data of a signal format having a different bandwidth is uniformly processed based on a clock signal having a fixed operating frequency. It consumes faster and requires more frequent charging.
[0010]
Therefore, the present invention has solved such a conventional problem, and when performing image processing on image data of a signal format having a different bandwidth, it is possible to variably set an operating frequency corresponding to the bandwidth of the image data. It is another object of the present invention to provide an image processing apparatus and an image processing method capable of reducing unnecessary power consumption as compared with a case where image processing is uniformly performed based on a clock signal having a fixed operating frequency.
[0011]
[Means for Solving the Problems]
The object described above is an apparatus for processing image data in a signal format including a predetermined resolution and a bandwidth, wherein the storage means for storing the image data, and the signal format of the image data stored in the storage means are detected. Signal calculating means for calculating the bandwidth of the image data and outputting operating frequency setting information, and signal generation for generating a clock signal of a desired operating frequency from a reference clock signal based on the operating frequency setting information by the signal detecting means. The image processing apparatus is provided with means for controlling writing and reading of the storage means based on a clock signal output from the signal generation means.
[0012]
According to the image processing apparatus of the present invention, when processing image data of a signal format including a predetermined resolution and bandwidth, the signal detection unit detects the signal format of the image data stored in the storage unit, and The bandwidth of the image data is calculated, and the operating frequency setting information is output to the signal generator. The signal generating means generates a clock signal having a desired operating frequency from the reference clock signal based on the operating frequency setting information from the signal detecting means. On the premise of this, the control means performs write / read control of the storage means based on the clock signal output from the signal generation means.
[0013]
Therefore, when image data of a signal format having a different bandwidth is to be written to and read from the memory, the operating frequency corresponding to the bandwidth of the image data can be variably set to the signal generating means, so that the bandwidth is reduced. The operating frequency of the clock signal for writing and reading the image data with a narrow bandwidth into the memory can be set lower than the operating frequency of the clock signal for writing and reading the widest image data in the memory.
[0014]
As a result, as compared with the case where image data having different bandwidths are uniformly written to and read from the memory based on a clock signal having a fixed operating frequency, image data with a narrow bandwidth can be written and read using a clock signal having a low operating frequency. Therefore, wasteful power consumption can be omitted.
[0015]
An image processing method according to the present invention is a method for processing image data in a signal format including a predetermined resolution and bandwidth, and operates by detecting a signal format of image data and calculating a bandwidth of the image data. Obtaining frequency setting information, generating a clock signal of a desired operating frequency from a reference clock signal based on the obtained operating frequency setting information, and performing memory write / read control based on the generated clock signal. It is characterized by the following.
[0016]
According to the image processing method of the present invention, when processing image data of a signal format including a predetermined resolution and bandwidth, when performing image processing of writing and reading image data of a signal format having a different bandwidth from a memory, etc. Since the operating frequency corresponding to the bandwidth of the image data can be variably set, the image data having the narrower bandwidth than the operating frequency of the clock signal for writing and reading the image data having the widest bandwidth is stored in the memory. The operating frequency of the clock signal for writing and reading can be set low.
[0017]
Therefore, compared to the case where image data having different bandwidths are uniformly written to and read from the memory based on a clock signal having a fixed operating frequency, image data having a narrow bandwidth is written and read using a clock signal having a low operating frequency. Therefore, unnecessary power consumption can be omitted.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of an image processing apparatus and an image processing method according to the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration example of a video display control device 100 to which an image processing device as an embodiment according to the present invention is applied.
In this embodiment, when processing image data in a signal format including a predetermined resolution and a bandwidth, a signal detection unit that detects the signal format, calculates the bandwidth of the image data, and outputs operating frequency setting information. When generating a clock signal having a desired operating frequency from a reference clock signal based on the operating frequency setting information, and performing image writing / reading processing on image data of a signal format having a different bandwidth in a memory, the image is output. The operating frequency corresponding to the data bandwidth can be variably set, and wasteful power consumption compared to the case where image data having different bandwidths are uniformly written to and read from memory based on a clock signal having a fixed operating frequency. Can be reduced.
[0019]
The video display control device 100 shown in FIG. 1 is an example of an image processing device, and is a device that processes digital image data of a signal format including a predetermined resolution and a bandwidth (hereinafter, also simply referred to as image data). The video display control device 100 also handles image data of a signal format having a different bandwidth. As an application example of the video display control device 100, the video display control device 100 is mounted on a battery-driven portable display terminal device or the like. Of course, the present invention is not limited to this, and may be applied to the video display control device 100 for driving AC power.
[0020]
The video display control device 100 includes an input buffer 1, an image format detection circuit 5, a clock generation circuit 6, a memory control unit 7, a frame memory 8, a video processor unit 9, and a video display unit 10. For example, a display clock signal (hereinafter simply referred to as a pixel clock Cp), a horizontal synchronizing signal SH, and a vertical synchronizing signal SV are input to the video display control device 100 from a not-shown MPEG decoder together with digital image data as a component signal.
[0021]
In the video display control device 100, in addition to the component signals output from the MPEG decoder, digital image data of BS digital broadcast, image data such as QVGA (Qua Video Video Array) size from a server connected to the Internet, not shown. Image data such as CIF (Common Intermediate Format) and QCIF (Quarter Common Intermediate Format) sizes supplied from the camera module can also be handled. Image data such as QVGA size is supplied from a server that provides a streaming image data transmission service, and is input via a memory bus of a CPU (not shown).
[0022]
The image data DIN and the pixel clock Cp are input to the input buffer 1, and the image data DIN is temporarily held based on the pixel clock Cp when the image data DIN is written to the frame memory 8. For example, when the image data DIN is written into the frame memory 8, the memory bus between the frame memory 8 and the memory control unit 7 is connected to the OSD data (not shown) used in the video processor When the data is occupied by data such as module control parameters, the input buffer 1 is used to temporarily hold image data.
[0023]
The pixel clock Cp input to the input buffer 1 is supplied to the image format detection circuit 5 together with the horizontal synchronization signal SH and the vertical synchronization signal SV. The image format detection circuit 5 is an example of a signal detection unit. The detection circuit 5 includes a horizontal counter 2, a vertical counter 3, and a bandwidth calculation circuit 4.
[0024]
The horizontal counter 2 is an example of a first counter circuit, and receives a horizontal synchronization signal SH from an MPEG decoder or the like and measures the number of signal edge changes (the number of active transitions). The horizontal counter 2 outputs the counter value to the bandwidth calculation circuit 4.
[0025]
The vertical counter 3 is a second counter circuit, and similarly receives a vertical synchronization signal SV from an MPEG decoder or the like and measures the number of signal edge changes (the number of active transitions). The vertical counter 3 outputs the counter value to the bandwidth calculation circuit 4.
[0026]
The bandwidth operation circuit 4 is an example of an operation circuit, and detects an information amount and a bandwidth (frame rate) of one frame of the image data DIN based on the pixel clock Cp and counter values obtained from the horizontal and vertical counters 2 and 3. Then, the operating frequency setting information N, M is calculated and output. The operating frequency setting information N, M contains the frequency division ratio for dividing the frequency of the clock signal of the reference frequency Fs (hereinafter referred to as the reference clock signal CLK).
[0027]
As described above, the image format detection circuit 5 detects the signal format of the image data DIN stored in the frame memory 8, calculates the bandwidth of the image data DIN, and sends the operating frequency setting information N and M to the clock generation circuit 6. Output.
[0028]
The image format detection circuit 5 is connected to a clock generation circuit 6 which is an example of a signal generation means. Based on the operation frequency setting information N and M by the detection circuit 5, a desired operation frequency of the reference clock signal CLK is obtained. A clock signal is generated. For example, the clock generation circuit 6 generates a memory clock signal φm used by the memory control unit 7 and a display clock signal φv used by the video processor unit 9 from the reference clock signal CLK. The reference clock signal CLK is input from outside.
[0029]
The clock signal φm allows the memory control unit 7 and the frame memory 8 to operate at the optimized operating frequency, and the clock signal φp allows the video processor unit 9 to operate at the optimized operating frequency. The video display unit 10 can be operated at the optimized operation frequency by the signal φv, and the power consumption can be reduced. The clock generation circuit 6 is connected to a memory control unit 7 which is an example of a control unit, and controls the writing and reading of the frame memory 8 based on the memory clock signal φm output from the generation circuit 6. You.
[0030]
The memory control unit 7 is connected to a frame memory 8 as an example of a storage unit, and stores digital image data DIN. The frame memory 8 stores OSD data, video processor control parameters, and the like in addition to the image data DIN. A RAM or the like is used for the frame memory 8. An output buffer 11 is connected to the frame memory 8 so that the image data DIN is temporarily stored when the image data DIN is read from the frame memory 8.
[0031]
The memory control unit 7 executes the timing control when writing the image data DIN from the input buffer 1 to the frame memory 8 and the timing control when reading the image data DIN from the frame memory 8 to the output buffer 11. Done. For example, the memory controller 7 controls writing of the image data DIN between the input buffer 1 and the frame memory 8, and controls reading of the image data DIN between the frame memory 8 and the video processor 9 through the output buffer 11. do.
[0032]
A video processor unit 9 is connected to the memory control unit 7. For example, resolution conversion, frame rate conversion, brightness, contrast, and the like are performed on image data DIN input from the frame memory 8 via the memory control unit 7. , Gamma, sharpness, and other image quality adjustments.
[0033]
A video display unit 10 is connected to the video processor unit 9, receives the image data DIN processed by the video processor unit 9, and outputs the image data DIN based on the display clock signal φv. The display clock signal φv is supplied from the clock generation circuit 6.
[0034]
FIG. 2 is a block diagram illustrating a configuration example of the clock generation circuit 6. The clock generation circuit 6 shown in FIG. 2 includes, for example, three PLL (Phase-Locked Loop) synthesizer blocks # 1 to # 3. The PLL synthesizer block # 1 generates a memory clock signal φm having a desired operation frequency from the reference clock signal CLK based on the reference clock signal CLK and the operation frequency setting information N and M.
[0035]
The PLL synthesizer block # 2 generates a display clock signal φv having a desired operation frequency based on the reference clock signal CLK and the operation frequency setting information N and M. The PLL synthesizer block # 3 generates a processor clock signal φp having a desired operating frequency based on the reference clock signal CLK and the operating frequency setting information N and M.
[0036]
FIG. 3 is a block diagram showing an example of the internal configuration of the PLL synthesizer block # 1 and the like. A PLL synthesizer block # 1 shown in FIG. 3 includes a frequency divider (1 / N) 21, a phase comparator 22, a loop filter 23, a VCO (Voltage Control Oscillator) 24, and a frequency divider (1 / M). 25.
[0037]
The frequency divider 21 divides the frequency of the reference clock signal CLK of the reference frequency Fs by 1 / N based on the operating frequency setting information N supplied from the image format detection circuit 5 to generate a frequency-divided output signal S21 of the frequency Fs / N. And outputs it to the phase comparator 22.
[0038]
On the other hand, the frequency divider 25 divides the frequency Fo output from the VCO 24, for example, the memory clock signal φm to 1 / M based on the operating frequency setting information M supplied from the image format detection circuit 5, and divides the frequency Fo / An M-divided output signal S25 is generated and output to the phase comparator 22.
[0039]
The phase comparator 22 compares the frequency Fs / N of the frequency-divided output signal S21 output from the frequency divider 21 with the frequency Fo / M of the frequency-divided output signal S25 output from the frequency divider 25, and matches the phases. .
Fs / N = Fo / M (1)
Equations (1) and (2) in the phase comparator 22, that is,
Fo = (N / M) · Fs (2)
And the output of the phase comparator 22 is filtered by a loop filter. The output voltage after the filter processing is used in the VCO 24 for voltage control oscillation control, and the VCO 24 outputs a memory clock signal φm or the like having an operating frequency Fo.
[0040]
Subsequently, an operation example of the video display control device 100 regarding the image processing method according to the present invention will be described. FIG. 4 is a flowchart showing an operation example of the video display control device 100.
In the video display control device 100, it is assumed that image data DIN of a signal format including a predetermined resolution and a predetermined bandwidth is written to and read from a memory. In this case, the operating frequency setting information N, M is obtained by detecting the signal format of the image data DIN and calculating the bandwidth of the image data DIN, and based on the operating frequency setting information N, M obtained here. A case where a clock signal having a desired operating frequency is generated from the reference clock signal CLK and memory write / read control is performed based on the generated clock signal will be described as an example.
[0041]
Under these operating conditions, the video display control device 100 receives, for example, a pixel clock Cp, a horizontal synchronizing signal SH, and a vertical synchronizing signal SV together with digital image data DIN as a component signal from an MPEG decoder (not shown). The pixel clock Cp is supplied to the image format detection circuit 5 together with the horizontal synchronization signal SH and the vertical synchronization signal SV.
[0042]
Then, in step A1 of the flowchart shown in FIG. 4, the image format detection circuit 5 detects the signal format of the image data DIN stored in the frame memory 8. At this time, the image data DIN and the pixel clock Cp are input to the input buffer 1, and the image data DIN is temporarily held based on the pixel clock Cp when the image data DIN is written into the frame memory 8.
[0043]
Then, in step A2, the bandwidth of the image data DIN is calculated, and the operating frequency setting information N, M is output to the clock generation circuit 6. At this time, the horizontal counter 2 measures the number of signal edge changes of the horizontal synchronization signal SH, and outputs the counter value of the horizontal counter 2 to the bandwidth calculation circuit 4. The vertical counter 3 measures the number of signal edge changes of the vertical synchronization signal SV, and outputs the counter value of the vertical counter 3 to the bandwidth calculation circuit 4.
[0044]
The bandwidth calculation circuit 4 detects the information amount and the bandwidth (frame rate) of one frame of the image data DIN based on the pixel clock Cp and the counter values obtained from the horizontal and vertical counters 2 and 3, and sets the operating frequency setting information N , M are calculated. The operating frequency setting information N, M contains the frequency division ratio for dividing the frequency of the reference clock signal. The operating frequency setting information N and M are output to the clock generation circuit 6.
[0045]
Then, in step A3, the clock generation circuit 6 generates a clock signal having a desired operation frequency from the reference clock signal CLK based on the operation frequency setting information N and M from the image format detection circuit 5. For example, the PLL synthesizer block # 1 of the clock generation circuit 6 generates a memory clock signal φm having a desired operation frequency Fo from the reference clock signal CLK based on the reference clock signal CLK and the operation frequency setting information N and M. .
[0046]
In addition, the PLL synthesizer block # 2 generates a display clock signal φv having a desired operation frequency Fo ′ based on the reference clock signal CLK and the operation frequency setting information N and M. The PLL synthesizer block # 3 generates a processor clock signal φp having a desired operating frequency Fo ″ based on the reference clock signal CLK and the operating frequency setting information N and M.
[0047]
Thereafter, in step A4, a process of capturing image data is executed. At this time, when writing the image data DIN from the input buffer 1 to the frame memory 8, the memory control unit 7 executes the timing control based on the memory clock signal φm (write control). By this timing control, digital image data DIN is stored in the frame memory 8.
[0048]
When reading the image data DIN from the frame memory 8 to the output buffer 11, the memory control unit 7 executes timing control based on the memory clock signal φm. By this timing control, the image data DIN is read out to the video processor 9.
[0049]
The video processor unit 9 converts the image data DIN input from the frame memory 8 via the memory control unit 7 based on, for example, a processor clock signal φp, resolution conversion, frame rate conversion, brightness, contrast, gamma, and sharpness. And other processes such as image quality adjustment.
[0050]
The video display unit 10 receives the image data DIN processed by the video processor unit 9 and outputs the image data DOUT based on the display clock signal φv. The image data DOUT is output to, for example, a liquid crystal display device.
[0051]
Then, it is detected in step A5 whether the signal format of the image data DIN has been changed. In the video display control device 100, in addition to the component signals output from the MPEG decoder, digital image data of BS digital broadcasting, image data such as QVGA size from a server connected to the Internet, and a camera module (not shown) are supplied. Image data such as CIF and QCIF sizes can also be handled. The image data such as the QVGA size is supplied from a server that provides a streaming image data transmission service, and is input via a memory bus of a CPU (not shown).
[0052]
Therefore, when the signal format is changed, the process returns to step A1. If the signal format is not changed, the process goes to step A6 to determine the end. The judgment at this time is the user. When ending the video display control processing, the above-described image processing is ended. If the image processing is not terminated, the process returns to step A1 to continue the video display control processing.
[0053]
[Example]
Here, a case where the input of image data is switched from the 480p BS digital broadcast signal format to QVGA size 10 fps streaming data is taken as an example.
[0054]
(1) 480p BS digital broadcasting signal format
In this case, when the 480p image data, the horizontal synchronization signal SH, the vertical synchronization signal SV, and the pixel clock Cp are input to the video display control device 100 in step A1 shown in FIG. 4, the signal format of the image data is changed to the horizontal counter. 2, an image format detection circuit 5 having a vertical counter 3 and a bandwidth calculation circuit 4.
[0055]
In the image format detection circuit 5, every time the count value of the horizontal counter 2 is incremented in step A2, the pixel clock Cp is counted by 858. Each time the count value of the vertical counter 3 is incremented, the horizontal counter 2 is counted up 525 times. “525” is a count value indicating the number of lines in the horizontal direction. The frame rate is calculated by measuring the period in which the vertical counter 3 is incremented.
[0056]
With this 480p BS digital broadcast signal format, the frame rate is 60 frames / sec (hereinafter referred to as fps). From these calculation results, the image format detection circuit 5 sets an optimal memory clock signal φm generated by the clock generation circuit 6. In this example, since 480p is detected by the image format detection circuit 5, the image data bandwidth is 858 (pixels) × 525 (lines) × 16 (YUV data; YUV [4: 2: 2]) × 60. (Fps) = 432.432 Mbit / s.
[0057]
When reading image data from the frame memory 8 to the memory control unit 7, it is necessary to occupy the same amount of image data. Become. In this example, when a burst access mode with a 32-bit width (a mode in which data can be transferred once per clock) is used, the required operating frequency Fo of the memory clock signal is 864.864M ÷ 32 = 27.027 MHz.
[0058]
The image format detection circuit 5 outputs such operating frequency information setting information N, M to the clock generation circuit 6. The clock generation circuit 6 receives the operating frequency setting information N and M from the image format detection circuit 5 and sets the number of clocks obtained by adding the memory clock signal φm to a bandwidth (frame rate) required for other data transfer such as OSD data. I do.
[0059]
For example, if image data bandwidth of 640 Mbit / s is required for transfer of OSD (On Screen Display) data or the like, 640 M ÷ 32 = 20 MHz is added. That is, in the clock generation circuit 6, the PLL synthesizer block # 1 and the like shown in FIG. 3 are voltage-controlled and oscillated so as to output the memory clock signal φm such that the operation frequency Fo becomes 27M + 20M = 47 MHz. The memory clock signal φm of Fo is generated.
[0060]
{Circle around (2)} When the input signal format of the image data DIN is switched to streaming data of QVGA size 10 fps
In this case, similarly to the signal format for 480p BS digital broadcasting, the image format detection circuit 5 calculates the information amount of the image data by calculation, and then detects the signal format of the image data. In this example, since streaming data having a QVGA size of 10 fps is detected by the image format detection circuit 5, the image data bandwidth is 320 (pixels) × 240 (pixels) × 16 (RGB565; R color = 5 bits, G color = 6 bits, B color = 5 bits) x 10 (fps) = 12.288 Mbit / s.
[0061]
The image data bandwidth required by the video display control device 100 is 12.288 M × 2 = 24.576 Mbit / s, and if the same memory access condition as that of the signal format 480p is used, the memory bus occupancy is 24.576 M Since ÷ 32 = 0.768 MHz, the operating frequency Fo of the memory clock signal φm is 20M + 0.768M = 20.768 MHz.
[0062]
In this example, the operating frequency Fo of the memory clock signal φm can be appropriately reduced depending on the signal format of the image data. As a result, the power consumption of the video display control device 100 to which the method of the present invention is applied can be significantly reduced as compared with the video display control device to which the conventional technique is applied.
[0063]
FIG. 5 is a table showing various signal formats of image data and examples of power consumption reduction. The table shown in FIG. 5 shows an image data bandwidth, an OSD data bandwidth, and a memory clock for five signal formats (hereinafter also referred to as input image formats) of image data input to the video display control device 100. A set value of the operating frequency Fo of the signal φm (hereinafter also referred to as a memory clock set value) and a power consumption ratio are shown.
[0064]
In this example, regarding the input image format, SVGA (Super Video Graphics Array; 800 × 600/60 fps), 480p (720 × 480/60 fps), VGA (640 × 480/60 fps), QVGA (320 × 240/60 fps), QCIF (176 × 144/10 fps), and all resolutions were assumed to be 16 Bit / pixel. The image data bandwidth is calculated according to the calculation example in the text, and is rounded up to the nearest decimal point. For example, in the case of SVGA, it is 800 × 600 × 60 × 2 = 921.6 Mbit / s.
[0065]
The OSD data bandwidth is uniformly set to 100 Mbit / s. Regarding the memory clock set value, the case where the memory bus is 32 bits is taken as an example, and the operating frequency Fo is
Fo = {(image data bandwidth + OSD data bandwidth) × 1.1} / 32
Determined by Note that the calculation was performed in consideration of 10% as an inaccessible time such as a fresh cycle of the frame memory 8. The power consumption ratio is a ratio when the power consumption in SVGA is 100%.
[0066]
According to this table, the image data signal format is SVGA, the image data bandwidth is 922 Mbit / s, the OSD data bandwidth is 100 Mbit / s, the operating frequency Fo of the memory clock signal φm is 36 MHz, and the power consumption is Assuming that the ratio is 100%, in the signal format 480p, the image data bandwidth is 644 Mbit / s, the OSD data bandwidth is 100 Mbit / s, the operating frequency Fo of the memory clock signal φm is 27 MHz, and the power consumption ratio is Reduced to 75%.
[0067]
In the signal format VGA of image data, the image data bandwidth is 590 Mbit / s, the OSD data bandwidth is 100 Mbit / s, the operating frequency Fo of the memory clock signal φm is 24 MHz, and the power consumption ratio is 67%. Reduced.
[0068]
Furthermore, in the image data signal format QVGA, the image data bandwidth is 148 Mbit / s, the OSD data bandwidth is 100 Mbit / s, the operating frequency Fo of the memory clock signal φm is 9 MHz, and the power consumption ratio is 25%. To be reduced. Further, in the signal format QCIF of the image data, the image data bandwidth is 9 Mbit / s, the OSD data bandwidth is 100 Mbit / s, the operating frequency Fo of the memory clock signal φm is 4 MHz, and the power consumption ratio is 12%. Reduced.
[0069]
As described above, according to the video display control device 100 according to the embodiment of the present invention, the signal format of the image data DIN stored in the frame memory 8 is detected, and the image data bandwidth of the image data DIN is calculated. An image format detection circuit 5 that outputs operating frequency setting information N and M is provided, and a clock generation circuit is provided for performing image data DIN of a signal format having a different image data bandwidth as shown in FIG. 6, the operating frequency Fo corresponding to the bandwidth of the image data DIN can be variably set.
[0070]
Therefore, it is possible to set the operating frequency of the clock signal for writing and reading the image data DIN having a narrow bandwidth in the memory lower than the operating frequency of the clock signal for writing and reading the image data DIN having the widest image data bandwidth in the memory. it can. As a result, the image data DIN having a narrower image data bandwidth has a lower operating frequency Fo compared to a case where image data DIN having different image data bandwidths are uniformly written to and read from a memory based on a clock signal having a fixed operating frequency. Since the memory write / read processing can be performed by the clock signal, unnecessary power consumption can be reduced.
[0071]
When the video display control device 100 of the present invention is mounted on a battery-driven information processing device such as a mobile phone or a portable game machine, the continuous operation time that can be used in one charge is reduced by the conventional battery-driven information processing. It can be longer than the equipment. Further, in a graphic chip in which a semiconductor chip for display is formed at a high density in a battery-driven portable display terminal device or the like, excess power consumption can be suppressed, so that heat generation of the device body can be suppressed.
[0072]
【The invention's effect】
As described above, according to the image processing apparatus and the image processing method of the present invention, when processing image data of a signal format including a predetermined resolution and a bandwidth, the signal format of the image data is detected. Signal detecting means for calculating the bandwidth of the image data and outputting operating frequency setting information, wherein the signal generating means generates a clock signal of a desired operating frequency from a reference clock signal based on the operating frequency setting information. Done.
[0073]
With this configuration, when image processing is performed on image data of a signal format having a different bandwidth, the operating frequency corresponding to the bandwidth of the image data can be variably set to the signal generation unit. The operating frequency of the clock signal for performing image processing on image data having a narrow bandwidth can be set lower than the operating frequency of the clock signal for performing image processing on wide image data.
[0074]
Therefore, compared to the case where image data having different bandwidths are uniformly written to and read from the memory based on a clock signal having a fixed operating frequency, image data having a narrow bandwidth is written and read using a clock signal having a low operating frequency. Therefore, unnecessary power consumption can be omitted.
[0075]
INDUSTRIAL APPLICABILITY The present invention is very suitable when applied to a video display control device that handles image data of a signal format having a different image data bandwidth, a battery-driven portable display device equipped with the video display control device, and the like.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a video display control device 100 to which an image processing device as an embodiment according to the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration example of a clock generation circuit 6.
FIG. 3 is a block diagram showing an example of an internal configuration of a PLL synthesizer block # 1 and the like.
4 is a flowchart illustrating an operation example of the video display control device 100. FIG.
FIG. 5 is a table showing various signal formats of image data and an example of power consumption reduction.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Input buffer, 2 ... Horizontal counter (1st counter), 3 ... Vertical counter (2nd counter), 4 ... Bandwidth operation circuit (Operation circuit), 5 ... Image format detection circuit (signal detection means), 6 ... clock generation circuit (signal generation means), 7 ... memory control unit (control means), 8 ... frame memory (storage means), 9 ... Video processor, 10: video display unit, 11: output buffer, # 1 to # 3: PLL synthesizer block, 100: video display control device

Claims (5)

An apparatus for processing image data in a signal format including a predetermined resolution and bandwidth,
Storage means for storing the image data;
A signal detection unit that detects a signal format of image data stored in the storage unit, calculates a bandwidth of the image data, and outputs operating frequency setting information;
Signal generating means for generating a clock signal of a desired operating frequency from a reference clock signal based on operating frequency setting information by the signal detecting means,
An image processing apparatus comprising: a control unit that controls writing and reading of the storage unit based on a clock signal output from the signal generation unit. A display clock signal, a horizontal synchronization signal and a vertical synchronization signal are input together with the image data,
The signal detection means,
A first counter circuit that inputs the horizontal synchronization signal and measures the number of signal edge changes;
A second counter circuit that receives the vertical synchronization signal and measures the number of signal edge changes;
An arithmetic circuit for detecting the information amount and bandwidth of one frame of the image data based on the display clock signal and the counter value obtained from the first and second counter circuits, and calculating and outputting operating frequency setting information; The image processing apparatus according to claim 1, further comprising: An input buffer for temporarily holding image data to be written to the storage unit,
An output buffer for temporarily holding image data read from the storage means,
The control means includes:
Timing control for writing image data from the input buffer to the storage means;
2. The image processing apparatus according to claim 1, wherein timing control for reading image data from said storage means to an output buffer is performed. A method of processing image data of a signal format including a predetermined resolution and a bandwidth,
The operating frequency setting information is obtained by detecting the signal format of the image data and calculating the bandwidth of the image data,
Generating a clock signal of a desired operating frequency from the reference clock signal based on the obtained operating frequency setting information;
An image processing method, wherein memory write / read control is performed based on the generated clock signal. A display clock signal, a horizontal synchronization signal and a vertical synchronization signal are input together with the image data,
While measuring the number of signal edge changes of the horizontal synchronization signal, measuring the number of signal edge changes of the vertical synchronization signal,
The operating frequency is set by detecting the information amount and bandwidth of one frame of the image data based on the display clock signal and the measured number of signal edge changes of the horizontal synchronization signal and the measured number of signal edge changes of the vertical synchronization signal. The image processing method according to claim 4, wherein information is generated.

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