JP2003500709A - Packet classification state machine - Google Patents

Abstract

SUMMARY A method is disclosed for reprogramming classification data in a packet classification state machine without interrupting operation of the state machine. Data associated with a plurality of new nodes from the start node of the classification tree in the classification tree is stored, so that subsequent nodes in the existing data structure are pinpointed. After this data is stored, a new first node address is stored at a predetermined location. Thereby, the execution of the subsequent state machine starts at the new node. Preferably, the new first node address is stored using an atomic operation such that reading of the first node address during a store operation is not enabled. This method allows the simultaneous use of the same classified data memory by multiple state machines since it does not involve overwriting existing data.

Description

Detailed Description of the Invention

TECHNICAL FIELD The present invention relates to programmable state machines, and more particularly to programmable packet classification state machines for use in high speed communications.

BACKGROUND OF THE INVENTION In the past, programmable state machines have been provided with procedural oriented programming. This allows transitioning from one state to another under certain conditions according to the desired sequence. Since the state machine effectively controls the sequence of processing steps, the concept of a truly non-procedural programming method for state machines seems to be incompatible with it. For this reason, many "non-procedural" methods for programming state machines have been proposed. Nevertheless, the analysis revealed that they were procedural, or rather procedural. In these methods, the concept of branch and loop is common, and the operation flowchart is often clear.

To date, nonprocedurally oriented methods of programming state machines have been considered to have little benefit due to the procedurally oriented nature of state machines. Some of the "non-procedural" methods of programming state machines focus on programming code reuse and code modularity. That is, not only is the procedural element within each state accepted, but in some sense it is considered essential. However, the different states are generally easily reused or organized into classification descriptions as a whole.

When programming a state machine, it is important to consider the concept of a truly non-procedural oriented method for implementing a programmable state machine. Then, because the state machine description is non-procedural, changes are made to the state machine programming without considering the state flow. Furthermore, the implementation of the state machine is performed by the compiler, and, more importantly, the state machine designer, does not require significant design by the end user.

Reprogramming a state machine with procedural programming is considered a simple task. Pauses the state machine from execution, loads the new programming into program memory, and then restarts the state machine. The process of quiescing a state machine often entails stopping data flow, which is undesirable. For use in firewalls or other security applications, changes in programming often result from changes in security procedures. Therefore, it is important that changes are loaded as quickly as possible. Of course, as would be apparent to one of ordinary skill in the art, shutting down the system during reprogramming is often impractical, and thus system reprogramming is rarely performed at specific times. Absent. This lacks convenience.

Another problem arises with current reprogramming techniques for programmable state machines when multiple state machines share a common program memory. When doing a programming upgrade on any state machine, all state machines are quiesced. This is an important problem, but it can be avoided by using a duplicate program memory that ensures the operation of all but the state machine during the reprogramming operation. Another way to avoid this problem is to provide each state machine with its own dedicated state machine memory.

The current field of research in fast state machine design is that of digital communications. Generally, in a digital communication network, data is a packet,
Grouped into cells, frames, buffers, etc. Packets, cells, etc. contain data and classification information. Classification of packets, cells, etc. is important for routing and proper response in data communication. In one approach to classifying this type of data, a state machine is used.

[0008]   Addressing and routing for Gigabit Ethernet State machine to determine the protocol-related information, including the routing information. It is essential to operate at high speed to process data. Unfortunately, this is At very high speeds, memory access can be a state machine or other Type real-time data processor implementation of non-negligible bottleneck It becomes ku. Inspired by this, researchers are pioneers in improving classification performance. Seeking a solution. The obvious solution is the classification state machine Is implemented as complete hardware. Non-programmable hardware Air condition machines have excellent performance and are therefore of the highest design. Data rate is known to have good compatibility; however, communication The implementation of the protocol is inherently quite flexible in its nature. Today's one Common protocols are obsolete within a few months. Therefore, Gigabit Ethernet It is preferable that the state machine used for programming be programmable. In the past For 10 megabits and 100 megabytes to accommodate programmability One solution for Bit's Ethernet data networks Required a large number of memory access instructions per state. this Would substantially limit the speed of operation of prior art state machines.

The programmable state machine for data classification can be implemented entirely in software. Of course, software state machines are often much slower than their hardware equivalents. In the software state machine, each operation is executed by a software instruction and the state change results in a branch operation. As will be apparent to those skilled in the art, implementations in software of fast state machines with respect to packet classification require a large number-often more than a billion-instructions per second-and expensive parallel processors. Or will require technology that is unknown at this time. In fact, the hard limit on performance is the speed of the memory device. For example, if a 7 nanosecond memory device is used, then for each bit of the Gigabit Ethernet stream, the memory access possible per memory device is:
Less than once. That is, if each byte of data-or 8 bits-is processed in a single state, only one memory access operation is allowed during each state. Implementing this type of system as a pure software solution is neither practical nor desirable.

Current state of the art integrated memory devices have achieved performance on the order of 7 nanoseconds per memory access, when considering timing and other factors. Therefore, for each 8-bit in the Ethernet data stream, if only one memory access is required, pure hardware of a fast state machine sufficient to implement the classification of Gigabit Ethernet packets. Fulfillment is possible. Prior art implementations of such state machines allow state transitions within a time frame of a predetermined number of bits using a branch algorithm. Address data for the branch algorithm is stored in program memory. Here, assuming that the predetermined number of bits is 8, each state transition occurs within 8 nanoseconds. One way to achieve this performance is to store a table of data with 256 entries for each possible state. The address of this table is then combined with the 8 bits from the data stream to determine the next state address. This is continued until the value indicating the classification or the value indicating the classification failure is reached.

Unfortunately, the amount of memory required to implement a system as described above is extremely large. For example, using 8 bits at a time would mean a maximum of 256 entries per table, and 65,5 if using 16 bits at a time.
36 entries are required. However, the exact number of tables depends on the number of terminal sites. Since integrated memory with high storage capacity cannot be used,
Implementation of prior art programmable packet classification state machines with multiple edges in integrated memory is not currently feasible.

It has been found that a programmable hardware state machine for use in packet classification of high speed data communication in which reprogramming of the state machine is performed according to a non-procedural approach has been found to be advantageous.

It would also be advantageous to provide a state machine programming method that allows for easy modification of state machine programming during the operation of multiple state machines that use the same program memory.

OBJECTS OF THE INVENTION To overcome the above and other limitations of the prior art, the present invention provides
One object is to provide a state machine architecture for simultaneously supporting multiple state machines.

Furthermore, the present invention requires no disruption of the operation of the state machine,
It is another object to provide a method for reprogramming the state machine program memory.

SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a method of programming a state machine memory that includes a plurality of storage locations including a storage location of a first state address, the method comprising: Providing data corresponding to each of the states including data corresponding to all states preceding each of the new states including one new first state; the data in program memory Storing the data associated with each new state at a state address for the new state and storing the data in an unoccupied storage location; Data related to the first state is moved to the new first state address. A step in which the data is stored in a storage location that is not occupied by programming of the current state machine; and after the data corresponding to each new state is stored, Replacing the data in the one state address location with a new first state address.

In another embodiment of the present invention, the programming of the state machine is performed during the execution of the state machine, and the programming of the state machine is performed without interrupting the execution of the state machine. To accomplish this, the first state address location can be read at any time and returns a valid data result. A method of achieving this is to atomically store the data in the first state address location. Another method provides two registers for the first state address, one active register and the other inactive register, and atomically activates the inactive register.

In one embodiment, the state machine memory is provided for simultaneous use by multiple state machines. According to this embodiment, there is the option of programming each of the state machines to be the same programming or to program some state machines differently. This involves programming of one of the state machines without interrupting the execution of any of the other state machines between executions of the state machines. An option for programming a state machine of the plurality of state machines without interrupting execution of any state machine of the plurality of state machines during execution of the plurality of state machines; And / or data related to another state machine of the plurality of state machines is left unchanged.
There is an option to program one of the state machines.

According to the present invention, there is also provided a method of programming a state machine memory that includes a plurality of locations and a storage location of a first state address, the method comprising: Providing an image; modifying the programming of the state machine; determining a modified state in the current state machine; including states that precede the modified state, including one new first state. Determining an unoccupied memory location in current state machine memory; storing in an unoccupied memory location in current state machine memory to form reprogramming data To the modified condition and Compiling a state preceding the modified state; storing reprogramming data in an unoccupied memory location of the current state machine memory; and after said reprogramming data is stored, said first Replacing the data in the one state address location with a new first state address; and updating the image of the current state machine.

Embodiments of the method further include: determining an amount of unoccupied memory; determining whether reprogramming data fits in unoccupied memory; and reprogramming. When the data does not fit in unoccupied memory, the portion of the modified state and the states preceding it are compiled to form new reprogramming data, and the reprogramming data is converted to the new reprogramming data. Replacing with.

Preferably, the program memory is only read by the state machine. This is accomplished by storing the current state address in memory outside program memory. In such an embodiment, only the reprogramming reprogrammer writes the data to program memory. This is useful because when multiple state machines are operating from the same memory, the state machine's data integrity is guaranteed for each state machine.

According to another aspect of the invention, there is provided a memory of a reprogrammable state machine for simultaneous use by multiple state machines, wherein the memory of the reprogrammable state machine is: A program memory for storing data relating to states within a program memory, wherein data for each state is to be stored at a state address; a plurality of initial state address memory locations; , Each of which is an initial state address memory location for storing a first state address of one of the state machines.
Memory location; a means for storing data in program memory, wherein the data associated with each new state is stored at a state address for the new state, and the data associated with the new first state is new. Means for storing the data at a first state address and storing the data in a storage location not occupied by any of a plurality of state machines; and storing the data corresponding to each new state. Means for replacing the data in the first state address location with the new first state address after being deleted.

Preferably, the plurality of initial state address memory locations are a plurality of registers, and one register is assigned to each state machine included in the plurality of state machines.

According to the present invention, a packet classification state machine for classifying data from a data stream is provided. This state machine is: a) A programmable program for storing information related to states in the state machine.
A memory, the state of which includes a first group of states and a second group of states, each of the first group of states being represented by a table of data at a table address, and from the table address. A first plurality of table elements addressable at offsets, each of the table elements indicating the next state in the state machine, and the second group of states each including one table element. Programmable memory comprising, and represented by a table of data occupying less memory than a table of data representing one of the states of the first group; and b) current at offset from table address. For determining the next state based on the contents of the state table element The offset shall be determined during the table address load part of the instruction cycle depending on the bits in the data stream, and in order to switch the state machine to the next state accordingly. The processor of.

[0025]   According to yet another embodiment of the invention, the data from the data stream is separated.
A packet classification state machine for similar purposes is provided. This state machine is:   a) Programmable to store state related information in the state machine
A memory whose states are in three groups:   2 addressable at each offset from the table address ⁿ Of the first group represented by a table of data containing
State, the table element indicates the next state in the state machine, n is the offset
The number of bits in the data stream to determine
Status;   Each is smaller than the size of the table element in the state of the first group
Having 2ⁿA second table represented by a table of data containing a number of table elements
In the group state, the table element is offset from the table address.
Addressable in the state machine and the table element indicates the next state in the state machine.
Where n is the number of bits in the data stream to determine the offset
Status of the second group; and   A third, each represented by data showing a single possible next state
Programmable memory, which includes the state of the group; and   c) Regarding the table address of the first group, the current state address and
And multiple bits from the data stream are stored together to form an address
The table address of the second group, the current state address and
And multiple bits from the data stream are stored together to form an address.
, And the table address of the third group, the current state address
A processor for storing; from its address in programmable memory
Retrieves the operation, where it is the next state address.
Includes jump operations containing data related to
Determines the next state based on one of the information in; and switches the state machine to the next state.
Processor to replace;   , In which it only retrieves information from programmable memory
An operation is executed during successive state transitions.

According to yet another aspect of the invention, there is provided a method of packet classification for classifying data from a data stream. The method comprises: a) providing classification data containing information relating to states in a state machine, the states including a first group of states and a second group of states, and Each of the states of the group of is represented by a table of data that includes a first plurality of table elements addressable at a table address at an offset from the table address, where each of the table elements is a state machine. The second group of states, and each of the states of the second group includes one table element and is one of the states of the first group.
Shall be represented by a table of data occupying less memory than a table of data representing one state; b) preparing a table address of the current state; c) selecting a table element, the table The element is a table
Shall be selected depending on the address, the contents of the table, and the offset based on multiple bits in the data stream; d) the next state machine based on the contents of the selected table element in the current state. And e) switching the state machine to the next state according to the determination.

DETAILED DESCRIPTION OF THE INVENTION As used herein, the term data packet refers to a buffer,
It includes frames, cells, packets, and similar concepts used in data communications. A data packet is basically a grouping of data that can be classified according to a predetermined classification. The taxonomy is generally codified by a standards body that oversees communication standards.

In the state diagram shown in the drawings, the state represented by the rectangle is the terminal state. Other than the terminal state, it is represented by using a triangle.

Referring to FIG. 1 a, there is shown a simplified state diagram for a state machine supporting a single data access operation per data cycle. Each state is in the form of a look-up table at the state address. States are represented as blocks with four state transitions, each shown as a line to another state. In some cases, some state transitions lead to the same next state. A predetermined number of bits (2 in the simplified state diagram of Figure 1a) are loaded into the least significant bits of the address and data is read from the newly formed address. If the data consists of another state address, the next predetermined number of bits from the data stream are loaded into the least significant bit of the address. If not, an action such as filtering or packet classification is executed.

In order to reprogram such a state machine, it is generally necessary to interrupt the operation of the state machine, resulting in undesirable “downtime”. The new programming is stored in the state machine's memory, after which the state machine continues to run. Unfortunately, the data flow does not stop if filtering or classification is disabled. Given the above, it is clear that interrupting the processing capabilities of a single state machine has negative implications. Therefore, a method of reprogramming a state machine without interrupting the operation of the state machine is desired.

For example, if a programmable state machine of this kind is implemented in hardware, the address of block 1 will be fixed. Normally this address will be zero. Of course, other fixed addresses are possible. Writing a "1" to a single block, for example, often requires storing data at each of several locations, thereby requiring more than a single clock cycle. Thus, there is time between reprogramming when the block is partially reprogrammed. While the block is partially programmed, indeterminate results may be reached when the state machine reaches the block. This is not desirable.

Referring to FIG. 1b, three state machines stored in a single memory are shown. Each is a completely separate block, so that they are independent of each other. To reprogram one of the state machines, it is only necessary to interrupt that one by itself. Unfortunately, when some state machines are completely independent, there is little benefit from storing their programming in a single memory. On the other hand, if multiple state machines share a single memory and share some programming, one reprogramming of multiple state machines shares that single memory. It will incur "downtime" associated with every state machine that does.

Referring to FIG. 1c, a state diagram similar to that of FIG. 1b is shown, in which three state machines share the same program memory and similar blocks, eg 6,6b, And 6c are stored as the same block 6. As is apparent from FIG. 1c, each state machine performs different programming. Currently, it is difficult to reprogram the state machine memory shown in FIG. 1c without interrupting the execution of all three state machines.

Referring to FIG. 2, a simplified flowchart of the method according to the present invention is shown. This state machine performs a classification function. Preferably, this classification function is an acyclic classification function, but it is not required. The state machine is based on a table lookup for each state transition and the information associated with each state transition is stored as a table of data at state addresses. In operation, the first state address is read from the storage location of the first state address. The first state address is the address read at the start of operation of the state machine. This first state address indicates the first table.

The state machine programmer has a processor to distinguish between storage locations having state machine data and those not having state machine data. Generally, this is done by maintaining information related to the location where the current state machine information is stored. The programmer is provided with a modification to the programming of the current state machine. For example, a table of data associated with the second state of the state machine is modified. The programmer writes any new information to the memory at a storage location that is not used by the current state machine. This unused storage location does not contain programming data for the current state machine.

As will be appreciated by those skilled in the art, linking a newly written state to an existing state in the state machine requires some state modifications,
It is not easy to do it while one or more state machines are running. One approach to solving this problem is to stop the operation of the state machine until the reprogramming is complete. Stopping the operation of the state machine is undesirable because it stops processing data. According to the present invention, each state that precedes all modified states is also written to program memory that is not used by the programming of the current state machine. The newly written state forms the start of state machine programming from the beginning of the state machine's operation to the point in the state machine's programming where no further modifications are made. When data is written, the first state of newly written data becomes the first state of the state machine. Thus, by modifying the information stored in the first state address location, the newly written state data is used during subsequent executions of the state machine-that is, the modified state machine is executed. It Preferably, this operation shall be performed in an atomic manner. It is possible to ensure that the first state address location read is not performed during the non-atomic first state address write operation; however, this results in a small amount of downtime for the state machine. ,
Therefore, it is not desirable. As used herein, the expression "modified state" refers to the newly created state as well as the modified state. From the above discussion, this does not lead to a pause in the execution of the state machine, or to minimize pauses when a non-atomic operation is used to store the first state address so that the state machine is in between states during operation. It will be apparent that machine memory can be reprogrammed. Once the first state address is updated, subsequent state machine executions use the modified state machine programming. However, unmodified programming of the state machine is performed until the first state address is updated.

Of course, when the first address is updated, the storage location associated with the modified state—that is, the state for the state data that has already been rewritten—is due to another different state machine. An unused storage location unless those states are used. The resulting,
Storage locations that are not used by the programming of the current state machine are then "recovered" for use in further processing the reprogramming of the state machine memory.

Generally, the first state address is stored in the first hardware register to allow fast access to that address. When hardware registers are used, atomic operations are typically used to write the first state address. For example, the number of bits stored in a single clock cycle is equal to the number of bits in a register. Alternatively, pseudo-atomic operations may be used. For example, in a write operation, many bits are written per available cycle, and when all addresses are available, these bits are all clocked into the register at the same time.
Still alternatively, a few clock cycles are used to write to the second separate register, and the flag bit is updated to replace the first hardware register with a new write. The register may be read as the first state address. Those skilled in the art will be aware of other methods of atomically migrating from a first hardware register with an old first state address to a hardware register with a new first state address. Will be clear from.

Alternatively, the first state address is a fixed address in program memory,
That is, in an atomic or pseudo-atomic manner, store at a fixed address that can be loaded from that address and stored at that address. Preferably, this first state address is accessible in a single clock cycle.

Referring to FIG. 3, a method of reprogramming a state machine between runs is shown in accordance with the present invention. The illustrated method relates to a state machine program memory for simultaneous use by multiple state machines.

Each state machine performs a classification function. Preferably, this classification function is an acyclic classification function, but this is not necessary.
This state machine, like the state machine described with reference to FIG. 2, is based on a table lookup for each state transition and the information associated with each state transition is stored as a table of data at state addresses. ing. In operation, the first state address is read from the storage location of the first state address. The first state address is the address read at the start of operation of each state machine. When the state machines are individually programmable, each state machine has a first state address associated with it.

The state machine programmer has a processor to identify the storage locations containing the state machine data and what else. Generally, this is done by maintaining information related to the location where the current state machine information is stored. The programmer is provided with a modification to the programming of the current state machine. In one example, the table of data associated with the second state of the first state machine is modified. The programmer writes any new information to the memory at storage locations not used by the programming of the current state machine. The unused storage locations do not contain state machine programming data associated with the current state machine. According to the present invention, each state that precedes all modified states is also written to program memory that is not used by the programming of the current state machine. The newly written states form the start of programming of each state machine from the beginning of each state machine's operation to the point at which no further modification is made in programming of each state machine. When data is written,
The first state of the newly written data becomes the first state of those state machines. Thus, by modifying the information stored in each first state address location, the newly written state data is used during the execution of each subsequent state machine, ie, each modified state data. State machine is executed.

As mentioned above, it is important that the modification of the first state address occurs in an atomic or pseudo-atomic manner. In the alternative, the state machine is suspended during the writing of the first state address. Otherwise, the first state address may be accessible during the writing of the first state address and the loading of the address to begin execution of the state machine may be pointless.

From the above description, it will be apparent that the state machine memory can be reprogrammed during execution of any number of state machines. When one of the first state addresses is updated, subsequent execution of the associated state machine involves programming the modified state machine. Until the first state address is updated,
Programming of the unmodified state machine is performed. In this way, the present invention allows reprogramming of one state machine when each state machine is performing a different programming without interrupting the operation of the other state machine.

Once the new first state address is stored, memory recovery is possible. Even if memory recovery is optionally performed immediately, reprogramming should not be performed until the currently running state machine is restarted. This prevents the state of the previously running state machine from being overwritten during that run. Next, an outline of a memory recovery method will be described.

With the data associated with each state, a counter is provided that indicates the number of states that reference that state. When the first state address register is modified, the counter associated with the data at the address pointed to by the contents of the first state address register prior to the modification has one reference to that state data. It is decremented because it decreases. When the counter reaches zero, the memory location associated with the state is recovered and the counter associated with the data referenced by the data in the recovered memory location is decremented. This memory recovery operation proceeds recursively until there are no counters with a zero value.

In an alternative embodiment, a timer is provided and a timing signal is provided to pause execution of the state machine when the timer expires. This is useful for programming the programmable memory not only when the program needs to be stored by a certain time period but also when it can be stored in advance at any time. The program is entered and reprogramming is performed according to the method described above. If the reprogramming is not completed by the specified time, the state machine is paused between the sort operation and the completion of programming.

According to another embodiment of the present invention, before supplying data to the state machine, a buffer is used to buffer it, and a timer is implemented to allocate processing time to the reprogramming task. You can decide. For example,
When new programming is introduced, it may be desirable to allocate 10% of the state machine or processing power to reprogramming. Of course, if the state machine requires less than 90% of the processing power, the reprogramming operation can also consume the available processing time. Non-limiting applications of the present invention are described with reference to FIGS. FIG. 4 shows states 1 to 11.
FIG. 6 is a state diagram of a current state machine having When it was desired to modify states 6, 10, and 11, in prior art devices, it was necessary to pause the execution of the state machine. For ease of description, 11 states are used to represent the state diagram, but the actual number of states will be limited only by the memory size of the state machine and the operations performed. Changes were made to the image of the state machine of FIG. 4, resulting in a modified state 6n,
The state machine represented by the state diagram of FIG. 5 with 12, 13, and 14 is obtained. As will be appreciated by those skilled in the art, many new states can be added or modified, the number of which is limited only by the memory size of the state machine memory. The memory contents for the state machine shown in FIG. 4 are shown in FIG. 6 with the modified states 1n, 2n, and 6n. The data associated with the new and / or modified state, 1n, 2n, and 6n, is written to a storage location in memory that is not used by the programming of the currently executing state machine. In FIG. 6, the state machine programming for both the state machine of FIG. 4 and the state machine of FIG. 5 is explicitly shown in the state diagram.
The first state diagram starts from state 1 and the second state diagram starts from state 1n. States 3, 4, 5, 7, 8 and 9 are common to both state diagrams. Actual state 1n
Is similar to state 1 but also different because state 2n is different. Similarly, state 2n is similar to state 2 but also different because state 6n is different. In order to clearly distinguish the state machine of FIG. 4 from the state machine of FIG. 5, the starting address of the state machine must be determined. When all new and / or modified state data has been stored in memory, the starting address of the state machine is updated to the new first state address, that of state 1n. Operations are performed atomically or pseudo-primitively. The next time the state machine begins execution, the newly stored data will be used. Sufficient state machine memory is provided so that programming of either state machine can be used depending on the selected start address. Therefore, even if the three state machines use exactly the same programming, it is possible to modify one programming and leave the rest untouched by giving three independent first state address locations. It is possible. While modifying the state machine programming, it is important that state transitions be maintained and "downtime" avoided. If the starting address is that of state 1n, then the state machine diagram of FIG. 5 becomes the current state machine diagram and has modified states 1n, 2n, and 6n.
A memory location associated with a state that is not accessed by any state machine--in this case, a state that is not accessed by a single state machine--is now a "free" storage location, or by programming the current state machine. It is a storage location that is not used.

As will be appreciated by those skilled in the art, all memory locations are occupied and the term “unoccupied” as used herein is occupied by the program data of the current state machine. Not pointing to a memory location.

Of course, when two or more memory banks are used, the switching between banks allows the offline banks to be reprogrammed while the execution of the programming is occurring in the online banks. It will be possible. In fact, in some situations, two memory banks become program memory and the starting address within each bank is identified by the current bank.
That is, the identifier for identifying the current bank forms the storage location of the start address. When using two banks, the starting address storage location need only accommodate one bit of data, which is necessarily written in an atomic manner.

Although the starting address is described herein as being stored in one location, the programming of the first state is assigned two locations and a selection between the two locations is made based on the indicator bits. It is also possible. In that case, the indicator bit is the start address-address "0".
, Or address "1"-, and data can be stored in flip-flops or in other conventional ways.

Also, for the step of loading the current state address at the start of execution of the state machine, we have mentioned loading the address from the starting address location, but using flip-flops to indicate the current memory bank. In case the first state programming address is, except for the selection of the appropriate bank,
Usually fixed. Therefore, although the fixed address is used to load the current state address, the memory location where the programming data is retrieved depends on the content of the data relative to the starting address. In this case, the contents of the current state address register will be less than the address data needed to determine the current state address, and the starting address location should use which of the fixed starting addresses it has available. As long as it is to determine
It will form part of the current state address.

Referring to FIG. 7, there is shown a simplified flowchart of a method of recovering memory not used by any of the currently executing state machines. When new state data is stored in program memory, the existing state data is left unchanged. When the first state address of each modified state machine is updated to reflect the new first state address for the respective state machine, the replaced state machine data is identified and unused state machine memory. Indicated as.

To identify unused memory locations, a value is stored with the state data for each state, which indicates the number of references to that state data. The state data referenced by the previous first state address is accessed and the value contained therein is decremented. If the value is "1" or greater, then there is still a reference to that state data and it is not indicated as unused memory. A zero value means that there are no more references to the state machine's data at that location, which is indicated as "not used". Subsequently, all state machine data referenced from that data is accessed and the value associated with it is decremented. This method
Run recursively until only state machine data with associated values of "1" or above is left. Of course, it is possible to implement the method iteratively if desired.

The use of this kind of method simplifies the recovery of the memory and allows the programming of the state machine containing all the information necessary for its programming and reprogramming. Therefore, it can be said that this has advantages.

Although a state is described herein as another state that precedes it or another state that follows it, this is the most suitable representation for an acyclic state machine. For a circular state machine, the expression "reachable from" is a more accurate representation of a state that follows another state. For example, that state A is reachable from state B is equivalent to state A following state B in the case of an acyclic state machine. A circular state machine in which state A is reachable from state B is shown in FIG. Even in this case, the incremental programming according to the present invention is effective. To modify a single node, all nodes reachable from the node being modified are updated. If any part of the graph is unreachable for the node to be updated, that part of the graph does not require modification.

Referring to FIG. 9 a, there is shown a simplified state diagram of a typical classification state machine according to the prior art. Transitions between states are represented by a series of operations indicated by lines connecting the states shown as circles. This state diagram pertains to an acyclic state machine, where each state has one of many possibilities.
One continues. A state machine of this kind can be easily implemented in both software and hardware. However, as the operating speed of the state machine increases, the operations for each state transition must be executed simultaneously in order to ensure the required performance. To date, this bottleneck has required a dedicated non-programmable hardware state machine design.
FIG. 9b shows a condensed state diagram for the state machine of FIG. 9a. Referring to this, the terminal state A of the classification is integrated into a single state 901a. Similarly, other states are being integrated. As is clear from this figure, the number of edges representing the state transitions is somewhat smaller, that is, 20 to 16. Some states such as the state R are “accept” or “reject” terminal states.
A restart of the state machine follows these states. Restart generally occurs before the start of the packet that follows. Usually, there is a means for identifying the start of each packet, which is not included in the present invention.

Referring to FIG. 10 a, a very simplified protocol schematic diagram for packet classification is shown. This simplified protocol facilitates understanding of the invention without detailed knowledge of Ethernet or other communication protocols. Four bit patterns are shown, each representing a different classification. Each bit pattern is similar. The first set of 3 bits must be "1", otherwise the data stream is left unclassified. It is followed by 8 bits, whose existence is meaningful, but not important for classification. The subsequent 3 bits must also be "1", followed by 8 bits "unrelated" to the classification.
The last 2 bits are used to distinguish between the 4 classifications. In Figure 10b,
3 illustrates a classification tree implementing a programmable state machine. A typical packet classification tree contains data related to multiple classification protocols, each having a large number of bits; therefore, the classification tree shown in Figure 10b is a simplification to facilitate the description of the invention. Is. A typical classification tree results in a very large data structure that is often too large to be stored in a single integrated memory device.

For Gigabit Ethernet, the arrival of a single bit is within 1 nanosecond. For a Gigabit Ethernet packet classification state machine that operates on 3 bits per state, the first 3 bits arrive in 3 nanoseconds. After it has been provided to the state machine, there is a 3 nanosecond delay before the arrival of the next 3 bits. During this 3 nanosecond, all the operations related to the state transition are completed. Of course, if more time is needed to prepare for a state transition, then group more bits. Thus, depending on the speed of communication, the state machine for classification, which uses 2 bits at a time, may be 8 bits or 1 at a time.
It is possible as well as using 6 bits. The use of embedded memory within a programmable device allows for fast memory access operations, and thus for 8-bit operations-or 8 nanoseconds per state-the same programmable programmable for each state transition. Up to two consecutive memory access operations from memory are possible and, more likely, a single memory access operation.

A state of this kind can easily be implemented using the form of a look-up table with a large number of addresses or another form of address translation. For lookup table implementations responsive to receipt of eight data bits, only a single memory access is required to determine the next memory address for the lookup table. In one example, the current table address is loaded into the upper bits of the register. The 8 bits from the data stream are loaded into the lower bits of the register and act as an offset of 0-255. After being loaded, the data at the location pointed to by that register is loaded into the upper bits of that register. The check is then done for "accept" or "reject" and the next 8 bits from the data stream are loaded into the low order bits to form a new address. This is repeated until the terminal state is reached.

As described above, for a large number of bits, the look-up table storage becomes very large, and the use of an external memory device is inevitable, resulting in an increase in cost and a decrease in performance. Therefore, there is a practical limit to the number of bits that can be processed in parallel in the programmable state machine. Also, memory circuits that can support the required speed are currently limited to integrated memory circuits, which limits the amount of memory that can be used as classification data. Given this limitation, memory optimization offers significant advantages.

To the packet classification state machine, the resulting state is important in determining the operation and class of the packet. Therefore, the packet classification state machine follows a tree structure. Each node in the tree is 1 as shown in Figure 2b.
If associated with bits, the tree would be very large, with many nodes each having two child nodes and one parent node. If each node was associated with 8 bits, the tree would have much less levels, but would in fact have a similar number of edges. Figures 10c and 10d show the case where 2 bits and 3 bits are associated with each node, respectively. As will be apparent to those skilled in the art, many nodes are unimportant, and for this purpose the optimization of those nodes useful for packet classification is an important aspect of programmable state machines.

The preferred method of optimizing the classification data uses a new memory optimization technique to provide contracted classification tree data with the same information in it. 10b, 10c, and 10d, a modified representation of the same classification tree is shown. As can be seen, there are many nodes that need more or less information than others. This is used in accordance with the present invention to optimize memory storage requirements. For example, if each node with only one possible next node-each edge from that node leading to the same destination node-is stored as a single edge, the edge shown in FIG. Is reduced from 50 to 34. This is a big reduction considering the overall storage requirements. Of course, different savings in the number of edges used per node will yield different savings. For example, using the same optimization technique, the number of edges in the tree shown in FIG. 10c is 48 to 27, and the number of edges in the tree shown in FIG. 10d is 64.
To 36.

The preferred method also groups the nodes into several categories, each of which requires different amounts of storage—ie full-width nodes; half-width nodes; full-width irrelevant nodes; half-width irrelevant nodes, etc. Is. By having different nodes occupy different memories, the memory requirements are significantly reduced. Moreover, the representation of the data as one of the groups can be easily identified. If there are 4 groups, then 2 bits are sufficient to sort the elements into a particular group. As described above, it is preferable to optimize the memory, because the performance is degraded when the external memory is used. Of course, other forms of memory usage optimization can be applied in the context of the present invention.

To implement the tree traversal method according to the present invention, whether each edge extending from a node--each address--is a full-width edge or a half-width edge, and it is a word. It is preferred that they be individually addressable, whether aligned or not. For example, full-width nodes are word aligned,
It requires 2 ⁿ words for a 2 ⁿ directional node.

[0066]   Half-width nodes can be word aligned or half-width words aligned. to this
Of the bits from the data stream for full-width and half-width nodes
Allows consistent concatenation, where 1 bit for half-width nodes
Selects between the right half of the word and the left half of the word-that is, the half word
A selection between word and word alignment is made. Naturally, the full width node
However, no additional bits are needed. In FIG. 12, the half-width node is within the word
2 to the right or left ofⁿIs shown as a half word. Alternative
, The half-width nodes are word-aligned-2 for each pair of edges. ⁿ 2 for direction nodes^n-1Is required.

To support the speed required for Gigabit Ethernet, it is preferable to process all bit operations in a single step. To accomplish this, each edge includes information identifying the group of nodes to which the edge extends. This additional information includes the two bits mentioned above and, in the case of half-width nodes, also one bit indicating the right or left half of the word. Note that here, a half word is called a byte regardless of its size. It is advantageous to select the appropriate byte for the current node since the half-width nodes are aligned with the bytes and the word is read for each state transition. A suitable method for doing that will now be described with reference to FIG.

In a packet classification implementation that can support fast packet classification with substantially optimized memory usage, the following edge contents of the classification tree are used: “accept”, “accept”. "Reject" and "Jump". Of course, other operations are possible. Some operations may require more or less bits and thus another group of nodes.

“Accept” indicates that the packet is classified—reaching the leaf of the classification tree—and that appropriate action on the classified packet is desired. Some of the appropriate actions of some form are passing the classification tag to the system or user, passing the packet to a predetermined routine,
Pushing packets onto the application stack for known applications, etc. Packet processing is well known in the field of Ethernet communication.

“Reject” indicates that the packet is not a classified packet type.
Therefore, no "proper" action is taken, but in many situations there is a default action that is desirable. For example, passing a "deny" tag to the system or user to indicate that the classification was not successful.

A “jump” affects the contents of the current state register. In effect, this operation results in a change of the current node and hence of the current state. The "jump" operation loads the address contained in the word with the "jump" operation into the status register. This results in a change of state-i.e. A change to another node in the classification tree. As a result, a memory access is performed to retrieve edge information, and a register-to-register transfer is performed to load the new contents into the status register. Using a packet classification state machine specifically designed for the implementation of the invention, these actions are easily performed within the existing time constraints. This performance is possible by including the command and data needed to complete the command in the same word as the data.

FIG. 11 is a table showing the contents of words in the memory. Each word in the full-width node comprises 2w + 2 bits, where w is a sufficient number of bits to represent the address in the classification tree—in the state machine. As is clear from this table, all other commands, except the "accept" command, fit within half a word. Alternatively, some memory
Represents an address and makes some "jump" operations full width. This is important for state machine optimization. As shown, this width need not include the low order bits, it is inserted from the data stream to be sorted.

Here, if the half-width node data is stored contiguously—that is, if two table elements in the same table form a single word—the least significant bit from the data stream is the word. The bit needed to load the desired halfword until the right or left half is shown, thus loading that bit.
It should be noted that the shift or multiplexing setup cannot start. Alternatively, if all edges associated with a given node are stored in the right or left byte, the least significant bit of the half-width node address, that is, the least significant bit not inserted from the data stream. Bits indicate the right or left half of the word-upper or lower, respectively. To facilitate the operation of the state machine, all edges associated with a given node are stored in the right or left byte, and the bits in the node data are used in place of the least significant bit in the right or left byte. It has been found that identifying the left side allows the data path setup to begin prior to reading the data, thus improving overall performance.

Preferably, an indication of whether the node is half-width, full-width, or irrelevant is registered and stored for subsequent use in subsequent states. The node information of the acyclic state machine is directly stored in the memory. Preferably, a protocol description is provided and during configuration these selected protocols are compiled into a classification tree, optimized and stored in the program memory of the state machine device. The state machine node has two of the following formats, which eventually lead to four possible formats: full width / half width and irrelevant / 2 ⁿ directions. Each of these node formats is associated with a format for storing information for edges extending from that node. Irrelevant nodes
It has one edge towards the following state node. A 2 ⁿ direction node has 2 ⁿ edges. Full-width nodes are implemented such that each edge is assigned a complete word, and half-width nodes store the information associated with each of the two edges in a single word. Basically, some edge information requires half a word or less, and some edge information requires more. If an edge from a node requires more than half a word of information for fulfillment, then all edges from that node are full width. Otherwise, the edge is optimized for half width. Also, if all edges from an edge are equal, the storage is reduced to a single edge. Of course, other node types with memory storage optimizations are possible within the scope of the invention.

Referring to FIG. 12a, a memory map of a packet classification data memory according to the present invention is shown. The memory is divided into four areas. These regions support nodes in four formats-full width and half width irrelevant nodes, and full width and half width 2 ⁿ directional nodes. Each "jump" instruction has an additional 2 bits to identify the type of next node-i.e. Irrelevant / ²ⁿ directions and full width / half width. In the case of a half-width node, an additional 1 bit is used to indicate whether it is word aligned or right aligned (half word aligned).

Next, regarding optimization of the data representation of the state machine according to the invention, see FIGS.
Description will be given with reference to the classification tree diagrams of 0c and 10d. The resulting memory contents are as in Figures 12b, 12c, and 12d, respectively. Since the data structure of the classification tree is very small, it is difficult to understand the memory saving effect from this result. For example, referring to FIG. 4d, 2 ³ directions tree appear to require significantly more memory than two directions tree. However, an analysis reveals that much of the memory space is unused. Larger trees tend to use space more efficiently. Also note that although the overall number of nodes is greatly reduced in the tree of FIG. 10d, the corresponding memory requirements are similar. Without memory optimization, the tree of FIG. 20b requires storage for 50 edges, and FIG.
The tree of d will require storage for 64 edges. Therefore, it is advantageous to maintain similar memory storage requirements even for trees that have more edges per node.

In each of the tables of FIGS. 12b, 12c, and 12d, the half-width irrelevant nodes are above the thick line and the half-width 2 ⁿ directional nodes are below the line. Since the first node is a 2 ⁿ directional node, it is shown at the first address on the left side (word justification) below the thick line in each table. Also, when the "accept" operation is full width, there will be a full width node section of memory. Since there are only four classes here, half-width "accept" instructions are supported.

Referring to FIG. 12b, this state machine starts at address 00100x. The least significant bit, shown as x, is combined from the data stream. This results in an instruction-here "reject" or "jump". This instruction is retrieved and executed.

A simplified block diagram of the classification state machine according to the present invention is shown in FIG. This state machine is useful for classifying data from a data stream, especially for classifying data packets. As shown, this state machine is a single integrated circuit 1100.
It is integrated within. Integrated circuit 1100 includes programmable memory 1110.
, Processor 1130, and programmable memory arbiter 1140.

The programmable memory 1110 is preferably in the form of high speed static random access memory (RAM), which can achieve performance speeds that enable support for high speed operations. Of course, with respect to slow operation, for example, the speed required for a 10 megabit Ethernet packet classification state machine, the well-known DRAM
The circuit can be used to increase density and reduce cost. RAM 11
10 is provided for storing information related to classification of stream data-classification tree data. In other words, RAM 1110 will be provided to store data related to the state in the state machine.

For example, in RAM 1110, data associated with each state machine node is stored. The data is stored in tables, each table having a table address and a table format. The processor 1130 can access the RAM 1110 once per state transition.
Further, in accessing the classification data in the RAM 1110, the processor 1
130 has the highest priority. This ensures that the state machine performance is not affected by any other RAM access operation. The programmable memory arbiter 1140 controls access to the RAM 1110. The programmable memory arbiter 1140 ensures that reprogramming the RAM 1110 does not impact the performance of the state machine. In effect, at low speeds, the arbiter 1140 guarantees the processor a single access to the RAM 1110 for each state transition. For higher data rates, the arbiter prohibits RAM access by anything other than the processor 1130 while the sort operation is in progress. This basically requires reprogramming of the programmable memory 1110 when the state machine is disabled and reprogramming is enabled, or when the incoming data is part of a classified packet and needs to be classified. Only when there is no packet to do. State machines are generally disabled to allow reprogramming when used within security applications that require changes to the contents of programmable memory due to security concerns.

The processor 1130 is programmable by an upper limit of once per state transition.
Information is retrieved from the memory 1110. Preferably, during classification, a single access to the programmable memory occurs for each state transition. Of course, after the data has been sorted, there will be a pause in the operation of the state machine until the start of the next packet. During this pause, the RAM arbiter 1140
Allows programming of RAM 1110. Therefore, the state machine is fully programmable, even at very high speeds.

The processor retrieves the data from RAM 1110 and uses that data to perform operations to determine the next state, which in turn switches the state machine to the next state determined there.

Although an “accept” operation is provided here with a small number of bits to indicate the classification, it can be increased using any of several methods. In the first method, an "accept" operation is performed with a value that is an index to the classification, thereby allowing a long classification code.
Instead, it implements the "accept" operation using a full width node that provides an additional w bit for the classification result. Of course, it is also possible to combine these two methods.

Arbiter 1140 preferably provides processor 1130 with transparent access to programmable memory 1110. This is accomplished by blocking the memory access operation for reprogramming the programmable memory 1110 when the memory access from the processor 1130 is a potential operation. Processor 11
Since 30 is assigned the highest priority, it is important that it not be blocked when attempting to access programmable memory 1110. Alternatively, other methods of arbitrating between ports can be used.

As a matter of course, since the processor does not access the programmable memory 1110 more than once for each state transition,
If multiple RAM accesses are possible for one state transition, the processor is assigned one access to the programmable memory 1110 and the programmable memory is reprogrammed during the remaining memory accesses in the same state transition. Can also be executed.

When new packet data is detected, the processor is provided with a starting address for initiating a sort operation. This starting address is programmable and is used in accordance with the method of reprogramming a programmable memory, as described next.

The clock source for use in accordance with the present invention is selected based on the application and current knowledge in the field. It is well known in the field of communication hardware design to select and implement clock sources and methods of synchronizing clocks to clock sources provided by the network.

Unlike conventional solutions for Gigabit Ethernet, which rely on a high-speed host CPU or embedded CPU to examine each frame in real time or near real time, the present invention is easy to scale to Gigabit rates. . A CPU with 10 times the speed per port is not economical. further,
The required processing speed varies with the complexity of the classification criteria. According to the invention, there are no such restrictions.

In another embodiment, when implementing a packet classification state machine for a 10 Megabit Ethernet, multiple processors have the same programmable memory 11
Use 10. This is shown in FIG. The resulting system has multiple processors 1130 and a single programmable memory 1110. Each state machine simultaneously classifies data according to different classification tree structures.
Alternatively, several processors may follow the same classification tree structure. Also, the classification data associated with each processor can be independently programmed.

Reprogramming of the programmable memory 1110 adds new table data related to the change from the existing node in the tree to the root of the tree within the classification tree structure of one or more state machines. It can be achieved by going down. It then supplies the root address as the starting address to the processor executing that state machine. Programmable memory 1
When the tables stored in 110 are no longer used by any processor, they will reuse their memory locations during subsequent reprogramming. In this way programming is possible during the operation of the state machine without affecting existing programming operations or existing classification operations.

For the above reasons, it is important to automate the generation and optimization process of the classification data table as much as possible. After being automated, the packet classification details are
It becomes less important in the sense of procedure and becomes the process of pattern matching. In essence, the tree structure remains a problem for packet classifier compilers. Not surprisingly, there are two classes-ie "acceptance" and "acceptance".
A similar system can be applied to filtering considered packet classification with "deny"-.

Applying the memory optimization technique according to the invention leads to a considerable memory optimization. This is an integrated programmable
Enables implementation of packet classification state machine. In order to achieve reasonable performance and cost, it is useful to optimize the generated table data by compressing the table from a group of expressions into one minimal expression.
Of course, other expressions are used if desired. Also, higher or lower optimizations will be used depending on the particular application.

Preferably, the compiler software maintains an image of the data in programmable memory to determine the memory in use and memory locations that are no longer part of the classification data for any state machine. In this way,
By allowing the memory to be reused when the contents of the memory become obsolete, the frequency of memory overflow is reduced. This is simply possible, but because the present invention supports incremental programming and the program memory can support multiple processors, it is very useful in automatically tracking memory allocations.

Although the preferred embodiment uses a single access by the processor to the programmable memory in a single state transition, unnecessary accesses to the programmable memory are replaced, for example using a counter. The present invention can also be implemented in this mode. That is, if four "irrelevant" states are consecutive, the count command is loaded with the count number "4" and the next address. Data is fetched from the next address in the programmable memory each time the counter completes the specified number of counts. For one "irrelevant", this precludes one memory access.

As will be appreciated by those skilled in the art, programmable memory is accessed by the state machine processor for read purposes. The state machine processor never writes to programmable memory. In contrast, programmable memory programming requires only write operations. Therefore, separate write access and read access—ie dual ported—is suitable for the present invention. In yet another embodiment, true dual port memory is used, eliminating the need for memory arbitration or providing it in memory circuitry. Alternatively, programming and diagnostics use read-write access to the programmable memory while the processor has read access to the programmable memory.

Preferably, the present invention is implemented in a custom IC such as an ASIC. For example,
When moving to gigabit data rates, more efficient handling of frames rejected by the classification process is achieved by integrating the classification system within the MAC. After the "deny" decision is made, the MAC stops DMA for frames arriving in host memory, or if DMA has not started yet,
Flush that frame from that queue. It then uses the same receive descriptor without any driver software, thereby reducing traffic on the host's bus.

There are several other advantages of integrating the method according to the invention in the MAC. To do this: Remove the host bridge and load the pattern memory through the interface of the MAC to reduce the load on the host bus; No storage is needed to associate the ring descriptor with the sort result as needed; in addition, the receive ring descriptor is located anywhere in the driver's wishes, thus benefiting from the cache. It can be maximized.

Alternatively, when implemented in an FPGA, the design is preferably optimized for implementation in the type of FPGA used.

It is also possible to implement "irrelevant" bits using an "irrelevant" mask, so that individual bits are "relevant" bits and the others are "irrelevant" bits. This is a simple problem when the "irrelevant" bits fall on either side of the table element's data. When performing this function for bits in the middle of a table element's data value, a shift operation is performed depending on the mask data in order to align the bits properly and adjacent to each other. Due to the speed required of the classification state machine, this type of shift operation can require significant hardware. Using this approach, a single "don't care" bit eliminates 2 ³¹ possibilities for a 32-bit packet classification engine.

Numerous other embodiments of the invention are possible without departing from the spirit or scope of the invention.

[Brief description of drawings]

Embodiments of the present invention will be described below by way of example with reference to the accompanying drawings.

1a and 1b:   FIG. 6 is a simplified state diagram for a classification state machine according to the prior art.

[Fig. 1c]   FIG. 6 is a simplified state diagram for a classification state machine according to the present invention.

FIG. 2 is a simplified flowchart illustrating a method of reprogramming a state machine during execution according to the present invention.

FIG. 3 is a simplified flowchart illustrating a method of reprogramming multiple state machines during execution in accordance with the present invention.

[Figure 4]   FIG. 7 is a simplified state diagram of a highly simplified state machine.

FIG. 5 is a simplified state diagram with modifications of the highly simplified state machine shown in FIG.

FIG. 6 is a simplified state diagram showing a combination of the state machines shown in FIGS. 4 and 5.

[Figure 7]   6 is a simplified flowchart illustrating a method of memory recovery according to the present invention.

[Figure 8]   FIG. 3 is a simplified state diagram of a circular state machine for explaining the method of the present invention.

9a and 9b.   FIG. 6 is a simplified state diagram for a classification state machine according to the prior art.

FIG. 10a shows a simplified packet descriptor for classifying a packet as one of four classifications: A, B, C, or D.

FIG. 10b   FIG. 11 is a simplified diagram showing a classification tree for the packet classification shown in FIG. 10a.

FIG. 10c shows a classification tree equivalent to the classification tree shown in FIG. 10b, using 2 bits per symbol.

FIG. 10d shows a classification tree equivalent to the classification tree shown in FIG. 10b, using 3 bits per symbol.

FIG. 11 is a table showing memory usage and opcodes for an exemplary implementation of a state machine in accordance with the present invention.

FIG. 12a is a simplified memory map for state machine memory according to the present invention.

12b is an address table for the classification tree implemented for the classification tree of FIG. 10b.

12c is an address table for a classification tree implemented for the classification tree of FIG. 10c.

12d is an address table for a classification tree implemented for the classification tree of FIG. 10d.

FIG. 13 is a simplified block diagram illustrating an integrated circuit implementation of an acyclic classification state machine according to the present invention.

FIG. 14 is a simplified block diagram of a system in accordance with the invention that implements multiple state machines using a single identical programmable classification data memory.

─────────────────────────────────────────────────── ─── Continued front page    (31) Priority claim number 09 / 459,460 (32) Priority date December 13, 1999 (December 13, 1999) (33) Priority claiming countries United States (US) (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, SD, SL, SZ, TZ, UG, ZW ), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, C N, CR, CU, CZ, DE, DK, DM, DZ, EE , ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, K P, KR, KZ, LC, LK, LR, LS, LT, LU , LV, MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, S G, SI, SK, SL, TJ, TM, TR, TT, TZ , UA, UG, US, UZ, VN, YU, ZA, ZW

Claims (55)

[Claims] 1. A program memory for storing programming data relating to at least one state machine state and state machine transitions; and atomic and near atomic write operations of data to an entire location. One of which is programmable
A start address memory location for storing data indicating a start address for programming the state machine stored in memory, the start address being capable of being reprogrammed during operation of the state machine; A reprogrammable state machine comprising: 2. The reprogrammable state machine of claim 1, wherein the data indicative of the starting address comprises data indicative of an address of data associated with the first state for execution within the state machine. 3. The reprogrammable state machine of claim 2 having a current state address register separate from the program memory and having a current state address for the state machine stored therein during execution of the state machine. . 4. The reprogrammable state machine of claim 2, wherein data associated with the first state for execution in the state machine is stored in memory that is read-only to the state machine. 5. Data associated with each new state is stored at a state address for the new state, data associated with a new first state is stored at a new first state address, and the data is a state machine. Means for storing data in program memory, stored during execution of the state machine, in a storage location not occupied by; and after the data corresponding to each new state has been stored 3. The reprogrammable state machine of claim 2, further comprising: means for replacing data indicating a starting address in the address memory location with data indicating a new starting address. 6. The reprogrammable state machine of claim 5 having a current state address register for storing a current state address. 7. The reprogrammable state machine of claim 6, wherein re-execution of the state machine is initiated by loading the current state address with an address based on the contents of the starting address memory location. 8. The reprogrammable state machine of claim 7, wherein the data indicative of the new starting address comprises an address of data associated with the first state for execution within the state machine. 9. The reprogrammable state machine of claim 8, wherein re-execution of the state machine is initiated by loading the current state address with an address previously stored in a starting address memory location. 10. A step of determining a state pointed to by a first state address to be replaced; and a step of repeatedly executing the following: wherein the step of repeatedly executing the determined Decrementing the counter associated with the state; and, when the counter reaches zero, determines that the data associated with the state is unoccupied and is pointed to by the data in the determined state. The method according to claim 1, further comprising: selecting a state to be determined as the determined state. 11. A program memory for storing state-related data in each state machine at a state address; each initial state address memory location being one of a plurality of state machines.
Multiple initial state addresses that store the first state address of one state machine
A memory location; data associated with each new state is stored at a state address for the new state, data associated with a new first state is stored at a new first state address, and Stores data that is stored in a storage location that is not occupied by data that forms part of
Means for storing data in program memory; after the data corresponding to each new state has been stored, a new first state address location, in atomic or pseudo-atomic manner, is stored. 1
Means for storing the state address of the reprogrammable state machine for simultaneous use by multiple state machines, including; 12. An atomic or pseudo-atomic aspect is defined as one that eliminates operations for reading a first state address location during a store of a new first state address. Item 11. The reprogrammable state machine of item 11. 13. The method of claim 11, comprising a plurality of current state address registers, each associated with a respective state machine of the plurality of state machines, for storing a current state address of the associated state machine. Reprogrammable state machine. 14. Re-execution of one of the state machines comprises:
2. Starting by loading the current state address register associated with the state machine with an address based on the contents of an initial state address memory location associated with the state machine.
A reprogrammable state machine as described in 3. 15. Re-execution of one of the state machines comprises:
15. The reprogrammable state machine of claim 14, starting by loading a current state address register associated with the state machine with an address previously stored in an initial state address memory location. 16. Providing data corresponding to each new state, including one new first state, including data corresponding to all states reachable to each new state; Program the data associated with each new state stored at the state address, the data stored in a storage location not occupied by the data associated with the currently running state machine.
Storing in memory; a new first state related data stored at a new first state address stored in a storage location not occupied by data for use with a currently executing state machine. Storing ;; after the data corresponding to each new state is stored, atomically or pseudo-atomically replacing the data in the first state address location with the data indicating the new first state address. And ;; a method of reprogramming a state machine memory having a plurality of storage locations and a first state address storage location. 17. Atomic and pseudo-atomic are defined as in a manner that precludes operations for reading a first state address location during a store of a new first state address. A reprogrammable state machine of the described method. 18. The method of claim 16 wherein the state machine is acyclic, where the new state is reachable from the states preceding the new state. 19. The method of claim 16, wherein reprogramming the state machine is performed during execution of the state machine. 20. The method of claim 19, wherein reprogramming the state machine is performed without interrupting execution of the state machine. 21. The state machine memory is for simultaneous use by multiple state machines, wherein programming of a first state machine of the multiple state machines is performed by the plurality of state machines. 20. The method of claim 19, which is the same as programming the second state machine of the. 22. The state machine memory is for simultaneous use by a plurality of state machines, wherein programming of a first state machine of the plurality of state machines is performed by the plurality of state machines. 17. The method of claim 16 different from programming the second state machine of the. 23. The state machine memory is for simultaneous use by multiple state machines, wherein programming of one of the multiple state machines is performed by the state machine memory. 17. The method of claim 16, wherein the method is performed during execution without interruption of execution of any other state machine of the plurality of state machines. 24. The state machine memory is for simultaneous use by multiple state machines, wherein programming of one of the multiple state machines is performed by the multiple state machines. 17. The method of claim 16, wherein the method is performed without interruption of execution of any of the state machines of the plurality of state machines during execution of. 25. The state machine memory is for simultaneous use by multiple state machines, wherein the plurality of state machines are programmed during programming of one of the state machines. 17. The method of claim 16, wherein data related to another of the state machines is left unchanged. 26. Providing an image of a current state machine memory on a computer; modifying the state machine programming; determining a modified state in the current state machine; Determining states in which the modified state may be reached, including states of one; determining a memory location in the current state machine memory not occupied by data associated with the running state machine. A modified state and said modification to store at a memory location in the current state machine memory not occupied by data associated with the running state machine to form reprogramming data. The state that compiles the states that precede the Storing the reprogramming data in a memory location in the current state machine memory that is not occupied by data associated with the running state machine; and after the reprogramming data is stored. Replacing data in the first state address location with a new first state address; updating an image of the current state machine; A method of programming a state machine memory that includes locations. 27. The method of claim 26, wherein the step of replacing the data in the first state address location with the new first state address is performed atomically or pseudo-atomically. 28. Atomic and pseudo-atomic are defined as in a manner that precludes operations for reading a first state address location during a store of a new first state address. A reprogrammable state machine of the described method. 29. The step of determining a memory location in the current state machine memory that is not occupied by data associated with the running state machine comprises: determining the state pointed to by the first state address being replaced. A step of repeatedly executing the following steps: a step of repeatedly executing a step of decrementing a counter associated with a determined state; and a state of the counter when the counter reaches zero. 27. Determining that the data associated with is unoccupied; selecting the state pointed to by the data in the determined state as the determined state. Method. 30. a) having a programmable memory for storing information related to states in a state machine, the states including a first group of states and a second group of states, The state of the group of 1 is the table
A first plurality of table elements represented by a table of data at addresses and addressable at an offset from said table address;
Each of the table elements shall indicate the next state in the state machine,
And each of the states of the second group is represented by a table of data that includes one table element and occupies less memory than a table of data representing one of the states of the first group. And b) a processor for determining the next state based on the contents of the table element of the current state at the offset from the table address, the offset being in the data stream. A processor for switching the state machine to the next state in accordance with the decision, which is to be determined during the table address load part of the instruction cycle. A packet classification state machine for classifying data. 31. The packet classification state machine for classifying data according to claim 30, wherein the table element contains data related to a format of the table element in the next state. 32. The table of data representing one of the states of the first group each occupy the same amount of memory and have the same number “n” of table elements. Packet classification state machine. 33. Each of the tables of data representing one of the states of the first group, when represented as N, is the number of bits used by the processor to determine an offset from the table address. 33. The packet classification state machine of claim 32, having ^2N table elements. 34. The packet of claim 32, wherein each of the tables of data representing one of the states of the second group occupies the same amount of memory and contains only a single table element. Classification state machine. 35. The packet classification state machine of claim 30, wherein the processor includes means for determining a size of a table element in the table and means for loading an element of the determined size. 36. Means for determining the size of a table element in a table, means for determining an alignment of a table element within a data word, and table element of the determined size having the determined alignment. 36. The packet classification state machine of claim 35 including means for loading the contents of 37. Each of the tables of data representing one of the states of the second group includes data representing only one next state.
A packet classification state machine described in 0. 38. a) including a first group of states and a second group of states, each of the first group of states at a table address:
Represented by a table of data comprising a first plurality of table elements addressable at an offset from said table address, each of said table elements indicating a next state in a state machine, a second group Each of the states in the state machine is represented by a table of data that contains one table element and occupies less memory than a table of data representing one of the states of the first group. B) providing the table address of the current state; and c) the table element is the table address, the contents of the table, and the data.
Selecting a table element, which shall be selected depending on an offset based on a plurality of bits in the stream; and d) next to the state machine based on the contents of the selected table element in the current state. Determining the state; and e) switching the state machine to the next state according to the decision; a method of packet classification for classifying data from a data stream. 39. Steps (c), (d) and (e) are performed iteratively, in which switching the state machine to the next state, wherein step (e) is a table of tables representing the next state. 39. A method of packet classification for classifying data from a data stream according to claim 38, comprising the step of providing the address as a current state table address for the next iteration. 40. The step of determining the next state of the state machine comprises concatenating bits in the table address and the data stream to form an element address for states included in the first group of states. 39. A method of packet classification for classifying data from a data stream according to claim 38, wherein executed data in memory at said element address is indicative of said next state. 41. The method of packet classification for classifying data from a data stream of claim 38, wherein the bits are consecutive bits within the data stream. 42. The step of determining the next state of the state machine concatenates the table address and successive bits in the data stream to form an element address for the states contained in the first group of states. 42. The method of packet classification for classifying data from a data stream of claim 41, wherein the data in memory at said element address is indicative of the following states. 43. The method of packet classification according to claim 38, wherein steps (c) and (d) are performed for each state transition. 44. The method of packet classification according to claim 38, wherein the classification data is an acyclic classification tree. 45. The classification data is optimized by determining the states that have only one possible next state and storing them as a table representing the states contained in the second group of states. 45. The method of packet classification according to claim 44. 46. Some information related to a state is an "irrelevant" operation, wherein some information related to a previous state includes an operation for which the next state is "irrelevant". 45. The method of packet classification of claim 44, wherein the state comprises fewer table elements than a state that has no "irrelevant" operations. 47. Some information relating to a state is subsequently irrelevant.
The method of packet classification according to claim 44, wherein the method is a counter indicating the number of operations. 48. The states of the first group are represented by a table having elements with a width of m bits and the states of the second group are represented by a table having elements with a width of approximately m / 2 bits. 39. The method of packet classification according to claim 38. 49. Each of the first group of states and the second group of states is 2 ⁿ table elements, where n is the number of bits in the data stream upon which table elements are selected. 49. The method of packet classification according to claim 48, represented by a table having 50. The method of packet classification of claim 38, wherein state-related information in the state machine is stored in memory, the information including information related to alignment of table elements in memory. 51. The method of packet classification according to claim 50, wherein the table of table elements is stored in memory with the same alignment. 52. The method of packet classification of claim 38, wherein the state-related information in the state machine includes information related to the width of table elements related to the next state. 53. a) To store state related information within a state machine
Programmable memory, wherein the states are three groups of states:
Wachi:   2 addressable at each offset from the table address ⁿ Represented by a table of data containing a number of table elements, said table element
Indicates the next state in the state machine and n is the data for determining the offset.
The state of the first group as the number of bits in the data stream;   Each is smaller than the size of the table element in the state of the first group.
Having an iz 2ⁿIs represented by a table of data containing
Table elements are addressable at offsets from the table address
Where the table element indicates the next state in the state machine, n is the offset
The state of the second group, which is the number of bits in the data stream to determine
;   A third, each represented by data showing a single possible next state
Group status and;   c) A current state address for the table address of the first group.
Address and store multiple bits from the
Create and current address of the second group of table addresses
And store multiple bits from the data stream together to address
, And with respect to the table addresses of the third group, the current state
Store the dress and operate from that address in programmable memory.
And the operation contains data related to the next state address.
Including a jump operation; based on one of the information in the operation
Determine the next state; and the processor that switches the state machine to the next state;   And the only operator that retrieves information from the programmable memory
Partition from the data stream, which is executed during successive state transitions.
A packet classification state machine for classifying data. 54. A packet classification state machine for classifying data from a data stream according to claim 53, further comprising: means for determining a group of tables related to the next state. 55. A packet classification state machine for classifying data from a data stream according to claim 53, further comprising: means for determining alignment of tables related to the next state.