JP2003332585A - Liquid crystal panel, electronic equipment, tft array substrate, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a thin film transistor in a pixel section from exerting an influence even when potential at a light shielding layer fluctuates. <P>SOLUTION: A TFT array substrate (10) is provided with a light shielding layer (11a) disposed to face a TFT (30), a light shielding wiring section (11b) connected to the layer (11a), and constant-potential wiring (6b) formed on the wiring section (11b) through an insulating film. The substrate (10) is also provided with a contact hole (5b) which electrically connects the light shielding wiring section (11b) and the constant-potential wiring (6b) to each other. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technical field of a liquid crystal panel of an active matrix driving system driven by a thin film transistor (hereinafter referred to as a TFT), an electronic device, a TFT array substrate and a manufacturing method thereof, and particularly, a liquid crystal projector and the like. The present invention belongs to the technical field of a liquid crystal panel in which a light-shielding layer is provided below a TFT and an electronic device using the same.

[0002]

2. Description of the Related Art Conventionally, when this type of liquid crystal panel is used as a light valve in a liquid crystal projector or the like, generally, projection light is incident from the side of a counter substrate which is arranged to face a TFT array substrate with a liquid crystal layer interposed therebetween. It Here, the projected light is a-Si (amorphous silicon) film of TFT or p-
When incident on a channel forming region made of a Si (polysilicon) film, a photocurrent is generated in this region due to a photoelectric conversion effect, and the transistor characteristics of the TFT deteriorate. For this reason, it is general that a light-shielding layer called a second light-shielding layer is formed of a metal material such as Cr (chrome) or resin black at a position facing each TFT on the counter substrate.

Further, in this type of liquid crystal panel, particularly, a positive stagger type or coplanar type amorphous silicon or poly that adopts a top gate structure (that is, a structure in which a gate electrode is provided above a channel on a TFT array substrate) is adopted. When using a silicon TFT, it is necessary to prevent a part of the projected light from entering the channel of the TFT from the side of the TFT array substrate as return light by the projection optical system in the liquid crystal projector. Similarly, when the projection light passes through the projection optical system after being reflected from the surface of the TFT array substrate, or when it is emitted from another liquid crystal panel when a plurality of liquid crystal panels for color is used in combination. It is also necessary to prevent part of the incoming projection light from entering the TFT channel from the TFT array substrate side as return light. Therefore, in JP-A-9-127497, JP-B-3-52611, JP-A-3-125123, and JP-A-8-171101, a TFT is formed on a TFT array substrate made of a quartz substrate or the like. Also proposed is a liquid crystal panel in which a light-shielding layer is formed of, for example, an opaque refractory metal also at a facing position (that is, below the TFT).

When the light-shielding layer is provided below the TFT in this manner, the light-shielding layer and the TFT are electrically insulated from each other, and the interlayer insulation is provided on the light-shielding layer in order to prevent contamination of the TFT from the light-shielding layer. A layer is formed and a TFT is formed thereon. That is, if a light shielding layer is provided below the TFT,
Along with this, an interlayer insulating layer between the light shielding layer and the TFT becomes an essential component.

[0005]

In the liquid crystal panel, there is a strong demand for improvement in image quality as well as improvement in production efficiency and reduction in production cost.

However, there is a possibility that the fluctuation in the potential of the light-shielding layer facing the thin film transistor in the pixel portion may have an adverse effect.

The present invention has been made in view of the above-mentioned problems, and an object thereof is to prevent the thin film transistor in the pixel portion from being influenced by the potential fluctuation of the light shielding layer.

[0008]

In order to solve the above-mentioned problems, a TFT array substrate of the present invention is connected to a light-shielding layer provided on the substrate and arranged to face a thin film transistor of a pixel portion, and the light-shielding layer. A light shielding wiring portion; a constant potential wiring formed above the light shielding wiring portion via an insulating film; and a contact hole electrically connecting the light shielding wiring portion and the constant potential wiring. Characterize.

Further, in the TFT array substrate of the present invention, an end portion of the light shielding layer of the pixel portion extends to a peripheral parting region that defines an image display region, and the light shielding layer and the light shielding wiring are provided in the peripheral parting region. It is good if the department is connected.

Further, the TFT array substrate of the present invention may have a plurality of light shielding layers in the pixel portion, and each light shielding layer may be connected to the light shielding wiring portion.

Further, the TFT array substrate of the present invention has a peripheral partition for defining an image display area formed in the same layer as the light shielding layer in the pixel section, and the light shielding layer and the light shielding wiring section are the peripheral partition. Good to be connected to.

Further, in the TFT array substrate of the present invention, it is preferable that the light shielding layer in the pixel portion is arranged so as to overlap with the capacitance line and the data line.

Further, in the TFT array substrate of the present invention, the light shielding layer in the pixel portion may be arranged along the scanning line or the data line.

Further, the liquid crystal panel of the present invention has the above-mentioned TF.
It is characterized by comprising a T array substrate, a counter substrate facing the TFT array substrate, and a liquid crystal sealed between the TFT array substrate and the counter substrate.

An electronic device of the present invention is characterized by including the above liquid crystal panel.

In the method of manufacturing a TFT array substrate of the present invention, a step of forming a light shielding wiring portion on the substrate, a step of forming an insulating layer on the light shielding wiring portion, and a part of the light shielding wiring portion. A step of forming a contact hole in the insulating layer and removing the insulating film, and forming a constant potential line in the insulating layer and the contact hole on the light shielding wiring part to electrically connect the light shielding wiring and the constant potential line. And a step of forming an insulating layer on the light-shielding wiring portion and an insulating layer on the constant potential line. Further, in the method of manufacturing the TFT array substrate of the present invention, the constant potential line may be formed in the same layer as the data line.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Structure and Operation of Liquid Crystal Panel) Regarding structure and operation of the embodiment of the liquid crystal panel according to the present invention, FIG.
From now on, it will be explained based on FIG.

First, the basic structure of the liquid crystal panel will be described with reference to FIGS. FIG. 1 is a plan view of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, light shielding layers, etc. are formed. FIG. 2 is a plan view of a connecting portion between the light shielding layer and the constant potential line. Figure 3
FIG. 4 is a cross-sectional view of an embodiment of a liquid crystal panel showing an AA ′ cross section along with a counter substrate and the like, and FIG. 4 is a cross-sectional view of a modification of the liquid crystal panel of FIG. 3. FIG. 5 is a cross-sectional view of a liquid crystal panel showing the BB ′ cross section of FIG. 1 together with a counter substrate,
FIG. 6 is a cross-sectional view of a liquid crystal panel showing a cross section CC ′ of FIG. 1 together with a counter substrate and the like. Further, FIG. 7 shows DD ′ of FIG.
FIG. 3 is a cross-sectional view of a liquid crystal panel showing a cross section together with a counter substrate and the like. 3 to 7, the scales of the layers and members are different from each other in order to make the layers and members recognizable in the drawings.

In FIG. 1, a plurality of transparent pixel electrodes 9a are arranged in a matrix on the TFT array substrate of the liquid crystal panel.
(The outline is indicated by a dotted line portion 9a '), and the data line 6a (source electrode), the scanning line 3a (gate electrode), and the capacitance line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. It is provided. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film through the contact hole 5a, and the pixel electrode 9a is later described through the contact hole 8 of the semiconductor layer 1a. Is electrically connected to the drain region of the. Further, a scanning line 3a (gate electrode) is arranged so as to face a channel forming region 1a ′ (a region of a diagonal line descending to the right in the drawing) of the semiconductor layer 1a, which will be described later. Then, the light shielding layer 11a in the pixel portion is provided in the region shown by the diagonal lines rising to the right in the drawing. That is, the light shielding layer 11a is
In the pixel portion, the channel forming region 1 of the semiconductor layer 1a
The TFT including a ', the data line 6a, the scanning line 3a, and the capacitance line 3b are provided at positions overlapping with each other when viewed from the TFT array substrate side.

In particular, in FIG. 1, in a mesh-like (matrix-like) region surrounded by thick lines including the data lines 6a, the scanning lines 3a and the capacitance lines 3b, the first interlayer insulating layer described later is recessed. Pixel electrode 9 that is formed and is otherwise formed
In a region substantially corresponding to a, the first interlayer insulating layer is formed to be relatively convex (planar).

In FIG. 2, on the TFT array substrate of the liquid crystal panel, a constant potential line 6b formed of a conductive layer such as Al, which is the same as the data line 6a, is provided, and in the non-pixel portion through the contact hole 5b. Shading layer (shading wiring) 1
It is connected to 1b. In particular, in FIG. 2, in a region surrounded by a thick line including the contact hole 5b, a later-described first interlayer insulating layer is recessed and formed, and in other regions, the first interlayer insulating layer is formed. It is formed to be relatively convex (planar).

As shown in FIGS. 3 to 6, the liquid crystal panel 1
00 includes a TFT array substrate 10 that constitutes an example of one transparent substrate, and a counter substrate 20 that constitutes an example of the other transparent substrate that is arranged to face the TFT array substrate 10. TFT
The array substrate 10 is made of, for example, a quartz substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. TFT
The array substrate 10 is provided with the pixel electrodes 9a,
An alignment film 19 that has been subjected to a predetermined alignment process such as a rubbing process is provided on the upper side thereof. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (indium tin oxide film). The alignment film 19 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a common electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment treatment such as rubbing treatment is provided below the common electrode 21. There is. The common electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

As shown in FIG. 3, on the TFT array substrate 10, each pixel electrode 9 is provided at a position adjacent to each pixel electrode 9a.
A TFT 30 that controls switching of a is provided.

As shown in FIGS. 3 to 7, the counter substrate 20 further includes a second light-shielding layer 2 in an area other than the opening area of each pixel.
3 is provided. Therefore, the projected light does not irradiate the channel forming region 1a ′ and the LDD (Lightly Doped Drain) regions 1b and 1c of the semiconductor layer 1a of the TFT 30 from the counter substrate 20 side. Further, the second light shielding layer 23 is
It has functions of improving contrast and preventing color mixture of color materials.

A seal member 52, which will be described later, is provided between the TFT array substrate 10 and the counter substrate 20 which are arranged in this manner and are arranged so that the pixel electrode 9a and the common electrode 21 face each other.
Liquid crystal is enclosed in a space surrounded by (see FIGS. 8 and 9) to form a liquid crystal layer 50. The liquid crystal layer 50 is formed on the alignment film 19 in a state where the electric field from the pixel electrode 9a is not applied.
A predetermined orientation state is adopted by the elements 22 and 22. The liquid crystal layer 50 is
For example, it is composed of a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. The sealing material 52 is used for the two substrates 10 and 20.
Are adhesives made of, for example, a photo-curing resin or a thermosetting resin, for bonding them around them, and a spacer such as glass fiber or glass beads for mixing the distance between both substrates to a predetermined value is mixed. ing.

As shown in FIG. 3, the TFT array substrate 10 and each of the TFTs 30 are located at positions facing the TFTs 30, respectively.
Between, for example, WSi (tungsten silicide)
The respective light shielding layers 11a are provided. Shading layer 1
1a is Ti, C which is preferably an opaque refractory metal
It is composed of a simple metal, an alloy, a metal silicide or the like containing at least one of r, W, Ta, Mo and Pd. With such a material, the TFT is formed after the step of forming the light shielding layer 11a on the TFT array substrate 10.
By the high temperature treatment in the step of forming 30, the light shielding layer 11a
Can be prevented from being destroyed or melted. Light shielding layer 11a
Since it is formed, it is possible to prevent the return light or the like from the TFT array substrate 10 side from entering the channel forming region 1a ′ and the LDD regions 1b and 1c of the TFT 30 in advance. The characteristics of the TFT 30 do not deteriorate.

Further, a first interlayer insulating layer 12 'composed of the first insulating layer 12 and the second insulating layer 13 is provided between the light shielding layer 11a and the plurality of TFTs 30. The first interlayer insulating layer 12 ′ is the semiconductor layer 1 a that constitutes the TFT 30.
Is provided to electrically insulate from the light shielding layer 11a. Further, the first interlayer insulating layer 12 ′ is formed on the entire surface of the TFT array substrate 10, so that the TFT 30
Also has a function as a base film. That is, TFT
It has a function of preventing deterioration of the characteristics of the TFT 30 due to roughness of the surface of the array substrate 10 during polishing, stains remaining after cleaning, and the like.

In particular, as shown in FIGS. 3 to 7, the first interlayer insulating layer 12 ′ is the light shielding layer 1 on the TFT array substrate.
The region where 1a is formed is formed on the light shielding layer 11a, and the region where the light shielding layer 11a is not formed is provided on the TFT array substrate 10.
Then, a portion facing the TFT 30, the data line 6a, the scanning line 3a, and the capacitance line 3b is formed to be recessed when viewed from the counter substrate 20 side. In the present embodiment, in particular, the first interlayer insulating layer 12 ′ is composed of a single layer portion and a two layer portion, and the single layer portion of the second insulating layer 13 is a thin concave portion. The first and second insulating layers 12
The two-layer portions of Nos. 13 and 13 are thickened and are not concavely depressed. When the first interlayer insulating layer 12 ′ is formed in this manner, the layer thickness of the first interlayer insulating layer 12 ′ in the concavely depressed portion is relatively easily and surely set as the layer thickness of the second insulating layer 13. It can be controlled with high precision. Therefore, the layer thickness of the first interlayer insulating layer 12 ′ (that is, the layer thickness of the second insulating layer 13) in the recessed portion can be made extremely thin.

The first interlayer insulating layer 1 configured as described above
2'can electrically insulate the TFT 30 and the like from the light shielding layer 11a and prevent the light shielding layer 11a from contaminating the TFT 30 and the like. Here, in particular, the first interlayer insulating layer 1
In 2 ', since the portions facing the TFT 30, the data line 6a, the scanning line 3a, and the capacitance line 3b are formed in a concave shape, the first interlayer insulating layer is formed flat and formed thereon as in the conventional case. Compared with the case of forming these TFTs,
Depending on the depth of the recessed portion, the difference in the total layer thickness between the region where these TFTs and the like are formed and the region where these TFTs are not formed is reduced, and planarization in the pixel portion is promoted.

For example, if the depth of the recessed portion is set so that the difference in the total layer thickness becomes substantially zero, the subsequent flattening process can be omitted. Alternatively, if the depth of the concave portion is set so as to reduce the difference in the total layer thickness to some extent, the burden of the subsequent flattening process can be reduced. More preferably, the first interlayer insulating layer 12 ′ is the light shielding layer 11a, the semiconductor layer 1a, the capacitance line 3b, and the data line 3a.
Is formed in a concave shape with a depth corresponding to the total layer thickness.
By configuring the first interlayer insulating layer 12 ′ in this manner, the upper surface of the data line 6 a and the upper surface of the second interlayer insulating layer 4 adjacent to the data line 6 a can be substantially aligned with each other, and the pixel before the pixel electrode 9 a is formed. The flattening of the part is promoted. However, the first interlayer insulating layer 12 ′ may be formed in a concave shape with a depth corresponding to the total layer thickness of the light shielding layer 11 a, the semiconductor layer 1 a, and the capacitance line 3 b. If the first interlayer insulating layer 12 'is configured in this way, the upper surface of the second interlayer insulating layer 4 can be made substantially flat, and the flattening in the pixel portion before the pixel electrode 9a is formed is promoted.

As described above, since the predetermined region of the first interlayer insulating layer 12 ', which is required by providing the light shielding layer 11a, is concavely formed, according to the present embodiment, the above-mentioned conventional method is used. The steps such as spin coating of the flattening film, CMP treatment, and formation of the flattened insulating layer can be omitted or simplified.

As shown in FIG. 4, instead of the first interlayer insulating layer 12 'composed of two layers shown in FIG. 3, the first interlayer insulating layer 12 "may be composed of a single layer. Thus, it is not necessary to increase the number of layers as compared with the conventional case, if it is composed of a single layer. If controlled, the first interlayer insulating layer 12 ″ can be obtained.

Referring again to FIG. 3, the first interlayer insulating layer 12 '
Is a highly insulating glass such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphosilicate glass), or a silicon oxide film or a silicon nitride film. Become.

In the present embodiment, as shown in FIGS. 1 and 5, the high-concentration drain region 1e of the semiconductor layer 1a extends along the data line 6a, and the light-shielding layer 11a corresponds to the data line 6a. Since it is also provided below, the first storage capacitor electrode (polysilicon layer) extended along the data line 6a
A capacitance is formed between 1f and the light-shielding layer (third storage capacitance electrode) 11a via the second insulating layer 13. As a result, the storage capacity of the pixel electrode 9a can be increased by effectively utilizing the space below the opening area below the data line 6a. Further, a capacitance is formed between the capacitance line (second storage capacitance electrode) 3b and the first storage capacitance electrode 1f by using an insulating film formed in the same step as the gate insulating film 2 as a dielectric.
As a result, above and below the first storage capacitor electrode 1f,
Capacitance can be formed, and a storage capacitor can be effectively added in a limited area, so that the pixel size can be miniaturized. Alternatively, since a high aperture ratio can be realized, a bright liquid crystal panel can be provided.

In the present embodiment, as shown in FIGS. 1 and 6, the first interlayer insulating layer 12 'is also formed by recessing a portion facing the capacitance line (second storage capacitance electrode) 3b. Therefore, even if the capacitance line 3b is provided above the first interlayer insulating layer 12 ', it is possible to achieve flattening in the region where the capacitance line 3b is provided. The layer thickness of the first interlayer insulating layer 12 'in the portion facing the capacitance line 3b is extremely thin (for example, about 1000 to 2000 Å), and the light shielding layer (third storage capacitance electrode) 11a is formed. Is also provided under the capacitance line 3b, the light-shielding layer 11a and the high-concentration drain region 1e of the semiconductor layer 1a, which are opposed to each other via the second insulating layer 13, are extended without increasing the surface area of the capacitance line 3b. The storage capacitance 70 between the provided first storage capacitance electrode 1f can be increased. That is, the storage capacitance 70 of the pixel electrode 9a can be increased as a whole.
In this way, the storage capacity can be increased so as not to narrow the opening area of each pixel in a limited area of the screen display area, which is very advantageous. In addition, the capacitance line 3b
Alternatively, the storage capacitor may be formed between the scanning line 3a and the scanning line 3a in the preceding stage. Further, if a constant potential line that supplies a constant potential to the capacitance line 3b is connected to a constant potential source such as a negative power source or a positive power source of a peripheral drive circuit (a data line drive circuit, a scanning line drive circuit, etc., which will be described later), it can be externally connected. It is possible to omit the mounting terminal for inputting the signal and the signal wiring provided at the edge of the mounting terminal, which is very advantageous when the liquid crystal panel is downsized.

In this embodiment, as shown in FIGS. 2 and 7, the light shielding layer 11b in the light shielding wiring portion (and the light shielding layer 11a in the pixel portion connected thereto) is electrically connected to the constant potential line 6b. Therefore, the light shielding layer 11a has a constant potential.
Therefore, the potential variation of the light shielding layer 11a does not adversely affect the TFT 30 arranged so as to face the light shielding layer 11a. In this case, the constant potential of the constant potential line 6b may be equal to the ground potential or the common electrode 21. Further, the constant potential line 6b may be connected to a constant potential source such as a negative power source or a positive power source of a peripheral driving circuit for driving the liquid crystal panel 100. Further, there is no problem even if the light shielding layer 11b and the above-mentioned capacitance line 3b are electrically connected. In this case, since the constant potential line can be shared, the signal wiring can be reduced, the space can be effectively used, and it is very advantageous when the liquid crystal panel is downsized.

Further, as shown in FIGS. 2 and 7, the first interlayer insulating layer 12 'is formed in a concave shape at the position where the light shielding layer 11b and the constant potential line 6b are connected, and therefore will be described later. As described above, the process of opening the contact hole 5b by etching after forming the first interlayer insulating layer 12 'is facilitated depending on the depth of the recessed portion, and the contact holes 5a and 5b are collectively opened. You can make holes. Therefore, it is possible to omit the step for forming the contact hole 5b, so that it is possible to reduce the cost and improve the yield by reducing the number of steps.

Referring again to FIG. 3, the TFT 30 is an LD
A channel forming region 1 of the semiconductor layer 1a having a D (Lightly Doped Drain) structure and in which a channel is formed by an electric field from the scanning line 3a (gate electrode) and the scanning line 3a.
a ′, the gate insulating layer 2 for insulating the scanning line 3a from the semiconductor layer 1a, and the low-concentration source region of the semiconductor layer 1a (source side L
DD region) 1b, data line 6a (source electrode), low-concentration drain region of semiconductor layer 1a (drain side LDD region)
1c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
A corresponding one of the plurality of pixel electrodes 9a is connected to e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e have a predetermined concentration of an n-type or p-type dopant depending on whether an n-type or p-type channel is formed in the semiconductor layer 1a. It is formed by doping. The n-type channel TFT has an advantage of high operation speed and is often used as the TFT 30 which is a pixel switching element. In the present embodiment, especially the data line 6a (source electrode) is composed of a light-shielding thin film such as a metal film of Al or the like or an alloy film of metal silicide or the like. Further, on the scanning line 3a (gate electrode), the gate insulating layer 2 and the first interlayer insulating layer 12 ', the contact hole 5 leading to the high concentration source region 1d.
The second interlayer insulating layer 4 in which the contact holes 8 leading to a and the high-concentration drain region 1e are respectively formed is formed. The data line 6a (source electrode) is electrically connected to the high-concentration source region 1d through the contact hole 5a to the source region 1b. Further, a contact hole 8 to the high-concentration drain region 1e is formed on the data line 6a (source electrode) and the second interlayer insulating layer 4 to form a third hole.
The interlayer insulating layer 7 is formed. Through the contact hole 8 to the high concentration drain region 1e, the pixel electrode 9a
Are electrically connected to the high concentration drain region 1e. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating layer 7 thus configured.

The TFT 30 is preferably L as described above.
Although it has a DD structure, it may have an offset structure in which the low-concentration source region 1b and the low-concentration drain region 1c are not implanted with the impurity ions. Alternatively, the gate electrode 3a is used as a mask for implanting the impurity ions at a high concentration to perform self-alignment. It may be a self-aligned type TFT that forms the high-concentration source region 1d and the drain region 1e. Further, as shown in FIG. 3, in the present embodiment, two gate electrodes to which the same scanning signal is supplied between the high concentration source region 1d and the high concentration drain region 1b of the TFT 30 via the gate insulating film 2. 3a may be provided to form a dual-gate (double-gate) structure TFT. As a result, the TFT3
The leak current of 0 can be reduced. If the dual-gate TFT has the above-mentioned LDD structure or offset structure, the leak current of the TFT 30 can be further reduced and a high contrast ratio can be realized. Further, due to the dual gate structure, redundancy can be provided, pixel defects can be significantly reduced, and image quality with a high contrast ratio can be realized because the leak current is low even during high temperature operation. Needless to say, the number of gate electrodes 3a provided between the high concentration source region 1d and the high concentration drain region 1b of the TFT 30 may be three or more.

Here, in general, the polysilicon layer such as the channel forming region of the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c is photocurrent due to the photoelectric conversion effect of polysilicon when light is incident. However, in this embodiment, the data line 6a (source electrode) is made of a light-shielding metal thin film such as Al so as to cover the scanning line 3a (gate electrode) from the upper side. Since it is formed, at least the channel forming region 1a ′ of the semiconductor layer 1a and the LDD region 1 are formed.
It is possible to effectively prevent the incident of the projected light (that is, the light from the upper side in FIG. 3) on b and 1c. Also, as mentioned above,
Since the light shielding layer 11a is provided below the TFT 30, at least the channel forming region 1 of the semiconductor layer 1a is formed.
a ′ and returning light to the LDD regions 1b and 1c (ie, FIG.
It is possible to effectively prevent the incidence of light from below).

Further, as shown in FIG. 6, each pixel electrode 9a is provided with a storage capacitor 70. This storage capacity 70
More specifically, the first storage capacitor electrode 1 formed of the polysilicon film formed in the same step as the semiconductor layer 1a and extending from the high-concentration drain region 1e of the semiconductor layer 1a.
f, an insulating layer 2 ′ formed via the gate insulating layer 2, a capacitance line 3b (second storage capacitance electrode) formed in the same step as the scanning line 3a (gate electrode), second and third interlayer insulating layers 4 and 7, and a part of the pixel electrode 9a facing the capacitance line 3b via the second and third interlayer insulating layers 4 and 7. Since the storage capacitor 70 is provided in this way, the duty ratio is small, and high-definition display without flicker is possible. As shown in FIG. 1, the capacitance line 3b (second storage capacitance electrode) is provided in parallel with the scanning line 3a (gate electrode) on the surface of the TFT array substrate 10. Furthermore, in the present embodiment, the first storage capacitor electrode 1
Since the first interlayer insulating layer 12 'under f can be thinned, the storage capacitance can be increased and a liquid crystal panel with high image quality can be realized.

By the way, in the present embodiment, the first interlayer insulating layer in the formation region including all of the semiconductor layer 1a, the data line 6a, the scanning line 3a and the capacitance line 3b shown in FIG. 1 is thinned. When it is considered that the signal delay of the signal or the scanning signal becomes an unacceptable level or the transistor characteristics of the pixel switching TFT 30 are affected, the semiconductor layer 1a, the data line 6a, the scanning line 3a, and the capacitance line 1a. The first interlayer insulating layer in at least one region of 3b may be thinned.

The liquid crystal panel 100 configured as described above
The overall configuration of will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan view of the TFT array substrate 10 together with the constituent elements formed thereon, as viewed from the counter substrate 20 side.
FIG. 9 is a sectional view taken along the line HH ′ of FIG. 8 including the counter substrate 20.

In FIG. 8, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof,
A light-blocking peripheral parting 53 made of the same material as or different from the second light-blocking layer 23 such as a black matrix is provided in parallel with the inside. The data line driving circuit 101 and the mounting terminal 10 are provided in the area outside the sealing material 52.
2 is provided along one side of the TFT array substrate 10, and the scanning line driving circuit 104 is provided along two sides adjacent to this one side. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for electrically connecting the scanning line driving circuits 104 provided on both sides of the screen display area are provided. The TFT array substrate 1 is provided at least at one corner of the counter substrate 20.
There is provided a silver dot 106 made of a conductive material for establishing electrical conduction between 0 and the counter substrate 20. And in FIG.
8, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is fixed to the array substrate 10.

The data line driving circuit 101 and the scanning line driving circuit 104 are electrically connected to the data line 6a (source electrode) and the scanning line 3a (gate electrode) by wiring. An image signal converted into a format that can be displayed immediately is input to the data line driving circuit 101 from a control circuit (not shown), and the scanning line driving circuit 104 sends a gate voltage to the scanning lines 3a in sequence in a pulsed manner. Then, the data line driving circuit 101 sends a signal voltage corresponding to the image signal to the data line 6a (source electrode). In the present embodiment, in particular, the TFT 30
Is a p-Si (polysilicon) type TFT, it is possible to form the data line driving circuit 101 and the scanning line driving circuit 104 in the same step when forming the TFT 30, which is advantageous in manufacturing.

FIG. 10 shows a two-dimensional layout on the TFT array substrate 100 of the light shielding layer 11b forming the light shielding wiring portion.

As shown in FIG. 10, the light-shielding layer 11a includes the scanning lines 3a in the screen display area within the peripheral parting 53.
Capacitance lines 3b and data lines 6a (not shown) are routed so as to overlap with each other, and are routed outside the screen display area so as to pass below the peripheral partition 53 on the counter substrate 20,
It is connected to the constant potential line as shown in FIG. With such wiring, the dead space under the peripheral partition 53 can be effectively used, and the area for curing the sealing material can be increased. In addition, the peripheral parting 53 provided on the counter substrate 20 is provided on the TFT array substrate 10 as the light shielding layer 11a.
The same material is provided in the same layer as, and electrically connected to the light shielding layers 11a and 11b. In this way, the peripheral closure 53
Since the second light-shielding layer on the counter substrate 20 is not necessary by incorporating the above, the precision at the time of bonding the TF array substrate 10 and the counter substrate 20 can be neglected, and a bright liquid crystal device in which the transmittance does not vary can be obtained. realizable. Further, the light shielding layer 11a may be arranged only along the scanning line 3a below the light shielding layer 11a, or may be arranged only below the light shielding layer 11a along the data line 6a. Light-shielding layer 11 described above
The method of arranging a is selected in consideration of the layer thickness of the step portion and the yield. In addition, in FIG. 8 to FIG.
On the FT array substrate 10, a precharge circuit that supplies a precharge signal of a predetermined voltage level to the plurality of data lines 6a prior to the image signal, respectively, and an image signal is sampled and supplied to the plurality of data lines 6a. It is also possible to form a sampling circuit, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipping. In addition, the data line driving circuit 101 and the scanning line driving circuit 104
Instead of being provided on the TFT array substrate 10, a driving LSI mounted on, for example, a TAB (tape automated bonding substrate) is provided with an anisotropic conductive film provided on the periphery of the TFT array substrate 10. You may make it connect electrically and mechanically.

Although not shown in FIGS. 1 to 10, the side of the counter substrate 20 on which the projected light is incident and the side of the TFT array substrate 10 on which the emitted light is emitted are, for example, T 1 respectively.
Depending on the operating mode such as N (twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, normally white mode / normally black mode, a polarizing film,
A retardation film, a polarizing plate, etc. are arranged in a predetermined direction.

Next, the operation of the present embodiment configured as described above will be described with reference to FIGS. 3 and 8 to 10.

First, the data line drive circuit 101 which receives the image signal from the control circuit supplies the signal voltage to the data line 6a (source electrode) at the timing and magnitude corresponding to the image signal.
To the scanning line driving circuit 104 in parallel with this.
The gate voltage is sequentially applied in a pulsed manner to the scanning line 3a (gate electrode) at a predetermined timing to drive the TFT 30.
As a result, in the TFT 30 to which the source voltage is applied when the gate voltage is turned on, the source regions 1d and 1b of the semiconductor layer 1a, the channel formed in the channel forming region 1a ′ and the drain regions 1c and 1e are formed. A voltage is applied to the pixel electrode 9a via the pixel electrode 9a. Then, the voltage of the pixel electrode 9a is held by the storage capacitor 70 (see FIG. 6) for a time that is, for example, three digits longer than the time when the source voltage is applied.

As described above, when the voltage is applied to the pixel electrode 9a, the alignment state of the liquid crystal in the portion of the liquid crystal layer 50 sandwiched between the pixel electrode 9a and the common electrode 21 changes, and the normally white mode is obtained. If so, the projection light cannot pass through this liquid crystal portion depending on the applied voltage, and in the normally black mode, the projection light can pass through this liquid crystal portion depending on the applied voltage. As a whole, the liquid crystal panel 100 emits light having a contrast corresponding to the image signal.

In particular, in this embodiment, the TFT 30 is excellent in light-shielding property, and the adverse effect of returning light is reduced, so that the transistor characteristics of the TFT 30 are improved, and the first interlayer insulating layer 12 ′ has the TFT 30. Since the liquid crystal panel 100 is formed in a concave shape at a position facing each other and various wirings, the alignment failure of the liquid crystal is reduced, and finally, the liquid crystal panel 100 can display a high-contrast and high-quality image. It will be possible.

Since the liquid crystal panel 100 described above is applied to a color liquid crystal projector, the three liquid crystal panels 100 are respectively used as light valves for RGB,
The light of each color separated through the dichroic mirror for RGB color separation is incident on each panel as projection light. Therefore, in each of the embodiments, the counter substrate 20 is not provided with a color filter. However, also in the liquid crystal panel 100, an RGB color filter is provided in a predetermined region facing the pixel electrode 9a where the black matrix 23 is not formed, together with its protective film,
It may be formed on the counter substrate 20. If you do this,
The liquid crystal panel of this embodiment can be applied to a color liquid crystal device such as a direct-view type or a reflection type color liquid crystal television other than the liquid crystal projector. Further, microlenses may be formed on the counter substrate 20 so as to correspond to each pixel. By doing so, a bright liquid crystal panel can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that creates RGB colors may be formed by utilizing interference of light by depositing a number of interference layers having different refractive indexes on the counter substrate 20. This counter substrate with a dichroic filter can realize a brighter color liquid crystal panel.

In the liquid crystal panel 100, the projection light is made incident from the counter substrate 20 side as in the conventional case, but since the light shielding layer 11a is present, the projection light is made incident from the TFT array substrate 10 side and opposed. The light may be emitted from the substrate 20 side. That is, even when the liquid crystal panel 100 is attached to the liquid crystal projector in this way, it is possible to prevent light from entering the channel forming region 1a ′ and the LDD regions 1b and 1c of the semiconductor layer 1a, and display a high quality image. It is possible to Here, conventionally, in order to prevent reflection on the back surface side of the TFT array substrate 10, it is necessary to separately dispose a polarizing plate coated with an AR film for antireflection or to attach an AR film. However, in the present embodiment, the surface of the TFT array substrate 10, at least the channel forming region 1a ′ of the semiconductor layer 1a and the LDD region 1b,
Since the light-shielding layer 11a is formed between 1c and 1c, it is not necessary to use such an AR-coated polarizing plate or AR film or to use the substrate obtained by AR-treating the TFT array substrate 10 itself. Therefore, according to this embodiment, the material cost can be reduced, and the yield is not lowered due to dust, scratches, etc. when the polarizing plate is attached, which is very advantageous. Further, since the light resistance is excellent, even if the light utilization efficiency is improved by using a bright light source or polarization conversion by the polarization beam splitter, image deterioration such as crosstalk due to light does not occur.

In the liquid crystal panel 100, a flattening film may be further applied on the third interlayer insulating layer 7 by spin coating or the like in order to further suppress the alignment failure of the liquid crystal molecules on the TFT array substrate 10 side. Or, CMP treatment may be performed. Alternatively, the third interlayer insulating layer 7 may be formed of a flattening film. In the present embodiment, as shown in FIGS. 3 to 7, the TF is formed by the concave depression of the first interlayer insulating layer 12 ′.
Since the T30 and the portion where various wirings are formed and the portion other than that have almost the same height, such a flattening process is generally unnecessary, but in order to display a higher quality image, This embodiment is very advantageous because even if the uppermost layer is further flattened, the flattening film can be made very thin or only a small amount of flattening treatment is required.

The switching element of the liquid crystal panel 100 is a positive stagger type or coplanar type polysilicon TF.
Although described as T, this embodiment is also effective for other types of TFTs such as an inverted stagger type TFT and an amorphous silicon TFT.

Further, in the liquid crystal panel 100, the liquid crystal layer 50 is made of nematic liquid crystal as an example.
The use of the polymer-dispersed liquid crystal in which the liquid crystal is dispersed as fine particles in the polymer eliminates the need for the alignment films 19 and 22, the polarizing film, the polarizing plate, and the like, and improves the light utilization efficiency of the liquid crystal panel. The advantages of higher brightness and lower power consumption can be obtained. Further, when the liquid crystal panel 10 is applied to a reflective liquid crystal device by forming the pixel electrode 9a from a metal film having a high reflectance such as Al, the SH in which liquid crystal molecules are substantially vertically aligned in the absence of applied voltage is applied. A (super homeotropic) type liquid crystal or the like may be used. Furthermore, in the liquid crystal panel 100, the common electrode 21 is provided on the counter substrate 20 side so as to apply an electric field (vertical electric field) perpendicular to the liquid crystal layer 50. Each of the pixel electrodes 9a is composed of a pair of electrodes for horizontal electric field generation so as to apply an electric field (that is, without providing electrodes for vertical electric field generation on the counter substrate 20 side, the TFT array substrate 10 side). It is also possible to provide an electrode for generating a lateral electric field). The use of the horizontal electric field in this manner is advantageous in widening the viewing angle as compared with the case of using the vertical electric field. Other,
This embodiment can be applied to various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.

(Manufacturing Process) Next, a manufacturing process of the liquid crystal panel 100 having the above-described structure will be described with reference to FIG.
From now on, it will be described with reference to FIG. 11 to 14
Shows each layer on the side of the TFT array substrate in each step as shown in FIG.
FIG. 15 is a process diagram corresponding to a section taken along the line AA, and FIGS. 15 to 18 are process diagrams illustrating each layer on the TFT array substrate side in each process corresponding to a line BB ′ in FIG.
9 to 22 are process diagrams showing each layer on the TFT array substrate side in each process in correspondence with the CC ′ cross section of FIG. 6, and FIGS. 23 to 26 show each layer on the TFT array substrate side in each process. It is a process drawing shown corresponding to the DD 'section of 7. The steps (1) to (20) described in each figure are collectively performed as the same step in different parts on the TFT array substrate 1.

First, referring to FIG. 11 to FIG.
A manufacturing process of a portion including the TFT 30 corresponding to the AA ′ cross section will be described.

As shown in step (1) of FIG. 11, a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, preferably, annealing treatment is performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pretreatment is performed so that distortion occurring in the TFT array substrate 10 in a high temperature process performed later is reduced. I'll do it. That is, the TFT array substrate 10 is preliminarily heat-treated at the same temperature or higher in accordance with the highest temperature of the manufacturing process.

The TFT array substrate 1 thus processed
A metal film such as a metal such as Ti, Cr, W, Ta, Mo and Pd or a metal alloy film such as a metal silicide is sputtered on the entire surface of 0 to form a light-shielding film having a layer thickness of about 1000 to 3000Å, preferably about 2000Å. 11 is formed.

Subsequently, as shown in step (2), a resist mask corresponding to the pattern of the light shielding layer 11a is formed on the formed light shielding film 11 by photolithography,
By etching the light shielding film 11 through the resist mask, the light shielding layer 11a is formed.

Next, as shown in step (3), the light shielding layer 11
On top of a, for example, TE by normal pressure or low pressure CVD method or the like.
OS (tetra-ethyl-ortho-silicate) gas, T
EB (Tetra-Ethyl-Borate) gas, TMOP
Using a (tetra-methyl-oxy-foslate) gas or the like, the first insulating layer 12 (two first layers) made of a silicate glass film such as NSG, PSG, BSG or BPSG, a silicon nitride film or a silicon oxide film is used. A lower layer of the interlayer insulating layer 12 'is formed. The layer thickness of the first insulating layer 12 is, eg, about 8000 to 12000Å.

Next, as shown in step (4), the TFT 3
The regions where 0, the data lines 6a, the scanning lines 3a, and the capacitance lines 3b are to be formed above are etched to remove the first insulating layer 12 in these regions. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed with substantially the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to the dimensions. On the other hand, when at least wet etching is used, the opening area of the first interlayer insulating layer 12 expands because of the isotropic property, but the side wall surface of the opening can be formed in a tapered shape, so that, for example, in a later step, for example, scanning. The polysilicon film and the resist for forming the line 3a do not remain around the sidewall of the opening without being etched or peeled off, and the yield is not reduced. As a method of forming the side wall surface of the opening portion of the first interlayer insulating layer 12 in a tapered shape, dry etching is performed once, and then the resist pattern is retracted,
Dry etching may be performed again.

Next, as shown in step (5), the light shielding layer 11
On the a and the first insulating layer 12, a second insulating layer 13 (two first interlayer insulating layers 12) made of a silicate glass film, a silicon nitride film, a silicon oxide film, or the like, is formed similarly to the first insulating layer 12. 'Upper layer). The layer thickness of the second insulating layer 13 is, for example, about 1000 to 2000Å. Second
The insulating layer 13 may be annealed at about 900 ° C. to prevent contamination and flatten it.

Particularly in this embodiment, the layer thicknesses of the first insulating layer 12 and the second insulating layer 13 forming the first interlayer insulating layer are as follows.
The pixel region is set to be substantially flat before the pixel electrode 9a is formed later.

Next, as shown in the step (6), the temperature is about 450 to 550 ° C., preferably about 500, on the second insulating layer 13.
Flow rate of about 400-600cc /
An amorphous silicon film is formed by low pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using min monosilane gas or disilane gas. Then, in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours,
Preferably, the polysilicon film 1 is solid-phase grown to a thickness of about 500 to 2000 Å, preferably about 1000 Å, by performing an annealing treatment for 4 to 6 hours. At this time, when the n-channel type TFT 30 is produced, a dopant of a group V element such as Sb (antimony), As (arsenic) and P (phosphorus) is slightly doped by ion implantation or the like. When the TFT 30 is a p-channel type, B (boron), Ga (gallium), In
A dopant of Group III element such as (indium) is slightly doped by ion implantation or the like. The polysilicon film 1 may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, the polysilicon film 1 may be formed by implanting silicon ions into the polysilicon film deposited by the low pressure CVD method to once make it amorphous and then recrystallizing it by annealing or the like.

Next, as shown in step (7) of FIG. 12, a photolithography step, an etching step, etc.
The semiconductor layer 1a having a predetermined pattern as shown in 1 is formed.

Next, as shown in step (8), the semiconductor layer 1
a at a temperature of about 900 to 1300 ° C., preferably about 100
A thermal oxide film with a relatively thin thickness of about 300Å is formed by thermal oxidation at a temperature of 0 ° C, and a high temperature silicon oxide film (HTO film) or nitride film with a relative thickness of about 500Å is formed by a low pressure CVD method. The gate insulating layer 2 having a multi-layered structure is formed by depositing it to a small thickness. As a result, the semiconductor layer 1a has a thickness of about 300 to 1500Å, preferably about 35.
The thickness of the gate insulating layer 2 becomes 0 to 500Å
Thickness of about 200-1500Å, preferably about 300-1
The thickness is 000Å. By shortening the high temperature thermal oxidation time in this way, it is possible to prevent warpage due to heat, particularly when a large substrate of about 8 inches is used. However, the gate insulating layer 2 having a single layer structure may be formed only by thermally oxidizing the polysilicon layer 1.

Next, as shown in step (9), low pressure CVD
After depositing the polysilicon layer 3 by a method such as phosphorus (P)
Are thermally diffused to render the polysilicon film 3 conductive. Or P
A doped silicon film in which ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. As shown in step (10), the scanning line 3a (gate electrode) having a predetermined pattern as shown in FIG. 1 is formed by a photolithography process using a mask, an etching process, and the like. The layer thickness of the scanning line 3a (gate electrode) is, for example, about 3500Å.

However, the scanning line 3a (gate electrode) may be formed of a refractory metal film such as W (tungsten) or Mo (molybdenum) or a metal silicide film instead of the polysilicon layer, or these. The metal film or the metal silicide film and the polysilicon film may be combined to form a multi-layer. In this case, if the scanning line 3a (gate electrode) is arranged as a light-shielding film corresponding to a part or the whole of the region covered by the second light-shielding layer 23, the second light-shielding property is provided by the light-shielding property of the metal film or the metal silicide film. It is also possible to omit part or all of the layer 23. In this case, in particular, there is an advantage that it is possible to prevent a decrease in the pixel aperture ratio due to the misalignment between the opposing substrate 20 and the TFT array substrate 10.

Next, as shown in step (11), the TFT 3
When 0 is an n-channel TFT having an LDD structure, the low concentration source region 1b is first formed in the p-type semiconductor layer 1a.
In order to form the low-concentration drain region 1c, the scanning line 3a (gate electrode) is used as a diffusion mask, and the dopant 200 of the group V element such as P is low in concentration (for example, P ions are 1 to 3 × 10 ¹³ / Doping (with a dose of cm ² ). As a result, the semiconductor layer 1a under the scanning line 3a (gate electrode) becomes the channel forming region 1a '.

Subsequently, as shown in the step (12) of FIG. 13, the high concentration source region 1b and the high concentration drain region 1c.
To form the resist layer 202 on the scanning line 3a (gate electrode) with a mask wider than the scanning line 3a (gate electrode), a high concentration of a V-group element dopant 201 such as P is also formed. (For example, P ion of 1 to 3 ×
Dope (with a dose of 10 ¹⁵ / cm ² ). Also, T
When the FT 30 is a p-channel type, the n-type semiconductor layer 1
a, a low concentration source region 1b and a low concentration drain region 1
In order to form c and the high-concentration source region 1d and the high-concentration drain region 1e, doping is performed using a Group III element dopant such as B. When the LDD structure is used as described above, there is an advantage that the short channel effect can be reduced. Note that, for example, a TFT having an offset structure may be used without performing low-concentration doping, and a self-aligned TFT is formed by an ion implantation technique using P ions, B ions, etc., using the scanning line 3a (gate electrode) as a mask. May be

In parallel with these steps, an n-channel type polysilicon TFT and a p-channel type polysilicon TFT are provided.
The data line driving circuit 101 and the scanning line driving circuit 104 having a CMOS (complementary MOS) structure
It is formed on the periphery of the T array substrate 10. in this way,
Since the TFT 30 is a polysilicon TFT, the TFT 3
The data line driving circuit 101 and the scanning line driving circuit 104 can be formed in the same step when 0 is formed, which is advantageous in manufacturing.

Next, as shown in step (13), the scan line 3
To cover a (gate electrode), for example, NSG, PSG, or a normal pressure or low pressure CVD method or TEOS gas is used.
A second interlayer insulating layer 4 made of a silicate glass film such as BSG or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The layer thickness of the second interlayer insulating layer 4 is about 5000 to 1
5000Å is preferable.

Next, as shown in step (14), after annealing for about 20 minutes at about 1000 ° C. for activating the high concentration source region 1d and the high concentration drain region 1e, the data line 31 (source The contact hole 5a for the electrode) is formed by dry etching such as reactive etching or reactive ion beam etching. At this time, the contact hole 5 is formed by anisotropic etching such as reactive etching or reactive ion beam etching.
Opening a has the advantage that the opening shape can be made substantially the same as the mask shape. However, by combining dry etching and wet etching to open the holes, the contact hole 5a can be tapered, and therefore, there is an advantage that disconnection at the time of wiring connection can be prevented. Further, a contact hole for connecting the scanning line 3a (gate electrode) to a wiring (not shown) is also formed in the second interlayer insulating layer 4 in the same process as the contact hole 5a.

Next, as shown in step (15), a low resistance metal such as Al having a light shielding property or a metal silicide is formed as a metal film 6 on the second interlayer insulating layer 4 by a sputtering process or the like to form about 1,000. ~ 5000Å thickness, preferably about 3
Then, as shown in step (16), the data line 6a (source electrode) is formed by a photolithography step, an etching step, and the like.

Next, as shown in step (17) of FIG.
To cover the data line 6a (source electrode), for example,
NS using normal pressure or low pressure CVD method or TEOS gas
A third interlayer insulating layer 7 made of a silicate glass film such as G, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The layer thickness of the third interlayer insulating layer 7 is preferably about 5000 to 15000Å.

In the present embodiment, the first interlayer insulating layer is recessed and formed in the TFT 30 and various wiring portions by the steps (4) and (5) of FIG. The surface of the pixel region becomes substantially flat when (4) is finished. In order to make the surface flatter, instead of or on the silicate glass film forming the third interlayer insulating layer 7, an organic film or SOG (spin-on glass) is spin-coated, or CMP treatment is performed. Alternatively, a flat film may be formed.

Next, as shown in step (18), the contact hole 8 for electrically connecting the pixel electrode 9a and the high-concentration drain region 1e is formed by dry etching such as reactive etching or reactive ion beam etching. Form. At this time, when the contact hole 8 is opened by anisotropic etching such as reactive etching or reactive ion beam etching, there is an advantage that the opening shape can be made substantially the same as the mask shape. However, if the dry etching and the wet etching are combined to form the holes, the contact holes 8 can be formed in a tapered shape, so that there is an advantage that disconnection at the time of wiring connection can be prevented.

Next, as shown in step (19), ITO is formed on the third interlayer insulating layer 7 by sputtering or the like.
A transparent conductive thin film 9 such as a film is deposited to a thickness of about 500 to 2000Å, and as shown in step (20), a pixel electrode 9 is formed by a photolithography step, an etching step, and the like.
a is formed. When the liquid crystal panel 100 is used in a reflective liquid crystal device, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid of a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, as shown in FIG. The alignment film 19 is formed.

On the other hand, for the counter substrate 20 shown in FIG. 3, a glass substrate, a quartz substrate, or the like is first prepared, and the second light shielding layer 23 and the light shielding peripheral partition 53 are formed by sputtering metal chromium, for example, and Lithography process,
It is formed through an etching process. The second light shielding layer 23
The peripheral partition 53 may be formed of a metal material such as Cr, Ni or Al, or a material such as resin black in which carbon or Ti is dispersed in a photoresist.

Thereafter, a transparent conductive thin film of ITO or the like is formed on the entire surface of the counter substrate 20 by sputtering or the like to a thickness of about 5 nm.
The common electrode 21 is formed by depositing to a thickness of 00 to 2000Å. Further, the alignment film 22 is formed by applying a polyimide-based alignment film coating liquid on the entire surface of the common electrode 21 and then performing a rubbing treatment in a predetermined direction so as to have a predetermined pretilt angle.

Finally, the T on which each layer was formed as described above.
The FT array substrate 10 and the counter substrate 20 are pasted together with a sealing material 52 so that the alignment films 19 and 22 face each other, and by vacuum suction or the like, for example, a plurality of types of nematic liquid crystals are mixed in the space between the substrates. The resulting liquid crystal is sucked to form a liquid crystal layer 50 having a predetermined layer thickness.

Next, referring to FIG. 15 to FIG.
The manufacturing process of the portion including the data line corresponding to the BB ′ cross section will be described.

Step (1) in FIG. 15 to step (2) in FIG.
0) is performed as the same manufacturing process as the step (1) of FIG. 11 to the step (20) of FIG. 14 described above.

That is, as shown in step (1) of FIG.
After forming the light shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), the light shielding layer 11a is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
a on the first insulating layer 12 (two first interlayer insulating layer 1
2 ′ (lower layer) is formed, and as shown in step (4), the region where the data line 6a is to be formed above is etched to remove the first insulating layer 12 in this region. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed with substantially the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to the dimensions. On the other hand, when at least wet etching is used, the opening region of the first interlayer insulating layer 12 expands because of the isotropic property, but the side wall surface of the opening can be formed in a tapered shape, so that, for example, in the case of a post-process, for example, the capacitance is increased. The polysilicon film or resist for forming the line 3b does not remain around the sidewall of the opening without being etched or peeled off, and the yield is not reduced. As a method of forming the side wall surface of the opening portion of the first interlayer insulating layer 12 in a tapered shape, it is possible to perform dry etching once, then retreat the resist pattern, and perform dry etching again.

Next, as shown in step (5), the light shielding layer 1
A second insulating layer 13 (an upper layer of the two first interlayer insulating layers 12 ′) is formed on the la and the first insulating layer 12.

Next, as shown in step (6), after forming an amorphous silicon film on the second insulating layer 13, the polysilicon film 1 is solid-phase grown.

Next, as shown in step (7) of FIG. 16, a photolithography step, an etching step, etc.
The semiconductor layer 1a having a predetermined pattern as shown in 1 is formed.

Next, as shown in step (8), the gate insulating layer 2 is formed by thermally oxidizing the first storage capacitor electrode 1f.
To form. Although not particularly limited, the first storage capacitor electrode 1
For e ′, for example, P ions are dosed at about 3 × 10 ¹² / cm 3.
^It may be doped with ² to reduce the resistance. The semiconductor layer 1a made of the polysilicon film 1 is extended to form the first storage capacitor electrode 15. Further, as shown in step (9), a polysilicon layer 3 is deposited thereon, and then, as shown in step (10), a predetermined pattern as shown in FIG. 1 is formed by a photolithography step, an etching step and the like. The capacitance line 3b is formed from the same layer as the scanning line 3a. Therefore, the capacitance line 3b
The layer thickness of is similar to that of the scanning line 3a (gate electrode) and is, for example, about 3500Å.

Next, as shown in step (11) of FIG. 16 and step (12) of FIG. 17, impurity ions 200 and 201
To further reduce the resistance of the capacitance line 3b.

Next, as shown in step (13), the capacitance line 3
The second interlayer insulating layer 4 is formed so as to cover b, and the step (1
As shown in 4), a contact hole for connecting the capacitance line 3b to a wiring (not shown) is opened in the second interlayer insulating layer 4.

Next, as shown in step (15), Al or the like is deposited as a metal film 6 on the second interlayer insulating layer 4 by sputtering or the like, and then, as shown in step (16), The data line 6a (source electrode) is formed by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
A third interlayer insulating layer 7 is formed so as to cover the data line 6a (source electrode).

In the present embodiment, particularly in the data line 6a portion by the steps (4) and (5) of FIG.
Since the first interlayer insulating layer is recessed in a concave shape, the surface of the pixel region becomes substantially flat when this step (17) is finished.

Next, in step (18) of FIG. 18, after waiting for the contact hole 8 to be opened, an ITO film or the like is formed on the third interlayer insulating layer 7 as shown in step (19). A transparent conductive thin film is deposited, and as shown in step (20), a pixel electrode 9a is formed by a photolithography process, an etching process and the like.

Next, referring to FIG. 19 to FIG. 22, FIG.
The manufacturing process of the portion including the scanning line and the capacitance line corresponding to the CC ′ cross section will be described.

The process (1) shown in FIG. 19 to the process (2) shown in FIG.
0) is performed as the same manufacturing process as the step (1) of FIG. 11 to the step (20) of FIG. 14 described above.

That is, as shown in step (1) of FIG.
After forming the light shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), the light shielding layer 11a is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
a on the first insulating layer 12 (two first interlayer insulating layer 1
2 ′) (lower layer), and as shown in step (4), the region where the scanning line 3a and the capacitance line 3b are to be formed above is etched to remove the first insulating layer 12 in this region. Remove. Here, when the etching is performed by dry etching such as reactive etching or reactive ion beam etching, the first insulating layer 12 can be anisotropically removed with substantially the same size as the resist mask formed by photolithography. There is an advantage that it can be easily controlled according to the dimensions. On the other hand, when at least wet etching is used, the opening region of the first interlayer insulating layer 12 expands because of the isotropic property, but the side wall surface of the opening can be formed in a tapered shape, so that, for example, in the case of a post-process, for example, the capacitance is increased. The polysilicon film or resist for forming the line 3b does not remain around the sidewall of the opening without being etched or peeled off, and the yield is not reduced. The first interlayer insulating layer 1
As a method of forming the side wall surface of the second opening in a tapered shape, dry etching may be performed once after the etching is performed once by dry etching.

Next, as shown in step (5), the light shielding layer 1
A second insulating layer 13 (an upper layer of the two first interlayer insulating layers 12 ′) is formed on the la and the first insulating layer 12.

Next, as shown in step (6), after forming an amorphous silicon film on the second insulating layer 13, the polysilicon film 1 is solid-phase grown.

Next, as shown in the step (7) of FIG. 20, a photolithography step, an etching step, etc.
The semiconductor layer 1a made of the polysilicon film 1 having a predetermined pattern as shown in FIG. 2 is extended to form the first storage capacitor electrode 1f.

Next, as shown in step (8), the gate insulating layer 2 is formed by thermally oxidizing the first storage capacitor electrode 1f.
1 is formed, and a polysilicon layer 3 is further deposited thereon as shown in step (9), and then, as shown in step (10), a photolithography step, an etching step, etc. are performed, as shown in FIG. The scanning line 3a and the capacitance line 3b having a predetermined pattern are formed.

Next, as shown in step (11) of FIG. 20 and step (12) of FIG. 21, impurity ions 200 and 201 are used.
To further reduce the resistance of the scanning line 3a and the capacitance line 3b.

Next, as shown in the step (13), the scanning line 3
The second interlayer insulating layer 4 is formed so as to cover a and the capacitance line 3b, and as shown in step (14), a second contact hole for connecting the scanning line 3a and the capacitance line 3b to a wiring not shown is formed. A hole is opened in the interlayer insulating layer 4.

Next, as shown in step (15), after depositing Al or the like as the metal film 6 on the second interlayer insulating layer 4 by sputtering or the like, as shown in step (16), The data line 6a (source electrode) that does not exist on the cross section is formed by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
The third interlayer insulating layer 7 is formed so as to cover the second interlayer insulating layer 4.

In the present embodiment, the first interlayer insulating layer is concavely formed in the scanning line 3a and the capacitor line 3b by the steps (4) and (5) in FIG. The surface of the pixel region becomes substantially flat when step (17) is completed.

Next, in step (18) of FIG. 22, after waiting for the contact hole 8 to be opened, an ITO film or the like is formed on the third interlayer insulating layer 7 as shown in step (19). A transparent conductive thin film 9 is deposited, and as shown in step (20), a pixel electrode 9a is formed by a photolithography step, an etching step, and the like.

Next, referring to FIGS. 23 to 26, FIG.
A manufacturing process of a portion including a connection portion between the light-shielding layer and the constant potential line corresponding to the DD ′ cross section will be described.

Steps (1) in FIG. 23 to steps (2) in FIG.
0) is performed as the same manufacturing process as the step (1) of FIG. 11 to the step (20) of FIG. 14 described above.

That is, as shown in step (1) of FIG.
After forming the light shielding film 11 on the entire surface of the TFT array substrate 10, as shown in step (2), the light shielding layer 11b is formed by a photolithography step, an etching step, or the like.

Next, as shown in step (3), the light shielding layer 11
b on the first insulating layer 12 (two first interlayer insulating layer 1
2'underlayer), and as shown in step (4), the region where the connection portion is to be formed above is etched to remove the first insulating layer 12 in this region, and then the process is performed. As shown in (5), the second insulating layer 13 (the upper layer of the two first interlayer insulating layers 12 ′) is formed on the light shielding layer 11b and the first insulating layer 12.

Next, as shown in step (6), after forming an amorphous silicon film on the second insulating layer 13, the polysilicon film 1 is solid-phase grown.

Next, in steps (7) and (8) of FIG.
The formation of the semiconductor layer 1a and the gate insulating layer 2 in the pixel portion is waited, and then, as shown in step (9), the polysilicon layer 3 is once deposited, and then, as shown in step (10), at this connection portion, The polysilicon layer 3 is entirely removed.

Then, as shown in step (11) of FIG. 20 and step (12) of FIG. 21, the doping of the impurity ions 200 and 201 for the semiconductor layer 1a is completed.

Next, as shown in step (13), the second interlayer insulating layer 4 is formed so as to cover the first insulating layer 13, and as shown in step (14), the light shielding layer 11b and the constant potential line. A contact hole 5b for connecting with 6b is opened in the second interlayer insulating layer 4. At this time, since only the second insulating layer 13 of the first interlayer insulating layer 12 ′ is formed under the second interlayer insulating layer 4, the high-concentration source region 1d of the semiconductor layer 1a is formed.
The second interlayer insulating layer 4 is opened above and the contact hole 5 is formed.
The holes can be opened at once by the same etching step as the step of forming a (step (14) in FIG. 13).

Next, as shown in step (15), after depositing Al or the like as the metal film 6 on the second interlayer insulating layer 4 by sputtering or the like, as shown in step (16), The constant potential line 6b is formed from the same layer (Al or the like) as the data line by a lithography process, an etching process, or the like.

Next, as shown in step (17) of FIG.
Third interlayer insulating layer 7 is formed so as to cover constant potential line 6b and second interlayer insulating layer 4.

Next, in step (18) of FIG. 26, after waiting for the contact hole 8 to be opened, an ITO film or the like is formed on the third interlayer insulating layer 7 as shown in step (19). The transparent conductive thin film 9 is once deposited, and as shown in step (20), this portion is entirely removed by a photolithography step, an etching step, and the like.

As described above, according to the liquid crystal panel manufacturing method of the present embodiment, the light shielding layer 11b and the constant potential line 6b are provided.
The second interlayer insulating layer 4 and the first insulating layer 1 are formed as contact holes 5b for connecting to the light shielding layer 11b.
3 (upper layer of the first interlayer insulating layer) is opened, and at the same time, TF
As the contact hole 5a for connecting T30 and the data line 6a, the second interlayer insulating layer 4 is opened up to the semiconductor layer 1a. Therefore, these two types of contact holes 5a and 5b can be collectively opened, which is advantageous in manufacturing. For example, by wet etching with the selection ratio set to an appropriate value, it becomes possible to collectively open such two types of contact holes 5a and 5b so as to each have a predetermined depth. In particular, the step of opening these contact holes is facilitated depending on the depth of the recessed portion of the first interlayer insulating layer. Since the contact hole opening process (photolithography process, etching process, etc.) for connecting the light-shielding layer and the constant potential line can be eliminated, the manufacturing cost and the yield do not increase due to the increase in the process.

As described above, according to the manufacturing process of this embodiment, the first concave portion is
By controlling the layer thickness of the second insulating layer 13, the layer thickness of the interlayer insulating layer 12 ′ can be controlled relatively easily, reliably, and highly accurately. Therefore, it is possible to make the layer thickness of the first interlayer insulating layer 12 ′ in the recessed portion very thin.

Incidentally, as shown in FIG. 4, when the first interlayer insulating layer 12 ″ is composed of a single layer, as shown in FIGS.
The steps (3), (4) and (5) shown in FIGS. 19 and 23, respectively, are slightly modified, and the steps (1) to (20) are performed.
Should be done. That is, in the step (3), the light shielding layer 11
On the a, a first interlayer insulating layer 12 ″ having a slightly thicker thickness, for example, about 10,000 to 15,000 Å is deposited, and in the step (4), the TFT 30, the data line 6 a,
The region where the scan line 3a and the capacitance line 3b are to be formed above is etched to leave the first interlayer insulating layer 12 ″ in this region with a thickness of about 1000 to 2000 Å. 5) is omitted. In this case as well, the layer thickness of the non-etched portion of the first interlayer insulating layer 12 ″ and the layer thickness of the etched portion are such that the pixel region is substantially flat before the pixel electrode 9a is formed later. Is set to. If the first interlayer insulating layer 12 ″ is composed of a single layer as described above, it is not necessary to increase the number of layers as compared with the conventional case, and the layer thickness between the recessed portion and the other portion can be reduced. It is convenient to control it by controlling the etching time because it can achieve flattening.

(Electronic Device) Next, an embodiment of an electronic device including the liquid crystal panel 100 described in detail above will be described with reference to FIGS. 27 to 31.

First, FIG. 27 shows the liquid crystal panel 10 as described above.
1 shows a schematic configuration of an electronic device including 0.

In FIG. 27, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, and a drive circuit 1.
004, liquid crystal panel 100, clock generation circuit 1008
In addition, the power supply circuit 1010 is provided. The display information output source 1000 is a ROM (Read Only Memory),
A RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like are included, and display information such as an image signal of a predetermined format is displayed based on a clock signal from a clock generation circuit 1008. It is output to the information processing circuit 1002. The display information processing circuit 1002 is configured to include various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. Digital signals are sequentially generated from the information and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal panel 100. The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The drive circuit 1004 may be mounted on the TFT array substrate that constitutes the liquid crystal panel 100,
In addition to this, the display information processing circuit 1002 may be mounted.

Next, FIG. 28 to FIG. 31 show specific examples of the electronic apparatus configured as described above.

In FIG. 28, a liquid crystal projector 1100, which is an example of an electronic device, is provided with three liquid crystal display modules including the liquid crystal panel 100 in which the above-mentioned drive circuit 1004 is mounted on the TFT array substrate. It is configured as a projector used as the valves 100R, 100G, and 100B. In the liquid crystal projector 1100, when the projection light is emitted from the lamp unit 1102 which is a white light source such as a metal halide lamp, 3
One mirror 1106 and two dichroic mirrors 1
108, the light components R corresponding to the three primary colors of RGB,
Light valve 100 divided into G and B and corresponding to each color
R, 100G and 100B respectively. At this time, in particular, the B light is incident lens 1122, relay lens 1123 and emission lens 11 in order to prevent light loss due to a long optical path.
It is guided through a relay lens system 1121 composed of 24. And the light valves 100R, 100G and 10
The light components corresponding to the three primary colors modulated by 0B are
After being combined again by the dichroic prism 1112, they are projected as a color image on the screen 1120 via the projection lens 1114.

In this embodiment, in particular, since the light shielding layer is also provided on the lower side of the TFT, the reflected light and the projected light by the projection optical system in the liquid crystal projector based on the projected light from the liquid crystal panel 100 pass through. The reflected light from the surface of the TFT array substrate at the time of moving, a part of the projected light (a part of the R light and the G light) that passes through the dichroic prism 1112 after being emitted from another liquid crystal panel, is returned as TF.
Even when the light is incident from the T array substrate side, it is possible to sufficiently shield the channel region of the pixel electrode switching TFT or the like. Therefore, even if a prism suitable for miniaturization is used in the projection optical system, an AR film for preventing return light is attached between the TFT array substrate of each liquid crystal panel and the prism, or an AR film treatment is performed on the polarizing plate. Since it is not necessary to provide the above, it is very advantageous in downsizing and simplifying the configuration.

In FIG. 29, a laptop personal computer (PC) 1200 for multimedia, which is another example of an electronic apparatus, is the above-mentioned liquid crystal panel 100.
Is included in the top cover case, and CP
A keyboard 12 for accommodating U, memory, modem, etc.
The main body 1204 in which 02 is incorporated is provided.

In FIG. 30, another example of a pager 1300 of an electronic apparatus is a backlight 1306a in which a liquid crystal panel 100 which is a liquid crystal display module in which the above-mentioned drive circuit 1004 is mounted on a TFT array substrate in a metal frame 1302. Light guide 1306 including a circuit board 1
308, first and second shield plates 1310 and 131
It is housed with two, two elastic conductors 1314 and 1316, and a film carrier tape 1318.
In the case of this example, the display information processing circuit 1002 (see FIG.
7) may be mounted on the circuit board 1308 or may be mounted on the TFT array substrate of the liquid crystal panel 100.
Further, the above-mentioned drive circuit 1004 can be mounted on the circuit board 1308.

Since the example shown in FIG. 30 is a pager, a circuit board 1308 and the like are provided. However, the drive circuit 1004 and further the display information processing circuit 1002
Liquid crystal panel 100 which is equipped with a liquid crystal display module to form a liquid crystal display module
In the case of, the liquid crystal panel 10 is placed in the metal frame 1302.
It is also possible to produce, sell, or use a liquid crystal device in which 0 is fixed or a backlight liquid crystal device in which a light guide 1306 is incorporated in addition to the liquid crystal device.

Further, as shown in FIG. 31, the drive circuit 100
4 and the liquid crystal panel 100 without the display information processing circuit 1002, the IC 1324 including the driving circuit 1004 and the display information processing circuit 1002 is the polyimide tape 13
TCP (Tape Carrier Package) mounted on 22
It is also possible to physically and electrically connect to 1320 via an anisotropic conductive film provided in the peripheral portion of the TFT array substrate 10 to produce, sell, or use as a liquid crystal device.

In addition to the electronic devices described with reference to FIGS. 28 to 31, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic notebook, a calculator, a word processor, an engineering A workstation (EWS), a mobile phone, a videophone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic device shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices including the liquid crystal panel 100 which has high manufacturing efficiency and is capable of displaying high-quality images.

Hereinafter, the contents of the present invention will be described as supplementary notes.

In the liquid crystal panel described in appendix 1, liquid crystal is sealed between a pair of substrates, and a plurality of data lines and a plurality of data lines intersecting the plurality of data lines are provided on one substrate of the pair of substrates. Scanning lines, a plurality of thin film transistors connected to the plurality of data lines and scanning lines, a plurality of thin film transistors connected to the plurality of thin film transistors, and a concave shape when viewed from the other substrate side of the pair of substrates. A first interlayer insulating film having a recessed portion, and at least a part of the thin film transistor, the data line, and the scanning line is formed in the recessed portion.

According to the liquid crystal panel described in appendix 1, the first
Since the portion of the interlayer insulating layer facing at least one of the TFT, the data line, and the scanning line is formed as a recess when viewed from the other substrate side, the first interlayer insulating layer is formed as in the conventional case. Compared to the case where these TFTs, etc. are formed flat and formed on top of them, the total of the area where these TFTs etc. are formed and the area where they are not formed, depending on the depth of the recessed portion. The difference in layer thickness is reduced, and planarization in the pixel portion is promoted. For example, if the depth of the recessed portion is set so that the difference in the total layer thickness is substantially zero, the subsequent flattening process can be omitted, or the difference in the total layer thickness can be reduced to some extent. If the depth of the recessed portion is set so as to decrease as much as possible, the burden of the subsequent flattening process can be reduced. That is, it is possible to omit or simplify the above-described conventional processes such as spin coating of a planarizing film and formation of a planarized insulating layer.

In the liquid crystal panel described in appendix 2, a liquid crystal is sealed between a pair of substrates, and a plurality of data lines and a plurality of data lines intersecting the plurality of data lines are provided on one substrate of the pair of substrates. Scanning lines, a plurality of thin film transistors connected to the plurality of data lines and scanning lines, a plurality of pixel electrodes connected to the plurality of thin film transistors, at least a channel forming region of the plurality of thin film transistors of the one The thin film transistor, the data line, and the light-shielding layer that are provided at positions respectively covering when viewed from the substrate side, and the first interlayer insulating film that has a recessed portion formed on the light-shielding layer. At least a part of the scanning lines is formed in a concave shape on the part.

According to the liquid crystal panel described in appendix 2, the light shielding layer is provided on one of the substrates at a position that covers at least the channel forming regions of the plurality of TFTs when viewed from the side of the one substrate. Therefore, it is possible to prevent the return light or the like from one of the substrates from entering the channel forming region, and it is possible to prevent the characteristics of the TFT from deteriorating due to the generation of photocurrent. The first interlayer insulating layer is provided on the light shielding layer in the region where the light shielding layer is formed on one substrate, and is provided on the one substrate in the region where the light shielding layer is not formed. ing.
Therefore, it is possible to electrically insulate the TFT and the like from the light shielding layer and prevent the light shielding layer from contaminating the TFT and the like. Here, in particular, since the portion of the first interlayer insulating layer that faces at least one of the TFT, the data line, and the scanning line is formed in a concave shape when viewed from the side of the other substrate, as in the conventional case. Compared with the case where the first interlayer insulating layer is formed flat and these TFTs and the like are formed thereon, the area where these TFTs and the like are formed is formed in accordance with the depth of the recessed portion. The difference in the total layer thickness from the unfilled region is reduced, and the flattening in the pixel portion is promoted. For example, if the depth of the recessed portion is set so that the difference in the total layer thickness is substantially zero, the subsequent flattening process can be omitted,
Alternatively, if the depth of the concave portion is set so as to reduce the difference in the total layer thickness to some extent, the burden of the subsequent flattening process can be reduced. That is, the conventional
The steps such as spin-coating the flattening film and forming the flattened insulating layer can be omitted or simplified.

The liquid crystal panel described in appendix 3 is characterized in that, in order to solve the above problems, the liquid crystal panel described in appendix 1 or 2 is characterized in that the first interlayer insulating layer is composed of a single layer.

According to the liquid crystal panel described in appendix 3, the first
Since the interlayer insulating layer may be composed of a single layer, it is not necessary to increase the number of layers as compared with the conventional case, and by controlling the layer thickness between the recessed portion and the other portion, A first interlayer insulating layer is obtained.

The liquid crystal panel described in appendix 4 is the same as in appendix 1 or 2.
In the liquid crystal panel according to [1], the first interlayer insulating layer is
It is composed of a single-layer portion and a multi-layer portion, and the single-layer portion is a recessed portion, and the multi-layer portion is a portion that is not recessed.

According to the liquid crystal panel described in appendix 4, since the single layer portion is a recessed portion, the layer thickness of the first interlayer insulating layer in the recessed portion is set to the layer thickness of the single layer portion. The thickness can be controlled relatively easily, reliably and with high precision. Therefore, the layer thickness of the first interlayer insulating layer in the recessed portion can be made extremely thin.

In order to solve the above problems, the liquid crystal panel described in appendix 5 is the liquid crystal panel described in any one of appendices 1 to 4, wherein the one substrate is provided in parallel with the plurality of scanning lines. And further comprising a plurality of capacitance lines that respectively apply a predetermined capacitance to the plurality of pixel electrodes, and the first interlayer insulating layer is formed such that the portion facing the capacitance lines is also recessed in the concave shape. Characterize.

According to the liquid crystal panel described in appendix 5, the first
Since the interlayer insulating layer is also formed by recessing the portion facing the capacitance line in a concave shape, even when the capacitance line is wired above the first interlayer insulating layer, the flatness in the region where the capacitance line is wired is achieved. Can be promoted. Then, the layer thickness of the first interlayer insulating layer in the portion facing the capacitance line can be made extremely thin.

In order to solve the above-mentioned problems, the liquid crystal panel described in appendix 6 is the liquid crystal panel described in appendix 5, in which the light-shielding layer is formed even at a position where the capacitance line overlaps when viewed from the one substrate side. It is provided on one of the substrates.

According to the liquid crystal panel described in appendix 6, when the layer thickness of the first interlayer insulating layer in the portion facing the capacitance line is reduced, the light shielding layer overlaps the capacitance line when viewed from one substrate side. Since it is also provided on one of the substrates, it is possible to increase the capacitance between the light-shielding layer and the semiconductor layer forming the TFT, which are opposed to each other via the insulating layer, without increasing the surface area of the capacitance line. That is, the storage capacity of the pixel electrode can be increased as a whole.

In order to solve the above problems, the liquid crystal panel described in appendix 7 is the liquid crystal panel described in appendix 5 or 6, wherein the first interlayer insulating layer is the total of the light shielding layer, the semiconductor layer and the capacitance line. It is characterized in that it is formed so as to be recessed in a depth corresponding to the layer thickness.

According to the liquid crystal panel described in appendix 7, the first
Since the interlayer insulating layer is formed as a recess in a depth corresponding to the total layer thickness of the light shielding layer, the semiconductor layer of the TFT and the capacitance line, the region where these light shielding layers are formed and the other regions. The step difference between and can be reduced, and the flattening in the pixel portion is promoted.

In order to solve the above problems, the liquid crystal panel described in appendix 8 is the liquid crystal panel described in appendix 5 or 6, wherein the first interlayer insulating layer is the light shielding layer, the semiconductor layer, the capacitance line, and It is characterized in that it is formed in a concave shape with a depth corresponding to the total thickness of the data lines.

According to the liquid crystal panel described in appendix 8, the first
Since the interlayer insulating layer is formed in a concave shape with a depth corresponding to the total layer thickness of the light shielding layer, the semiconductor layer of the TFT, the capacitance line and the data line, the region where these light shielding layers and the like are formed and It is possible to reduce the step difference with the area other than
Flattening in the pixel portion is promoted.

The liquid crystal panel according to attachment 9 is the liquid crystal panel according to any one of attachments 1 to 8 in order to solve the above problems, in which the semiconductor layer forming the TFT extends along the data line. The light-shielding layer is provided on the one substrate even at a position where the data line overlaps the data line when viewed from the one substrate side.

According to the liquid crystal panel described in appendix 9, between the semiconductor layer extending along the data line and the light shielding layer provided at the position where the data line overlaps when viewed from the side of one substrate. A capacitor is formed via the first interlayer insulating layer. As a result, the storage capacity of the pixel electrode can be increased by effectively utilizing the space under the data line outside the opening region.

In order to solve the above-mentioned problems, the liquid crystal panel described in appendix 10 is the liquid crystal panel described in any one of appendices 1 to 8, in which the first interlayer insulating layer is formed of a silicon oxide film or a silicon nitride film. It is characterized by being configured.

According to the liquid crystal panel described in appendix 10, the eleventh insulating layer made of a silicon oxide film or a silicon nitride film can electrically insulate the TFT and the like from the light shielding layer and prevent contamination from the light shielding layer. Moreover, the first interlayer insulating layer having such a structure is suitable as a base layer of the TFT.

In order to solve the above problems, the liquid crystal panel described in appendix 11 is the liquid crystal panel described in any one of appendices 1 to 10, wherein the light shielding layer is Ti (titanium),
It is characterized by containing at least one of Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum) and Pd (lead).

According to the liquid crystal panel described in appendix 11, the light shielding layer is made of opaque refractory metals such as Ti, Cr, W and T.
Since it is composed of, for example, a metal simple substance, an alloy, a metal silicide, etc. containing at least one of a, Mo and Pd, it is possible to perform high temperature treatment in the TFT forming process after the light shielding layer forming process on the TFT array substrate. , It is possible to prevent the light shielding layer from being destroyed or melted.

The liquid crystal panel described in appendix 12 is the liquid crystal panel described in any one of appendices 1 to 11 in order to solve the above-mentioned problems, characterized in that the light shielding layer is connected to a constant potential source. And

According to the liquid crystal panel described in appendix 12, since the light shielding layer is connected to the constant potential source, the light shielding layer has a constant potential. Therefore, the potential fluctuation of the light-shielding layer does not adversely affect the TFT arranged opposite to the light-shielding layer.

In order to solve the above problems, the liquid crystal panel described in appendix 13 is the same as the liquid crystal panel described in appendix 12,
The first interlayer insulating layer is formed in the concave shape and has an opening at a position where the light shielding layer and the constant potential source are connected.

According to the liquid crystal panel described in appendix 13, the first interlayer insulating layer is formed in a concave shape at the position where the light shielding layer and the constant potential source are connected. After the formation of the first interlayer insulating layer, the step of forming a hole at this position is facilitated depending on the depth of the recessed portion.

The method of manufacturing a liquid crystal panel described in appendix 14 is the method of manufacturing a liquid crystal panel described in appendix 2 in order to solve the above problems, in which the light shielding layer is formed in a predetermined region on the one substrate. A step, a step of depositing an insulating layer on the one substrate and the light-shielding layer, a step of forming a resist pattern corresponding to the recessed portion in the insulating layer by photolithography, and the step of interposing the resist pattern And dry etching for a predetermined time to form the recessed portion.

According to the method of manufacturing a liquid crystal panel described in appendix 14, first, a light shielding layer is formed in a predetermined region on one substrate, and an insulating layer is deposited on the one substrate and this light shielding layer. Next, a resist pattern corresponding to the concavely depressed portion is formed on the insulating layer by photolithography, and then dry etching is performed for a predetermined time through the resist pattern to form the concavely depressed portion. It is formed. Therefore, the depth and layer thickness of the recessed portion can be controlled by controlling the dry etching time.

The method for producing a liquid crystal panel according to attachment 15 is the method for producing a liquid crystal panel according to attachment 3 in order to solve the above problems, in which the light shielding layer is formed in a predetermined region on the one substrate. A step, a step of depositing a first insulating layer on the one substrate and the light shielding layer, a step of forming a resist pattern corresponding to the recessed portion in the first insulating layer by photolithography, and the resist Etching through a pattern to remove the first insulating layer corresponding to the recessed portion; and a step of depositing a second insulating layer on the one substrate and the first insulating layer. It is characterized by

According to the method of manufacturing a liquid crystal panel described in appendix 15, first, a light shielding layer is formed in a predetermined region on one substrate, and a first insulating layer is deposited on the one substrate and this light shielding layer. . Next, a resist pattern corresponding to the concavely depressed portion is formed on the first insulating layer by photolithography, and then etching is performed through the resist pattern to correspond to the concavely depressed portion. The first insulating layer is removed. Then, a second insulating layer is deposited on the one substrate and the first insulating layer. As a result, the layer thickness of the first interlayer insulating layer in the recessed portion can be controlled relatively easily, reliably and highly accurately by controlling the layer thickness of the second insulating layer.

The liquid crystal panel manufacturing method described in appendix 16 is characterized in that at least dry etching is performed as the etching method in order to solve the above problems.

According to the method of manufacturing a liquid crystal panel described in appendix 16, since the etching is performed by at least dry etching, the insulating layer on the light shielding layer having no resist pattern can be anisotropically removed. As a result, it is possible to form a recessed portion with a high degree of accuracy as designed.

The liquid crystal panel manufacturing method described in appendix 17 is characterized by performing at least wet etching as the etching method in order to solve the above problems.

According to the method of manufacturing a liquid crystal panel described in appendix 17, since the etching is performed at least by wet etching, the side wall of the recessed concave portion formed in the insulating layer on the light shielding layer can be formed in a tapered shape. This makes it possible to easily and surely remove the wiring film and the resist that will be formed on the side wall portion in a later step. Therefore, an unnecessary film is not left and the yield is not reduced.

The method of manufacturing the liquid crystal panel described in appendix 18 is the method of manufacturing the liquid crystal panel described in appendix 12 in order to solve the above problem, wherein the light shielding layer is formed in a predetermined region on the one substrate. A step of forming the first interlayer insulating layer on the one substrate and the light shielding layer so that a portion facing the TFT and a portion corresponding to the connection position are recessed in the concave shape; T on the insulating layer
The step of forming an FT, the step of forming a second interlayer insulating layer on the TFT and the first interlayer insulating layer, and the step of forming a contact hole for connecting the light shielding layer and the wiring from the constant potential source, The second and first interlayer insulating layers are opened to reach the light-shielding layer at the connection position, and at the same time, the semiconductor layer forming the TFT is used as a contact hole for connecting the TFT and the data line. A step of forming a hole in the second interlayer insulating layer up to the semiconductor layer at a position facing the source or drain region.

According to the method of manufacturing a liquid crystal panel described in appendix 18, a light shielding layer is formed in a predetermined region on one substrate,
A first interlayer insulating layer is formed on one of the substrates and the light shielding layer such that a portion facing the TFT and a portion corresponding to a position where the light shielding layer and the constant potential source are connected are recessed. Then, a TFT is formed on the first interlayer insulating layer,
A second interlayer insulating layer is formed on the first interlayer insulating layer.
The second interlayer insulating layer is provided for electrical insulation of TFTs, data lines, scanning lines and the like. Here, as the contact holes for connecting the light shielding layer and the wiring from the constant potential source, the second and first interlayer insulating layers are opened up to the light shielding layer, and at the same time, the TFT and the data line are connected. The second interlayer insulating layer is opened as a contact hole for reaching the semiconductor layer. Therefore, these two types of contact holes can be collectively opened.

The electronic equipment described in appendix 19 is characterized by including the liquid crystal panel described in appendices 1 to 12 in order to solve the above problems.

According to the electronic device described in appendix 19, the electronic device includes the above-described liquid crystal panel of the present invention,
A liquid crystal panel capable of efficiently flattening the pixel portion enables high-quality image display.

[0182]

According to the present invention, the thin film transistor in the pixel portion is not affected by the potential fluctuation of the light shielding layer.

[Brief description of drawings]

FIG. 1 is a plan view of adjacent pixel groups on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light shielding layer, etc. are provided, which is included in an embodiment of a liquid crystal panel according to the present invention.

FIG. 2 is a TFT showing a connection portion between a light shielding layer and a constant potential line
It is a top view of an array substrate.

FIG. 3 is a cross-sectional view of an embodiment of a liquid crystal panel showing the AA ′ cross section of FIG. 1 together with a counter substrate and the like.

FIG. 4 is a cross-sectional view of a modification of the liquid crystal panel showing the cross section AA ′ of FIG. 1 together with a counter substrate and the like.

5 is a cross-sectional view of a liquid crystal panel showing a cross section taken along the line BB ′ of FIG. 1 together with a counter substrate and the like.

6 is a cross-sectional view of a liquid crystal panel showing a cross section CC ′ of FIG. 1 together with a counter substrate and the like.

FIG. 7 is a cross-sectional view of a liquid crystal panel showing a DD ′ cross section of FIG. 1 together with a counter substrate and the like.

FIG. 8 is a plan view showing an overall configuration of the liquid crystal device of FIG.

9 is a cross-sectional view showing the overall configuration of the liquid crystal device of FIG.

FIG. 10 is a plan view on a TFT array substrate showing a two-dimensional layout of a light shielding layer forming a light shielding wiring.

FIG. 11 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 3.

FIG. 12 is a process diagram (No. 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG.

FIG. 13 is a process diagram (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG.

FIG. 14 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG.

FIG. 15 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 5.

FIG. 16 is a process diagram (part 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel with respect to the portion shown in FIG. 5.

FIG. 17 is a process diagram (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG.

FIG. 18 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 5.

FIG. 19 is a process chart (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 6.

FIG. 20 is a process diagram (part 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 6.

FIG. 21 is a process chart (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel with respect to the portion shown in FIG. 6.

FIG. 22 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel with respect to the portion shown in FIG. 6.

FIG. 23 is a process diagram (1) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 7.

FIG. 24 is a process diagram (part 2) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel with respect to the portion shown in FIG. 7.

FIG. 25 is a process chart (No. 3) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel with respect to the portion shown in FIG. 7.

FIG. 26 is a process chart (No. 4) sequentially showing the manufacturing process of the embodiment of the liquid crystal panel for the portion shown in FIG. 7.

FIG. 27 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a liquid crystal projector as an example of an electronic device.

FIG. 29 is a front view showing a personal computer as another example of the electronic apparatus.

FIG. 30 is an exploded perspective view showing a pager as an example of an electronic device.

FIG. 31 is a perspective view showing a liquid crystal device using TCP as an example of an electronic device.

[Explanation of symbols]

1a ... semiconductor layer 1a '... Channel forming region 1b ... low-concentration source region (source-side LDD region) 1c ... Low concentration drain region (drain side LDD region) 1d ... High-concentration source region 1e ... high-concentration drain region 1f ... First storage capacitor electrode 2 ... Gate insulating film 3a ... Scan line (gate electrode) 3b ... Capacitance line (second storage capacity electrode) 4 ... Second interlayer insulating layer 5a, 5b ... Contact holes 6a ... Data line (source electrode) 6b ... Constant potential line 7 ... Third interlayer insulating layer 8 ... Contact hole 9a ... Pixel electrode 10 ... TFT array substrate 11a, 11b ... Shading layer (third storage capacitor electrode) 12 ... First insulating layer (lower layer of first interlayer insulating layer) 12 ', 12 "... First interlayer insulating layer 13 ... Second insulating layer (upper layer of first interlayer insulating layer) 19 ... Alignment film 20 ... Counter substrate 21 ... Common electrode 22 ... Alignment film 23 ... Second light shielding layer 30 ... TFT 50 ... Liquid crystal layer 52 ... Sealing material 53 ... Surrounding area 70 ... Storage capacity 100 ... Liquid crystal panel 101 ... Data line drive circuit 104 ... Scan line drive circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2H092 GA24 HA06 JA24 JB31 JB52                       JB53 NA11 PA09 RA05 RA10                 5F110 AA06 AA21 AA30 BB02 BB04                       CC02 CC05 CC07 DD02 DD03                       DD12 DD13 DD14 DD17 DD21                       DD25 EE04 EE05 EE09 EE28                       EE45 FF02 FF03 FF09 FF22                       FF32 GG02 GG13 GG15 GG25                       GG32 GG47 GG52 HJ01 HJ04                       HJ13 HJ23 HL03 HL05 HL07                       HL23 HM14 HM15 NN03 NN04                       NN22 NN23 NN24 NN25 NN26                       NN35 NN36 NN44 NN46 NN72                       NN73 PP01 PP13 PP33 QQ04                       QQ05 QQ11 QQ19

Claims (10)

[Claims] 1. A light-shielding layer provided on a substrate so as to face a thin film transistor of a pixel portion, a light-shielding wiring portion connected to the light-shielding layer, and formed above the light-shielding wiring portion with an insulating film interposed therebetween. A TF including a constant potential wiring and a contact hole electrically connecting the light shielding wiring portion and the constant potential wiring.
T array substrate. 2. An end portion of the light shielding layer of the pixel portion extends to a peripheral parting region that defines an image display region, and the light shielding layer and the light shielding wiring part are connected to each other in the peripheral parting region. The TFT array substrate according to claim 1, wherein: 3. The TFT array substrate according to claim 2, wherein the pixel portion has a plurality of light shielding layers, and each light shielding layer is connected to the light shielding wiring portion. 4. A peripheral parting line that defines an image display region formed in the same layer as the light shielding layer in the pixel part, and the light shielding layer and the light shielding wiring part are connected to the peripheral parting line. The TFT array substrate according to claim 1. 5. The TFT array substrate according to claim 1, wherein the light shielding layer in the pixel portion is arranged so as to overlap the capacitance line and the data line. 6. The TFT array substrate according to claim 1, wherein the light shielding layer in the pixel portion is arranged along a scanning line or a data line. 7. The TFT array substrate according to claim 1, a counter substrate facing the TFT array substrate, and a liquid crystal sealed between the TFT array substrate and the counter substrate. A liquid crystal panel characterized by comprising. 8. An electronic device comprising the liquid crystal panel according to claim 7. 9. A step of forming a light-shielding wiring portion on a substrate, a step of forming an insulating layer on the light-shielding wiring portion, and forming a contact hole in a part of the insulating layer on the light-shielding wiring portion to form the insulating layer. A step of removing the film; a step of forming a constant potential line in the insulating layer and the contact hole on the light shielding wiring portion to electrically connect the light shielding wiring and the constant potential line; and insulation on the light shielding wiring portion. Layer, and a step of forming an insulating layer on the constant potential line, the method of manufacturing a TFT array substrate. 10. The method for manufacturing a TFT array substrate according to claim 9, wherein the constant potential line is formed in the same layer as the data line.