JP2003332384A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2003332384A JP2003332384A JP2002136593A JP2002136593A JP2003332384A JP 2003332384 A JP2003332384 A JP 2003332384A JP 2002136593 A JP2002136593 A JP 2002136593A JP 2002136593 A JP2002136593 A JP 2002136593A JP 2003332384 A JP2003332384 A JP 2003332384A
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- semiconductor chip
- connection
- conductive particles
- chip
- electrode
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
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- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
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- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＩＣチップ上に
ＩＣチップをフェイスダウンで接合する半導体装置およ
びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an IC chip is joined face down on an IC chip and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来の異方性導電ペースト(以下、ＡＣ
Ｐと呼ぶ)を用いたチップオンチップ接続(以下、ＣＯＣ
接続と呼ぶ)のパッド部の形状と接続プロセスを図４、
図５、図６に基づいて説明する。2. Description of the Related Art Conventional anisotropic conductive paste (hereinafter referred to as AC
Chip-on-chip connection using P) (hereinafter COC)
The shape of the pad part (referred to as connection) and the connection process are shown in FIG.
This will be described with reference to FIGS. 5 and 6.
【０００３】図４は従来のＣＯＣ接続パッド部の平面及
び断面の概略図を表わしている。図５は従来のＣＯＣ接
続パッド部の形状において接続プロセスとＡＣＰ中の導
電性粒子の挙動を概略図で表わしている。図６は従来の
ＣＯＣ接続パッド部の形状でＡＣＰを用いてＣＯＣ接続
されたチップ接続部の断面の概略図を表わしている。FIG. 4 shows a schematic view of a plane and a cross section of a conventional COC connection pad portion. FIG. 5 schematically shows the connection process and the behavior of the conductive particles in the ACP in the shape of the conventional COC connection pad portion. FIG. 6 shows a schematic view of a cross section of a chip connecting portion which is COC-connected using ACP in the shape of a conventional COC connecting pad portion.
【０００４】図４、図５、図６の１は接続パッド、２は
Ｓｉチップ、３′は保護膜、４はＡＣＰ、５は導電性粒
子、６はバンプである。In FIGS. 4, 5, and 6, 1 is a connection pad, 2 is a Si chip, 3'is a protective film, 4 is ACP, 5 is conductive particles, and 6 is a bump.
【０００５】図４に示すように従来のＣＯＣ接続パッド
１は、複数個のＣＯＣ接続パッド１をひとまとめにして
接続のための開口部７を保護膜３′に形成していた。As shown in FIG. 4, in the conventional COC connection pad 1, a plurality of COC connection pads 1 are grouped together to form an opening 7 for connection in the protective film 3 '.
【０００６】上記のような従来のＣＯＣ接続パッド形状
において、ＡＣＰ４を用いたＣＯＣ接続を行った場合の
接続部の断面は図６の通りである。FIG. 6 shows a cross section of the connection portion when the COC connection using the ACP 4 is performed in the conventional COC connection pad shape as described above.
【０００７】図５に基づいて従来のＣＯＣ接続パッド形
状において、ＡＣＰ４を用いたＣＯＣ接続を行った場合
のプロセスと、ＡＣＰ４中の導電性粒子の挙動について
説明する。With reference to FIG. 5, a process in the case of performing COC connection using ACP4 in the conventional COC connection pad shape and the behavior of the conductive particles in ACP4 will be described.
【０００８】初めにＡＣＰ４を塗布装置によりＣＯＣ接
続パッド１が形成されたＳｉチップ２ａに塗布する（図
５（ａ））。次に、バンプ６が形成されたＳｉチップ２
ｂが、Ｓｉチップ２ａの所定の位置に位置合わせされ、
所定の荷重により接合される。この接合時に、ＡＣＰ４
は中心より外に向かって押し出され、同時にＡＣＰ４中
の導電性粒子も外に向かって移動する（図５（ｂ），
（ｃ））。First, ACP 4 is applied to the Si chip 2a on which the COC connection pad 1 is formed by using a coating device (FIG. 5 (a)). Next, the Si chip 2 on which the bumps 6 are formed
b is aligned with a predetermined position of the Si chip 2a,
It is joined by a predetermined load. At the time of this joining, ACP4
Is pushed outward from the center, and at the same time, the conductive particles in ACP4 also move outward (FIG. 5 (b),
(C)).
【０００９】接続パッド１の開口部７をＡＣＰ４が通過
するとき、ＡＣＰ４中の導電性粒子５の一部が開口部７
の段差により接続パッド１の周辺にとどまる。最後に、
接続パッド１とバンプ６の間に導電性粒子５が挟みこま
れて接続が完了する（図６）。When the ACP 4 passes through the opening 7 of the connection pad 1, a part of the conductive particles 5 in the ACP 4 is opened.
Stays around the connection pad 1 due to the step. Finally,
The conductive particles 5 are sandwiched between the connection pad 1 and the bump 6 to complete the connection (FIG. 6).
【００１０】ＣＯＣ接続パッド１とバンプ６の間に挟み
こまれる導電性粒子５の数は図６に示すように数個程度
であり、存在しない場合もあり、接続不良や接続信頼性
低下の原因となる。さらに今後の高周波化・高密度化に
伴い接続抵抗の安定化が課題となる。The number of the conductive particles 5 sandwiched between the COC connection pad 1 and the bump 6 is about several as shown in FIG. 6, and they may not be present. Becomes In addition, the stabilization of connection resistance will become an issue with higher frequencies and higher densities in the future.
【００１１】[0011]
【発明が解決しようとする課題】上記従来の従来のＡＣ
Ｐを用いたＣＯＣ接続においては、安定して接続をする
ためには、ＣＯＣ接続パッド１とバンプ６の面積を大き
くし接続パッド１とバンプ６の間に存在する導電性粒子
５の数を増やす、または、ＡＣＰ４に含まれる導電性粒
子５を増やす必要がある。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Conventional AC described above
In the COC connection using P, in order to make a stable connection, the area of the COC connection pad 1 and the bump 6 is increased and the number of the conductive particles 5 existing between the connection pad 1 and the bump 6 is increased. Or, it is necessary to increase the conductive particles 5 contained in the ACP 4.
【００１２】しかしながら、ＣＯＣ接続パッド１とバン
プ６の面積を大きくすると、狭ピッチ、チップの小型化
に対応できないという課題があった。However, if the areas of the COC connection pads 1 and the bumps 6 are increased, there is a problem that the pitch cannot be reduced and the chip cannot be downsized.
【００１３】また、導電性粒子５の量を多くすると、安
定した接続を得られるが狭ピッチ化においてショートが
発生するという課題があった。Further, when the amount of the conductive particles 5 is increased, a stable connection can be obtained, but there is a problem that a short circuit occurs when the pitch is narrowed.
【００１４】したがって、この発明の目的は、このよう
なＡＣＰを用いたＣＯＣ接続において、狭ピッチ、チッ
プの小型化に対応可能であり、安定した接続を維持でき
る半導体装置およびその製造方法を提供することであ
る。Therefore, an object of the present invention is to provide a semiconductor device capable of coping with a narrow pitch and miniaturization of a chip and maintaining stable connection in a COC connection using such an ACP, and a manufacturing method thereof. That is.
【００１５】[0015]
【課題を解決するための手段】前述した目的を達成する
ために、この発明の請求項１記載の半導体装置は、第１
の半導体チップの電極に形成された突起電極と、第２の
半導体チップの電極とが電気的に接続され、前記第２の
半導体チップの電極の位置を開口するように前記第２の
半導体チップの表面に開口部を有する保護膜が形成さ
れ、前記第１の半導体チップと前記第２の半導体チップ
との間に、導電性粒子を含んだ樹脂が形成された半導体
装置であって、前記第２の半導体チップの電極どうしが
前記保護膜により仕切られ、前記開口部が個別に形成さ
れている。In order to achieve the above-mentioned object, the semiconductor device according to claim 1 of the present invention has a first structure.
Of the second semiconductor chip so that the protruding electrode formed on the electrode of the second semiconductor chip and the electrode of the second semiconductor chip are electrically connected to each other, and the position of the electrode of the second semiconductor chip is opened. A semiconductor device in which a protective film having an opening is formed on a surface, and a resin containing conductive particles is formed between the first semiconductor chip and the second semiconductor chip. The electrodes of the semiconductor chip are partitioned by the protective film, and the openings are individually formed.
【００１６】このように、第２の半導体チップの電極ど
うしが保護膜により仕切られ、開口部が個別に形成され
ているので、従来に比べて開口部にとどまる導電性粒子
の数が大幅に増加する。これにより、導電性粒子を含ん
だ樹脂を用いた第１の半導体チップと第２の半導体チッ
プのＣＯＣ接続において、挟ピッチ、チップの小型化に
対応可能である。また、電極どうしが仕切られているの
で挟ピッチ化においてもショートが発生することはな
く、安定した接続を維持できるＣＯＣ接続が得られると
いう作用を有する。As described above, since the electrodes of the second semiconductor chip are partitioned by the protective film and the openings are individually formed, the number of conductive particles remaining in the openings is significantly increased as compared with the conventional case. To do. Thereby, in the COC connection between the first semiconductor chip and the second semiconductor chip using the resin containing the conductive particles, it is possible to cope with a narrow pitch and downsizing of the chip. Further, since the electrodes are partitioned from each other, a short circuit does not occur even when the pitch is narrowed, and a COC connection capable of maintaining a stable connection can be obtained.
【００１７】請求項２記載の半導体装置は、請求項１記
載の半導体装置において、保護膜の厚みは、導電性粒子
の直径よりも大きい。このように、保護膜の厚みは、導
電性粒子の直径よりも大きいので、開口部にとどまる導
電性粒子がさらに増え安定した接続を維持できるＣＯＣ
接続が得られる。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the thickness of the protective film is larger than the diameter of the conductive particles. As described above, since the thickness of the protective film is larger than the diameter of the conductive particles, the number of the conductive particles remaining in the opening is further increased and the stable connection can be maintained.
Connection is obtained.
【００１８】請求項３記載の半導体装置の製造方法は、
第１の半導体チップの電極に突起電極を形成する工程
と、第２の半導体チップの電極の位置を開口し、かつ前
記第２の半導体チップの電極どうしを仕切るように開口
部を個別に形成した保護膜を前記第２の半導体チップの
表面に形成する工程と、前記第２の半導体チップの表面
側に導電性粒子を含んだ樹脂を塗布する工程と、前記突
起電極と前記第２の半導体チップの電極とを電気的に接
続する工程とを含む。A method of manufacturing a semiconductor device according to claim 3 is
The step of forming the protruding electrode on the electrode of the first semiconductor chip, the opening of the electrode of the second semiconductor chip, and the opening were separately formed so as to partition the electrodes of the second semiconductor chip. A step of forming a protective film on the surface of the second semiconductor chip, a step of applying a resin containing conductive particles on the surface side of the second semiconductor chip, the protruding electrode and the second semiconductor chip Electrically connecting the electrodes of the.
【００１９】このように、第１の半導体チップの電極に
突起電極を形成する工程と、第２の半導体チップの電極
の位置を開口し、かつ第２の半導体チップの電極どうし
を仕切るように開口部を個別に形成した保護膜を第２の
半導体チップの表面に形成する工程と、第２の半導体チ
ップの表面側に導電性粒子を含んだ樹脂を塗布する工程
と、突起電極と第２の半導体チップの電極とを電気的に
接続する工程とを含むので、従来に比べて開口部にとど
まる導電性粒子の数が大幅に増加する。すなわち、第１
の半導体チップと第２の半導体チップの接合時に、導電
性粒子を含んだ樹脂は中心より外に向かって押し出さ
れ、同時に樹脂中の導電性粒子も外に向かって移動す
る。樹脂が開口部を通過するとき、導電性粒子の一部が
開口部の段差によりとどまるが、開口部が個別に区切ら
れることにより、導電性粒子の移動が妨げられ開口部に
とどまり易くなる。これにより、導電性粒子を含んだ樹
脂を用いた第１の半導体チップと第２の半導体チップの
ＣＯＣ接続において、挟ピッチ、チップの小型化に対応
可能である。また、電極どうしが仕切られているので挟
ピッチ化においてもショートが発生することはなく、安
定した接続を維持できるＣＯＣ接続が得られるという作
用を有する。As described above, the step of forming the protruding electrodes on the electrodes of the first semiconductor chip, the opening of the electrodes of the second semiconductor chip, and the opening of the electrodes of the second semiconductor chip are divided. A step of forming a protective film having individual parts formed on the surface of the second semiconductor chip, a step of applying a resin containing conductive particles to the surface side of the second semiconductor chip, the protruding electrode and the second Since the step of electrically connecting the electrodes of the semiconductor chip is included, the number of conductive particles remaining in the openings is significantly increased as compared with the conventional case. That is, the first
When the semiconductor chip and the second semiconductor chip are bonded together, the resin containing the conductive particles is pushed outward from the center, and at the same time, the conductive particles in the resin also move outward. When the resin passes through the opening, a part of the conductive particles stays due to the step difference in the opening. However, the individual partitioning of the opening hinders the movement of the conductive particles and makes it easier to stay in the opening. Thereby, in the COC connection between the first semiconductor chip and the second semiconductor chip using the resin containing the conductive particles, it is possible to cope with a narrow pitch and downsizing of the chip. Further, since the electrodes are partitioned from each other, a short circuit does not occur even when the pitch is narrowed, and a COC connection capable of maintaining a stable connection can be obtained.
【００２０】[0020]
【発明の実施の形態】この発明の実施の形態を図１〜図
３に基づいて説明する。図１はこの発明の実施の形態の
半導体装置の概略断面図、図２（ａ）はこの発明の実施
の形態の半導体装置の保護膜が形成された半導体チップ
の平面図、（ｂ）はＡ−Ａ断面図である。なお従来例の
図４、図５、図６と同一の構成には同一の符号を付す。DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described with reference to FIGS. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2A is a plan view of a semiconductor chip having a protective film formed thereon according to the embodiment of the present invention, and FIG. FIG. The same components as those in FIGS. 4, 5, and 6 of the conventional example are designated by the same reference numerals.
【００２１】図１および図２において、１は接続パッド
（電極）、２は半導体チップ（Ｓｉチップ）、３は保護
膜、４はＡＣＰ、５は導電性粒子、６はバンプ（突起電
極）である。Ｓｉチップ２は、第１の半導体チップ２ｂ
と第２の半導体チップ２ａとからなる。In FIGS. 1 and 2, 1 is a connection pad (electrode), 2 is a semiconductor chip (Si chip), 3 is a protective film, 4 is ACP, 5 is conductive particles, and 6 is a bump (protruding electrode). is there. The Si chip 2 is the first semiconductor chip 2b.
And a second semiconductor chip 2a.
【００２２】この半導体装置のＡＣＰ４を用いたＣＯＣ
接続を行った場合の接続部の断面は図１の通りである。
すなわち、図１に示すように、第１の半導体チップ２ｂ
の電極に形成されたバンプ６と、第２の半導体チップ２
ａの接続パッド１とが電気的に接続され、第２の半導体
チップ２ａの接続パッド１の位置を開口するように第２
の半導体チップ２ａの表面に開口部８を有する保護膜３
が形成され、第１の半導体チップ２ｂと第２の半導体チ
ップ２ａとの間に、導電性粒子５を含んだＡＣＰ４が形
成されている。COC using ACP4 of this semiconductor device
The cross section of the connecting portion when the connection is performed is as shown in FIG.
That is, as shown in FIG. 1, the first semiconductor chip 2b
Bumps 6 formed on the electrodes of the second semiconductor chip 2
a is electrically connected to the connection pad 1 of the second semiconductor chip 2a so as to open the position of the connection pad 1 of the second semiconductor chip 2a.
Protective film 3 having opening 8 on the surface of semiconductor chip 2a
Is formed, and the ACP 4 containing the conductive particles 5 is formed between the first semiconductor chip 2b and the second semiconductor chip 2a.
【００２３】また、図２に示すように全てのＣＯＣ接続
パッド１が露出するように、保護膜３に開口部８を個別
に形成する。これにより、第２の半導体チップ２ａの接
続パッド１どうしは保護膜３により仕切られている。Further, as shown in FIG. 2, openings 8 are individually formed in the protective film 3 so that all the COC connection pads 1 are exposed. As a result, the connection pads 1 of the second semiconductor chip 2a are separated by the protective film 3.
【００２４】次にこの発明の実施の形態の半導体装置の
製造方法について説明する。すなわち、第１の半導体チ
ップ２ｂの電極にバンプ６を形成する工程と、第２の半
導体チップ２ａの接続パッド１の位置を開口し、かつ第
２の半導体チップ２ａの接続パッド１どうしを仕切るよ
うに開口部８を個別に設けた保護膜３を第２の半導体チ
ップ２ａの表面に形成する工程と、第２の半導体チップ
２ａの表面側に導電性粒子５を含んだＡＣＰ４を塗布す
る工程と、バンプ６と第２の半導体チップ２ａの接続パ
ッド１とを電気的に接続する工程とを含む。Next, a method of manufacturing the semiconductor device according to the embodiment of the present invention will be described. That is, the step of forming the bumps 6 on the electrodes of the first semiconductor chip 2b, opening the positions of the connection pads 1 of the second semiconductor chip 2a, and partitioning the connection pads 1 of the second semiconductor chip 2a. A step of forming a protective film 3 having openings 8 individually formed on the surface of the second semiconductor chip 2a, and a step of applying ACP4 containing conductive particles 5 on the surface side of the second semiconductor chip 2a. Electrically connecting the bump 6 and the connection pad 1 of the second semiconductor chip 2a.
【００２５】上記の製造工程において、ＡＣＰ４を用い
てＣＯＣ接続を行った場合のプロセスとＡＣＰ４中の導
電性粒子５の挙動について説明する。図３（ａ）〜
（ｃ）はこの発明の半導体装置の製造方法において接続
プロセスの概念を示す工程図である。In the above manufacturing process, the process when the COC connection is performed using the ACP 4 and the behavior of the conductive particles 5 in the ACP 4 will be described. Fig.3 (a)-
(C) is a process drawing which shows the concept of a connection process in the manufacturing method of the semiconductor device of this invention.
【００２６】図３（ａ）に示すように、初めにＡＣＰ４
を塗布装置によりＣＯＣ接続パッド１が形成された第２
の半導体チップ２ａに塗布する。As shown in FIG. 3A, first, ACP4
The second with the COC connection pad 1 formed by the coating device
Is applied to the semiconductor chip 2a.
【００２７】次に、図３（ｂ），（ｃ）に示すように、
バンプ６が形成された第１の半導体チップ２ｂが、第２
の半導体チップ２ａの所定の位置に位置合わせされ、所
定の荷重により接合される。この接合時に、ＡＣＰ４は
中心より外に向かって押し出され、同時にＡＣＰ４中の
導電性粒子５も外に向かって移動する。Next, as shown in FIGS. 3 (b) and 3 (c),
The first semiconductor chip 2b on which the bumps 6 are formed is the second semiconductor chip 2b.
The semiconductor chip 2a is aligned with a predetermined position and bonded by a predetermined load. At the time of this bonding, the ACP 4 is pushed outward from the center, and at the same time, the conductive particles 5 in the ACP 4 also move outward.
【００２８】接続パッド１の開口部８をＡＣＰ４が通過
するとき、ＡＣＰ４中の導電性粒子５の一部が開口部８
の段差により接続パッド１の周辺にとどまる。最後に、
接続パッド1とバンプ６の間に導電性粒子５が挟みこま
れて接続が完了する（図１）。When the ACP 4 passes through the opening 8 of the connection pad 1, a part of the conductive particles 5 in the ACP 4 is opened.
Stays around the connection pad 1 due to the step. Finally,
The conductive particles 5 are sandwiched between the connection pad 1 and the bump 6 to complete the connection (FIG. 1).
【００２９】ＣＯＣ接続パッド１とバンプ６の間に挟み
こまれる導電性粒子５の数は接続パッド１の開口部８が
個別に区切られることにより、従来の開口に比べ導電性
粒子５の移動が妨げられて、開口部８にとどまる数が図
１に示すように大幅に増加する。この際、導電性粒子５
の密度は、ＡＣＰ４の密度よりも大きいために、ＡＣＰ
４に含まれた導電性粒子５は流動するにともなって下方
に移動し、最終的には保護膜３の表面よりも下方に移動
して開口部８の表面にとどまる。The number of the conductive particles 5 sandwiched between the COC connection pad 1 and the bump 6 is larger than that in the conventional opening because the openings 8 of the connection pad 1 are individually divided. The number of obstacles that remain in the opening 8 is greatly increased as shown in FIG. At this time, the conductive particles 5
Since the density of ACP4 is higher than that of ACP4,
The conductive particles 5 contained in 4 move downward as they flow, and finally move below the surface of the protective film 3 and remain on the surface of the opening 8.
【００３０】このように本実施の形態によれば、ＡＣＰ
４を用いたＣＯＣ接続において、狭ピッチ、チップの小
型化に対応可能である。また、接続パッド１どうしが仕
切られているので挟ピッチ化においてもショートが発生
することはなく、安定した接続を維持できるＣＯＣ接続
が得られる。As described above, according to the present embodiment, the ACP
In the COC connection using No. 4, it is possible to cope with a narrow pitch and downsizing of a chip. Further, since the connection pads 1 are partitioned from each other, a short circuit does not occur even when the pitch is narrowed, and a COC connection capable of maintaining stable connection can be obtained.
【００３１】さらに、接続パッド１の開口部８を形成し
ている保護膜３の厚みが、導電性粒子５の直径より大き
くなれば、接続パッド１の開口部８にとどまる導電性粒
子５がさらに増え安定した接続を維持できるＣＯＣ接続
が得られる。Further, when the thickness of the protective film 3 forming the opening 8 of the connection pad 1 becomes larger than the diameter of the conductive particle 5, the conductive particle 5 remaining in the opening 8 of the connection pad 1 is further increased. A COC connection can be obtained that can increase and maintain a stable connection.
【００３２】また、保護膜３に形成する開口部８の形状
は、実施の形態では四角としているが、各接続パッド１
を分離できれば、丸、楕円、多角形などどのような形状
でも良い。The shape of the opening 8 formed in the protective film 3 is a square in the embodiment, but each connection pad 1
Any shape such as a circle, an ellipse, or a polygon may be used as long as it can be separated.
【００３３】[0033]
【発明の効果】この発明の請求項１記載の半導体装置に
よれば、第２の半導体チップの電極どうしが保護膜によ
り仕切られ、開口部が個別に形成されているので、従来
に比べて開口部にとどまる導電性粒子の数が大幅に増加
する。これにより、導電性粒子を含んだ樹脂を用いた第
１の半導体チップと第２の半導体チップのＣＯＣ接続に
おいて、挟ピッチ、チップの小型化に対応可能である。
また、電極どうしが仕切られているので挟ピッチ化にお
いてもショートが発生することはなく、安定した接続を
維持できるＣＯＣ接続が得られるという効果を有する。According to the semiconductor device of the first aspect of the present invention, the electrodes of the second semiconductor chip are partitioned by the protective film and the openings are individually formed. The number of conductive particles remaining in the area is significantly increased. Thereby, in the COC connection between the first semiconductor chip and the second semiconductor chip using the resin containing the conductive particles, it is possible to cope with a narrow pitch and downsizing of the chip.
Further, since the electrodes are partitioned from each other, a short circuit does not occur even when the pitch is narrowed, and a COC connection capable of maintaining a stable connection is obtained.
【００３４】請求項２では、保護膜の厚みは、導電性粒
子の直径よりも大きいので、開口部にとどまる導電性粒
子がさらに増え安定した接続を維持できるＣＯＣ接続が
得られる。In the second aspect, since the thickness of the protective film is larger than the diameter of the conductive particles, the number of the conductive particles remaining in the opening is further increased, and a COC connection capable of maintaining a stable connection can be obtained.
【００３５】この発明の請求項３記載の半導体装置の製
造方法によれば、第１の半導体チップの電極に突起電極
を形成する工程と、第２の半導体チップの電極の位置を
開口し、かつ第２の半導体チップの電極どうしを仕切る
ように開口部を個別に形成した保護膜を第２の半導体チ
ップの表面に形成する工程と、第２の半導体チップの表
面側に導電性粒子を含んだ樹脂を塗布する工程と、突起
電極と第２の半導体チップの電極とを電気的に接続する
工程とを含むので、従来に比べて開口部にとどまる導電
性粒子の数が大幅に増加する。すなわち、第１の半導体
チップと第２の半導体チップの接合時に、導電性粒子を
含んだ樹脂は中心より外に向かって押し出され、同時に
樹脂中の導電性粒子も外に向かって移動する。樹脂が開
口部を通過するとき、導電性粒子の一部が開口部の段差
によりとどまるが、開口部が個別に区切られることによ
り、導電性粒子の移動が妨げられ開口部にとどまり易く
なる。これにより、導電性粒子を含んだ樹脂を用いた第
１の半導体チップと第２の半導体チップのＣＯＣ接続に
おいて、挟ピッチ、チップの小型化に対応可能である。
また、電極どうしが仕切られているので挟ピッチ化にお
いてもショートが発生することはなく、安定した接続を
維持できるＣＯＣ接続が得られるという効果を有する。According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, the step of forming the protruding electrode on the electrode of the first semiconductor chip, the position of the electrode of the second semiconductor chip are opened, and A step of forming a protective film on the surface of the second semiconductor chip in which openings are individually formed so as to partition electrodes of the second semiconductor chip, and conductive particles are included on the surface side of the second semiconductor chip. Since the step of applying the resin and the step of electrically connecting the protruding electrode and the electrode of the second semiconductor chip are included, the number of conductive particles remaining in the opening is significantly increased as compared with the conventional case. That is, at the time of joining the first semiconductor chip and the second semiconductor chip, the resin containing the conductive particles is pushed outward from the center, and at the same time, the conductive particles in the resin also move outward. When the resin passes through the openings, a part of the conductive particles stays due to the step difference in the openings, but the individual partitioning of the openings hinders the movement of the conductive particles and easily stays in the openings. Thereby, in the COC connection between the first semiconductor chip and the second semiconductor chip using the resin containing the conductive particles, it is possible to cope with a narrow pitch and downsizing of the chip.
Further, since the electrodes are partitioned from each other, a short circuit does not occur even when the pitch is narrowed, and a COC connection capable of maintaining a stable connection is obtained.
【図１】この発明の実施の形態の半導体装置の概略断面
図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】（ａ）はこの発明の実施の形態の半導体装置の
保護膜が形成された半導体チップの平面図、（ｂ）はＡ
−Ａ断面図である。FIG. 2A is a plan view of a semiconductor chip having a protective film formed thereon of a semiconductor device according to an embodiment of the present invention, and FIG.
FIG.
【図３】（ａ）〜（ｃ）はこの発明の半導体装置の製造
方法において接続プロセスの概念を示す工程図である。3A to 3C are process diagrams showing the concept of a connection process in the method for manufacturing a semiconductor device of the present invention.
【図４】（ａ）は従来例において保護膜が形成された半
導体チップの平面図、（ｂ）はＣ−Ｃ断面図である。4A is a plan view of a semiconductor chip in which a protective film is formed in a conventional example, and FIG. 4B is a sectional view taken along line CC.
【図５】（ａ）〜（ｃ）は従来例において接続プロセス
の概念を示す工程図である。5A to 5C are process diagrams showing the concept of a connection process in a conventional example.
【図６】従来例の概略断面図である。FIG. 6 is a schematic cross-sectional view of a conventional example.
１ 接続パッド ２ 半導体チップ（Ｓｉチップ） ２ａ 第２の半導体チップ ２ｂ 第１の半導体チップ ３ 保護膜 ４ ＡＣＰ ５ 導電性粒子 ６ バンプ ８ 開口部 1 connection pad 2 Semiconductor chip (Si chip) 2a Second semiconductor chip 2b First semiconductor chip 3 protective film 4 ACP 5 Conductive particles 6 bumps 8 openings
───────────────────────────────────────────────────── フロントページの続き (72)発明者 菅野 純一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 竹村 康司 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 LL09 LL17 QQ08 RR17 RR18 RR19 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Junichi Kanno 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. (72) Inventor Koji Takemura 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F term (reference) 5F044 LL09 LL17 QQ08 RR17 RR18 RR19
Claims (3)
突起電極と、第２の半導体チップの電極とが電気的に接
続され、前記第２の半導体チップの電極の位置を開口す
るように前記第２の半導体チップの表面に開口部を有す
る保護膜が形成され、前記第１の半導体チップと前記第
２の半導体チップとの間に、導電性粒子を含んだ樹脂が
形成された半導体装置であって、前記第２の半導体チッ
プの電極どうしが前記保護膜により仕切られ、前記開口
部が個別に形成されていることを特徴とする半導体装
置。1. A protruding electrode formed on an electrode of a first semiconductor chip and an electrode of a second semiconductor chip are electrically connected to each other so that the electrode of the second semiconductor chip is opened at the position. A semiconductor device in which a protective film having an opening is formed on the surface of the second semiconductor chip, and a resin containing conductive particles is formed between the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the electrodes of the second semiconductor chip are partitioned by the protective film, and the openings are individually formed.
も大きい請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the thickness of the protective film is larger than the diameter of the conductive particles.
形成する工程と、第２の半導体チップの電極の位置を開
口し、かつ前記第２の半導体チップの電極どうしを仕切
るように開口部を個別に形成した保護膜を前記第２の半
導体チップの表面に形成する工程と、前記第２の半導体
チップの表面側に導電性粒子を含んだ樹脂を塗布する工
程と、前記突起電極と前記第２の半導体チップの電極と
を電気的に接続する工程とを含む半導体装置の製造方
法。3. A step of forming a protruding electrode on an electrode of a first semiconductor chip, an opening for opening an electrode of the second semiconductor chip, and an opening for partitioning the electrodes of the second semiconductor chip. Forming a protective film individually formed on the surface of the second semiconductor chip, applying a resin containing conductive particles to the surface side of the second semiconductor chip, the protruding electrode and the And a step of electrically connecting the electrodes of the second semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002136593A JP2003332384A (en) | 2002-05-13 | 2002-05-13 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002136593A JP2003332384A (en) | 2002-05-13 | 2002-05-13 | Semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003332384A true JP2003332384A (en) | 2003-11-21 |
Family
ID=29698567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002136593A Pending JP2003332384A (en) | 2002-05-13 | 2002-05-13 | Semiconductor device and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP2003332384A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237280A (en) * | 2005-02-25 | 2006-09-07 | Sony Corp | Semiconductor device and its manufacturing method |
| US7750469B2 (en) | 2005-08-24 | 2010-07-06 | Samsung Electronics Co., Ltd. | Insulating layer between bumps of semiconductor chip, and display panel using the same with anisotropic conductive film between semiconductor chip and substrate |
-
2002
- 2002-05-13 JP JP2002136593A patent/JP2003332384A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006237280A (en) * | 2005-02-25 | 2006-09-07 | Sony Corp | Semiconductor device and its manufacturing method |
| US7750469B2 (en) | 2005-08-24 | 2010-07-06 | Samsung Electronics Co., Ltd. | Insulating layer between bumps of semiconductor chip, and display panel using the same with anisotropic conductive film between semiconductor chip and substrate |
| TWI419292B (en) * | 2005-08-24 | 2013-12-11 | Samsung Display Co Ltd | Semiconductor chip, display panel using the same, and methods of manufacturing semiconductor chip and display panel using the same |
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