JP2003303883A - Method for forming wire - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a forming method for a wire which can form the wire of high quality by a simple method while suppressing an increase in the number of manufacturing processes. <P>SOLUTION: The method for forming the wire comprises steps for: (a) forming an etching-preventive film on a substrate where a lower-layer wire is formed; (b) forming an inter-layer insulating film on the substrate; (c) forming a connection hole in the inter-layer insulating film; (d) forming a non- photosensitive organic material film on the inter-layer insulating film including the connection hole; (e) removing the organic material film on the inter-layer insulating film while leaving the organic material film in the connection hole; (f) forming a resist pattern which has an opening in the area including the connection hole; (g) forming a wire groove by patterning the inter-layer insulating film by using the resist pattern as a mask; (h) removing the resist pattern, organic material film, and etching-preventive film; and (i) forming an upper-layer wire reaching the lower-layer wire by filling the connection hole and wire groove with a conductive film. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method, and more particularly to a wiring forming method for forming a semiconductor element or an integrated circuit.

[0002]

2. Description of the Related Art In manufacturing a semiconductor integrated circuit, an interlayer insulating film is formed on a metal wiring, and dry etching is performed to form a connection hole reaching the metal wiring in the interlayer insulating film. However, a method of embedding a metal material in the connection hole and forming a metal wiring on the metal material has been the mainstream. However, in recent years, due to miniaturization, multilayer wiring is inevitably formed. Therefore, the number of steps is increased and the formation thereof is difficult in the above method. In addition, it is difficult to realize next-generation fine wiring that is difficult to form by dry etching and copper wiring that is difficult to etch itself.

Therefore, after forming an interlayer insulating film, a groove having a wiring shape is formed in the interlayer insulating film, and a metal film is formed in the groove to form a wiring.
ne) method has been developed and put into practical use. In addition, so-called dual damascene (dua damascene (dua damascene)
l damascene) method is also used. A method of forming a multilayer wiring structure by such a dual damascene method is as follows. First, as shown in FIG. 3A, the lower wiring 12 is formed on the interlayer insulating film 11 and the plasma SiN film 13, and the plasma SiN film 1 is formed on the entire surface thereof.
4. Interlayer insulating film 15 is sequentially deposited.

Next, as shown in FIG. 3B, a resist pattern 21 having an opening at a position where a connection hole is formed is formed. Subsequently, as shown in FIG. 3C, etching is performed using the resist pattern 21 as a mask to form a connection hole, and then the resist is removed by O ₂ plasma. Next, as shown in FIG. 3D, a positive type resist 23a for forming a wiring groove is applied, and exposure and development are performed using a mask having a predetermined pattern.
As shown in (e), a resist pattern 23 is formed. At this time, the resist pattern 23 is left at the bottom of the connection hole because it is necessary to protect the lower layer wiring pattern at the bottom of the connection hole by etching for forming a wiring groove in the next step. Then, using the obtained resist pattern 23 as a mask, a groove is formed in the interlayer insulating film 15, and a metal film is embedded in the connection hole and the groove to form a wiring (not shown).

However, usually, in the photolithography and etching process for forming the wiring groove, the resist in the connection hole is also exposed, so that a resist having a sufficient film thickness is formed on the bottom of the connection hole after development. It cannot be left. Therefore, as shown in FIG. 3F, there is a problem in that the surface of the lower layer wiring 12 is etched, the lower layer wiring is partially thinned, and plasma damage occurs. As a method of solving such a problem, for example,
In Japanese Unexamined Patent Publication No. 2000-58647, similarly to the above method, after forming a connection hole as shown in FIGS. 4A to 4D, a positive resist 23a is formed inside the connection hole,
As shown in FIG. 4 (e), a mask pattern 31 of a wiring groove having a pattern with a dimension equal to or less than the resolution limit is formed at a position corresponding to a connection hole, and exposure and development are performed using the mask pattern 31. As shown in FIG. 4 (f), a method of forming a resist pattern for a wiring groove has been proposed. As a result, the resist 25 remains inside the connection hole, and the lower layer wiring 12 can be protected.

Further, in Japanese Patent Laid-Open No. 2000-188329, etc., as shown in FIG. 5 (d), after forming a connection hole as shown in FIGS. 5 (a) to 5 (c), as in the above method. To
The photosensitive resin layer 41 is embedded inside the connection hole, and the photosensitive resin layer 41 is entirely exposed and developed to remove the photosensitive resin layer 41 except the connection hole as shown in FIG. 5E. Then
Then, the photosensitive resin layer 41 is baked to cure the photosensitive resin layer 41 inside the connection hole, and as shown in FIG. 5F, a resist pattern 23 for forming a wiring groove.
Then, the resist pattern 23 is used as a mask to etch the interlayer insulating film 15 to form a wiring groove as shown in FIG. 5G, and thereafter, as shown in FIG. Thus, a method of removing the photosensitive resin layer 41 has been proposed. However, with the method shown in FIG. 4, it is difficult to leave the resist inside the connection hole with good controllability, and in particular, the amount of remaining resist inside the connection hole changes due to misalignment and variations in the light amount of the exposure device. In addition, when the mask pattern of the wiring groove is manufactured, a pattern having a resolution limit is required, which makes layout difficult.

Further, in the method shown in FIG. 5, since the cured photosensitive resin layer 41 is filled inside the connection hole, after the wiring groove is formed, the photosensitive resin layer 41 is removed by exposure and development. This requires treatments, etc., which makes it difficult to increase the number of steps and completely remove the cured photosensitive resin layer. The present invention has been made in view of the above problems, and an object of the present invention is to provide a wiring forming method capable of forming high-quality wiring by a simple method while suppressing an increase in manufacturing steps.

[0008]

According to the present invention, (a)
A step of forming an etching prevention film on the substrate on which the lower layer wiring is formed, (b) a step of forming an interlayer insulating film on the substrate, and (c) a step of forming a connection hole in the interlayer insulating film, (D) a step of forming a non-photosensitive organic material film on the interlayer insulating film including the connection hole, and (e) an organic material on the interlayer insulating film while leaving the organic material film in the connection hole. A step of removing the material film, (f) a step of forming a resist pattern having an opening in a region including the connection hole,
(G) patterning the interlayer insulating film using the resist pattern as a mask to form a wiring groove;
(H) a step of removing the resist pattern, the organic material film and the etching prevention film, and (i) a step of burying a conductive film in the connection hole and the wiring groove to form an upper layer wiring reaching the lower layer wiring. A method of forming a wiring having the same is provided.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In the wiring forming method of the present invention, first, in step (a), a substrate on which a lower layer wiring is formed is prepared, and an etching prevention film is formed thereon. Here, as the substrate, various substrates such as an elemental semiconductor substrate such as silicon, a compound semiconductor substrate such as GaAs, a so-called SOI substrate, which are usually used for forming a semiconductor device, can be cited. It is preferable that semiconductor elements such as transistors, capacitors, and resistors, circuits, and the like, element isolation regions, wiring layers, interlayer insulating films, and the like be formed on the substrate.

The lower layer wiring usually means a layer formed on a substrate with a conductive material such as an electrode or a wiring, but it may be a semiconductor substrate itself which functions as a wiring layer by being doped with impurities. . When the lower layer wiring is made of a conductive material, the lower layer wiring is preferably formed on an insulating film formed as a so-called interlayer insulating film. Examples of the conductive material include metals such as aluminum and copper, refractory metals such as tungsten, titanium, and tantalum, silicon, silicide, polycide, and alloys thereof. Among them, copper or copper alloy is preferable. The insulating film may be a film having any material, structure and film thickness as long as it can be used as an interlayer insulating film. In this case, the lower layer wiring is, for example, embedded in the groove formed in the insulating film,
It is preferably formed flat on the substrate.

The etching preventive film formed thereon has a small etching rate with respect to the interlayer insulating film formed in the step (b) or can protect the lower layer wiring when the interlayer insulating film is etched. Any material, structure, and film thickness may be used as long as it is a material. For example, the etching prevention film may be a single layer or a laminated film such as a silicon nitride film. Of these, a silicon nitride film is preferable.
The film thickness is, for example, about 20 to 100 nm. This film is formed, for example, by a sputtering method, various CVD methods,
It can be formed by a method known in the art such as a MOCVD method or a sol-gel method.

In step (b), an interlayer insulating film is formed on the obtained substrate. As described above, the interlayer insulating film here can be appropriately selected from those having a larger etching rate than the etching preventive film depending on the material, film thickness, structure, etc. of the etching preventive film. Thermal oxide film, low temperature oxide film: LTO film, etc., high temperature oxide film:
HTO film, TEOS film), SOG film, PSG film, BSG
A film, a single layer film such as a BPSG film, or a laminated film may be used.
The film thickness is, for example, about 700 to 3000 nm. This film can be formed by the same method as described above.

In step (c), a connection hole is formed in the interlayer insulating film. Since the connection hole here is used for electrically connecting to the lower layer wiring by embedding a conductive material in a later step, the shape and size are taken into consideration in consideration of its function and characteristics. It can be adjusted appropriately. The connection hole can be formed by a known method such as photolithography and etching. It is necessary to stop the formation of the connection hole here until reaching the etching prevention film, not to the lower layer wiring, in order to prevent etching damage to the lower layer wiring.

In step (d), a non-photosensitive organic material film is formed on the interlayer insulating film. The non-photosensitive organic material film here is preferably formed of a material that is less likely to be etched than the resist pattern formed in the step (f) and further the interlayer insulating film formed in the step (c). Depending on the etching method and the type of etchant used, a material having an etching rate as low as about 20 to 90% is suitable. Specific examples thereof include novolak resins that are generally used as a base resin for g-line or i-line resist. Of these, novolak resins are useful because they are easily available and inexpensive because they do not contain a photosensitizer. The organic material film can be formed by applying a known coating method such as a spin coating method or a doctor blade method, and drying. In addition,
Here, it is suitable to uniformly form the organic material film with a film thickness of about 100 to 200 nm on the interlayer insulating film and completely embed it in the wiring hole.

In step (e), the organic material film on the interlayer insulating film is removed. At this time, at least a part of the organic material film needs to remain in the connection hole. The organic insulating film is preferably removed by wet etching using a solvent that can dissolve the organic material film, for example, an alkaline developing solution. Examples of alkaline developers include tetramethyl ammonium hydroxide (TMAH),
Examples thereof include one or a mixture of two or more of sodium hydroxide, ammonia, potassium hydroxide, calcium hydroxide, sodium hydroxide and the like. Of these, TMAH is preferable. The alkaline developer is, for example, 100 to 200 n.
So that it can be dissolved at an etching rate of about m / minute,
It is preferable to adjust its kind and concentration, and in the above alkaline developer, about 1 to 10% by weight, especially TM
In the case of AH, it is preferable to use it at a concentration of about 2 to 4%.

In the present invention, an antireflection film may be further formed on the interlayer insulating film and the connection hole after removing the organic material film on the interlayer insulating film. The antireflection film reduces the line width variation of the photo of the wiring groove during the photo of the wiring groove and the development and suppresses the reduction of the non-photosensitive organic material film in the connection hole at the time of the development, for example, the novolac resin film. It is desirable to use a material that can do so and has an etching rate faster than that of the resist. As the antireflection film, a commercially available antireflection film made of an organic material can be used. The film thickness of the antireflection film is not particularly limited, but it is suitable to form it flat over the connection hole to the interlayer insulating film and to have a film thickness of about 20 to 100 nm on the interlayer insulating film. is there. The antireflection film can be formed by a spin coating method, a doctor blade method, or the like, as in the above.

In step (f), a resist pattern having an opening in a region including a connection hole is formed. The resist pattern can be formed by a known method such as photolithography and etching. In addition, in the steps (d) to (f), it is preferable to perform a series of sequences in a spinner device having a coating cup, a developing cup and a bake plate without exposing to the outside air. Also, when forming the antireflection film, it is preferable to perform a series of sequences in the same spinner device. As such a spinner device, a device generally used in the art can be used.

In step (g), the interlayer insulating film is patterned using the resist pattern as a mask to form a wiring groove. Examples of the patterning here include dry etching such as RIE and wet etching using an acid or alkaline solution. Above all, it is preferable to select an etching method for increasing the etching rate of the interlayer insulating film with respect to the non-photosensitive organic material film existing under the resist pattern and optionally the antireflection film.

In step (h), a resist pattern,
The organic material film and the etching prevention film are removed. Similar to the above, the removal here includes various methods such as dry etching such as RIE method, wet etching using an acid or alkaline solution, an organic solvent, etc., depending on the material forming each film. It is necessary to select the optimum conditions that do not damage the film or the like existing in the lower layer.

In step (i), a conductive film is embedded in the connection hole and the wiring groove to form an upper layer wiring reaching the lower layer wiring. The conductive film here can be formed using the materials exemplified for the lower layer wiring, and among them, copper or copper alloy is preferable. However, it is not always necessary to form the same material as the lower layer wiring. The conductive film is formed by sputtering, EB,
By various methods such as a vapor deposition method and a CVD method, it may be embedded only in the connection hole and the wiring groove, or by forming a film on the interlayer insulating film including the connection hole and the wiring groove and etching back,
It may be buried so as to be flush with the connection hole and the wiring groove, or may be embedded in the connection hole and the wiring groove by etching back using a mask having a desired shape, and may have a desired shape on the interlayer insulating film. The upper layer wiring having the wiring pattern of may be formed. An embodiment of a wiring forming method of the present invention will be described below in detail with reference to the drawings.

Example 1 First, as shown in FIG. 1A, after forming a lower wiring 12 made of copper on an interlayer insulating film 11, a plasma SiN film 13 is formed and an etching preventing film is further formed on the entire surface. The plasma SiN film 14 has a film thickness of about 50 nm, and the interlayer insulating film 15
As a plasma TEOS film, a film thickness of about 1000 nm, C
It is deposited by the VD method. Next, as shown in FIG. 1B, a resist is applied on the obtained interlayer insulating film 15,
The resist is exposed and developed using a mask having an opening at a position corresponding to the position where the connection hole is formed, and a resist pattern 21 is formed. Next, as shown in FIG. 1C, the interlayer insulating film 15 is etched by the RIE method using the resist pattern 21 as a mask, and then O
_{2 The} resist pattern 21 is removed by plasma to form a connection hole. Although copper is very susceptible to oxidation,
Since the plasma SiN film 14 is provided on the lower layer wiring 12, the lower layer wiring 12 is not exposed to O ₂ plasma when the resist pattern 21 is removed, and copper that is the lower layer wiring 12 is oxidized. Can be prevented. Then, as shown in FIG. 1D, a novolac resin 22 used as a base resin for a general g-line or i-line resist is deposited on the interlayer insulating film 15 by 100 to 200 nm by using a spin coater. A uniform film thickness is applied, the inside of the connection hole is filled, and a baking process is performed at a temperature of about 90 ° C.

Next, as shown in FIG. 1 (e), the novolac resin 22 is dissolved by the paddle method using an alkaline developer such as TMAH (NMD-W, manufactured by Tokyo Ohka Kagaku Kogyo Co., Ltd.) and connected. The interlayer insulating film 1 is left as it is inside the hole.
All the novolac resin 22 on 5 is removed. At this time, the dissolution rate of the novolac resin in the developing solution must be made as slow as possible because the novolac resin 22 inside the connection hole is exposed to the developing solution when the resist pattern of the wiring groove is formed in the subsequent step. In this case, it was set to 200 nm / min. The novolac resin 22 on the interlayer insulating film 15
As a result of performing overdevelopment to some extent in order to completely remove the above, the novolac resin 22 inside the connection hole is reduced by about 100 nm from the upper portion of the interlayer insulating film 15. Subsequently, as shown in FIG. 1F, a positive chemical amplification resist 23b for forming a wiring groove is formed by applying HMDS (hexamethylene disilazane) as an adhesion enhancer on the interlayer insulating film 15. Apply about 500 nm.

Next, as shown in FIG. 1G, exposure and development are performed using a predetermined mask to form a resist pattern 2.
3 is formed. At this time, the developing time is set to 60 seconds, and the novolac resin 22 inside the connection hole is thinned by about 200 nm. At this stage, the novolac resin 22 inside the connection hole is reduced by about 300 nm from the upper portion of the interlayer insulating film 15, but about 700 nm remains. Further, as shown in FIG. 1H, the interlayer insulating film 15 is etched by the RIE method using the resist pattern 23 as a mask to form a wiring groove pattern. On this occasion,
The RIE etching rate of the novolac resin 22 is
RI of positive chemically amplified resist for forming wiring groove
Since the etching rate is slower by about 77 to 83% than the etching rate at E, the novolac resin remains inside the connection hole after the etching of the wiring groove. After that, as shown in FIG. 1I, the resist pattern 23 on the interlayer insulating film 15 and the novolac resin 22 inside the connection hole are removed by O ₂ plasma to form a wiring groove.

Next, as shown in FIG. 1J, the plasma SiN film 14 immediately below the wiring groove is etched. Etching is performed in an atmosphere with a pressure of 20 to 80 mT and a power of 250 to
About 600 W, CH ₂ F ₂ gas is introduced at 10 to 30 sccm, Ar gas is introduced at 50 to 200 sccm, and O ₂ gas is introduced at about 10 to 30 sccm. Under this condition, the selection ratio of the plasma SiN film 14 and the interlayer insulating film 15 during etching is about 5 to 25, and no resist mask is required when etching the plasma SiN film 14, and the plasma SiN film is used as a mask. It is possible to etch 14.
Then, a copper film is formed on the wiring groove by a normal plating method to a thickness of 500 to 11
The thickness is about 100 nm, and the copper film is polished and the substrate is flattened by the electromechanical polishing method to form the metal wiring 16 embedded with the copper film. After that, copper, a copper alloy, an aluminum alloy, or the like is formed over the entire surface of the substrate by sputtering or the like, and patterned to form the upper wiring 17.

Example 2 Similar to Example 1, the lower layer wiring pattern 12, the plasma SiN films 13, 14 and the interlayer insulating film 1 were formed on the interlayer insulating film 11.
5, the connection hole, and the novolac resin 22 are formed (FIG. 2).
(A) -FIG.2 (e)). Next, as shown in FIG. 2F, a commercially available antireflection film 24 made of an organic material is formed to a thickness of 60 nm.
The positive type chemically amplified resist 23b for forming the wiring groove is applied to a thickness of about 500 nm. After that, Figure 2
As shown in (g), exposure and development are performed using a predetermined mask to form a resist pattern 23. At this time, in Example 1, the novolac resin 22 inside the connection hole is exposed to the developing solution, so that the film is reduced, but in the present embodiment in which the antireflection film 24 is applied, the novolac resin 22 inside the connection hole is reduced. do not do.

Then, as shown in FIG. 2H, the interlayer insulating film 15 is formed by using the resist pattern 23 as a mask.
Is etched by RIE to form a wiring groove pattern. At this time, the etching rate of the novolac resin by RIE is about 77 to 70% compared with the etching rate of the positive chemically amplified resist for forming the wiring groove by RIE.
Since it is as slow as 83%, the novolac resin 22 remains inside the connection hole after the etching of the wiring groove. Then, FIG.
As shown in (i), the interlayer insulating film 1 is formed by O ₂ plasma.
The resist pattern on 5 and the novolac resin 22 inside the connection hole are removed to form a wiring groove. After that, FIG. 2 (j)
As shown in, the upper wiring is formed by the same method as in the first embodiment.

[0027]

According to the present invention, in the dual damascene method, a low resistance metal wiring can be formed by a simple method without damaging the lower layer wiring under the connection hole and thus without deteriorating the device characteristics. Can be formed. Therefore, a highly reliable device can be manufactured at low cost without increasing the manufacturing cost. In particular, when a novolac resin is used as the non-photosensitive organic material film, the material is inexpensive and can be easily removed by etching, which is effective.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional process diagram of a main part showing an embodiment of a wiring forming method of the present invention.

FIG. 2 is a schematic cross-sectional process diagram of a main part showing an embodiment of another wiring forming method of the present invention.

FIG. 3 is a schematic cross-sectional process diagram of a main part showing a conventional wiring forming method.

FIG. 4 is a schematic cross-sectional process diagram of a main part showing another conventional wiring forming method.

FIG. 5 is a schematic cross-sectional process diagram of a main part showing still another conventional wiring forming method.

[Explanation of symbols]

11, 15 Interlayer insulation film 12 Lower layer wiring 13, 14 Plasma SiN film 16 Embedded metal wiring 17 Upper layer wiring 21, 23 resist pattern 23b resist 22 Novolac resin 24 Antireflection film

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 BB01 BB02 BB04 BB14 BB17                       BB18 BB19 BB24 CC01 DD07                       DD08 DD16 DD17 DD28 DD34                       DD37 DD43 DD52 DD75 EE05                       EE17 FF14 HH20                 5F033 HH09 HH11 HH12 JJ01 JJ11                       JJ12 KK01 KK04 KK05 KK06                       KK08 KK11 KK12 KK18 KK19                       KK21 KK25 MM01 MM02 MM07                       MM12 NN06 PP06 PP15 PP19                       PP33 QQ04 QQ09 QQ10 QQ13                       QQ21 QQ25 QQ28 QQ31 QQ46                       RR04 RR09 RR13 RR14 RR15                       SS04 SS08 SS11 SS15 SS21                       XX20 XX34                 5F046 PA17

Claims (6)

[Claims] 1. A process of forming an etching preventive film on a substrate on which a lower layer wiring is formed, a process of forming an interlayer insulating film on the substrate, and a process of forming an interlayer insulating film on the interlayer insulating film. A step of forming a connection hole; (d) a step of forming a non-photosensitive organic material film on the interlayer insulating film including the connection hole; and (e) while leaving the organic material film in the connection hole. A step of removing the organic material film on the interlayer insulating film, (f) forming a resist pattern having an opening in a region including the connection hole, and (g) using the resist pattern as a mask to form the interlayer A step of patterning the insulating film to form a wiring groove; (h) a step of removing the resist pattern, the organic material film and the etching prevention film; and (i) a conductive film embedded in the connection hole and the wiring groove. ,
And a step of forming an upper layer wiring reaching the lower layer wiring. 2. The non-photosensitive organic material film of step (d) comprises
The method according to claim 1, which is a novolac resin. 3. The method according to claim 1, wherein the removal of the organic material film in step (e) is performed by wet etching with an alkaline developer. 4. The method according to claim 1, wherein the etching prevention film in step (a) is a silicon nitride film. 5. The method according to claim 1, wherein the steps (d) to (f) are performed in a series of sequences in a spinner device having a coating cup, a developing cup and a bake plate. 6. Further, after the step (e) and at the step (f).
The method according to any one of claims 1 to 4, wherein an antireflection film is formed on the connection hole and on the interlayer insulating film before the step.