JP2003288561A - Ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an IC card which enables initial response data to speedily be updated if the initial response data, registered in a ROM, etc., as a memory whose storage contents are unrewritable, need to be altered afterward. <P>SOLUTION: In a nonvolatile memory, a reset response EF for writing new initial response data is provided and when a reset signal is received from outside, it is decided whether the new initial response data are written in the reset response EF; when the new initial response data are written in the reset response EF, the initial response data written in the ROM and the new initial response data in the reset response EF are read out and outputted to the outside. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card equipped with a non-volatile memory, and more particularly to an ATR (Answer To Res
et) relates to an IC card capable of updating information.

[0002]

2. Description of the Related Art With the advent of IC cards having a built-in semiconductor memory or the like, the storage capacity has dramatically increased as compared with conventional magnetic cards and the like, and by incorporating a semiconductor integrated circuit device such as a microcomputer in the IC card. Since the information medium itself has an arithmetic processing function, the information medium can be given high security.

The IC card is an ISO (International Orga)
(IC for standardization) is internationally standardized. Generally, an IC card has an IC such as a semiconductor memory built in a card body made of plastic or the like as a base material.
A conductive terminal made of metal is provided on the card surface for connection with an external device, and the IC card is used by inserting it into a card slot of the external device for data communication between the IC card and the external device. It is a thing. This IC card is called a contact type IC card, and is particularly suitable for applications requiring reliable and safe communication such as mass data exchange and settlement business, such as credit cards and electronic wallets.

On the other hand, when applying to gate management such as entry and exit, authentication is the main content of communication and the amount of communication data is often small, so simpler processing is desired. A technique devised to solve this problem is a non-contact type IC card. This is a direct current power source that provides a field for vibration energy such as high-frequency electromagnetic fields, ultrasonic waves, and light in the space, absorbs and rectifies the energy, and drives the electronic circuit built in the card. The frequency of the component is used as it is, or multiplied or divided to form an identification signal, and the identification signal is transmitted to the information processing circuit of the semiconductor element through a complex device such as a coil or a capacitor.

In particular, most of the non-contact type IC cards for the purpose of authentication and simple counting data processing have a battery and a CPU (Ce
ntral Processing Unit; wireless authentication of hardware logic without a central processing unit (so-called Radio Frequenc
With the advent of this non-contact type IC card, the security against forgery and tampering has increased compared to magnetic cards. Further, since this contactless card enables wireless communication with an external device, the card carrier carries the card when passing through a gate typified by a ticket gate at a station, for example. It is only necessary to bring the IC card close to the IC card reader / writer (hereinafter referred to as the card R / W) provided at the gate, and the gate can be easily passed without the troublesome work involved in passing through the conventional gate. be able to.

[0006] In recent years, a contact-type function having an external terminal of the former and a non-contact type function of communicating data by wireless communication of the latter have been provided for the purpose of supporting a multipurpose purpose with one card. A composite type IC card having the same has been devised.

[0007]

In the IC card as described above, when a data is transmitted / received to / from the card R / W which is an external device, a control program is usually generated by a reset signal from the card R / W. Activated, then card R
After receiving and decoding the command from / W and executing the processing corresponding to it, the processing result is output as response data to the card R / W, and then the standby state is entered. By the way, generally, the transmission protocol of an IC card differs depending on the model. Therefore, in order to notify the card R / W of the transmission protocol and the like, the IC card outputs initial response data called ATR (Answer To Reset) information to the card R / W after recognizing the reset release by the reset signal.

The ATR information is composed of transmission protocol specification information of the IC card and information unique to the IC card. Normally, in a manufacturing process of an IC chip mounted on the IC card, a mask ROM in the IC chip is used. Written in. Since the mask ROM is a non-rewritable memory, the ATR written in the mask ROM is
It is impossible to rewrite the information later.

However, after the IC card is issued, if it is desired to upgrade the software of the IC card or add new software to the IC card, it is necessary to update the ATR information registered in the ROM. Occurs. Although there are many scenes where the ATR information needs to be changed at present, in the conventional IC card, the A
Since the TR information could not be rewritten or added, it was not possible to deal with the data update or the like that occurs after the IC card is manufactured.

The present invention has been made in view of the above circumstances, and is a memory whose memory contents cannot be rewritten.
An object of the present invention is to provide an IC card capable of promptly updating the initial response data when it is necessary to change the initial response data registered in M or the like later.

[0011]

In order to achieve the above object, the present invention provides a non-volatile memory whose stored contents can be rewritten, a central processing unit for controlling the non-volatile memory, and a protocol unique to the card. An IC having a ROM in which initial response data for notifying outside is stored in advance
An IC card is provided which is provided with a file dedicated to writing initial response data for writing new initial response data in the nonvolatile memory.

The invention described in claim 2 is the same as claim 1.
In the IC card according to [4], when a reset signal is received from the outside, it is determined whether or not new initial response data is written in the initial response data write-only file, and the initial response data write-only file is written. If new initial response data is written in the ROM, the initial response data written in the ROM and the new initial response data in the initial response data write-only file are read and output to the outside. It is characterized by

Typical applications of the IC card of the present invention include, for example, cash cards, credit cards, passbooks, seal stamp certification cards, basic resident register cards, pension notebooks, and driver's licenses in financial relations. Certificates, passports and certificates of qualification are examples. Further, as the gift certificate, prepaid card, and stock certificate related to securities, a fixed-price ticket, a coupon ticket, an ETC card, a fare settlement ticket, a toll road ticket, and the like related to transportation are given as examples. In the medical field, health insurance card, medical certificate, mother and child certificate, medical chart, medical history certificate, personal medical certificate (enter blood type, prohibited drug information, etc.), blood donation certificate, etc. In the field of, employee ID, membership ID, insurance policy, point card, ID card,
Examples are student ID cards, gradebooks, salary schedules, attendance / receipt management cards, electronic keys, entry / exit management cards, library usage cards, equipment usage certificates, facility usage certificates, cafeteria usage certificates, various payment cards, telephone directories, police notebooks, etc. As.

[0014]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, contact type, non-contact type,
An outline of the basic structure, the basic operation, and the like of various IC cards of the composite type and the like will be described.

(1-1) Outline of Contact Type IC Card FIG. 20 shows a schematic view of a typical contact type IC card, and FIG. 21 shows an electric circuit configuration diagram of the contact type IC card. As shown in FIG. 20, in the contact type IC card 100, a terminal electrode 101 serving as an interface with an external device is attached to a part of the surface of a plastic card body, and an IC chip 102 is attached to the lower surface of the terminal electrode 101. ing. In addition, print characters and embossed characters 103 can be formed on the surface of the card body. In addition, in order to support the existing magnetic card system, the magnetic stripe 1
04 may be provided. The IC chip 10
As shown in FIG. 21, the electric circuit configuration 2 includes a CPU (Central Processing Unit) 105 and a memory. The memory includes a ROM (Read Only Memory) 106 and a RAM (Rand
om Access Memory (volatile memory) 107, EEPROM (E
lectrically Erasable Programmable ROM) 108 and the like. The ROM 106 stores I executed by the CPU 105.
The C card operation program is stored. Also, R
The AM 107 is used as a temporary storage area for data such as commands (commands) and a work area for the CPU 105. E
The EPROM 108 stores memory data and various settings. The CPU is connected via a bus of a predetermined width to read data from these memories and to write data.

The terminal electrode 101, which is an interface with an external device, has a power supply terminal Vcc and a ground terminal GND for supplying power from the outside, and a reset signal terminal RST for receiving a reset signal from the outside.
And an I / O terminal for transmitting and receiving data to and from the outside, and a clock terminal CLK for receiving a system clock signal from the outside.

Further, the CPU 105 is a ROM based on Vcc (power supply voltage), RST signal (reset signal) and CLK signal (clock signal) supplied from an external device.
The program stored in 106 is read and executed, and R
Data is written to and read from the AM 107 and the EEPROM 108, commands and write data, etc. are received from an external device via the I / O terminal, and processing results and read data as a response from the IC card are received. And so on. Since the contact type IC card 100 has a large storage capacity, software can be installed in the contact type IC card 100. Therefore, it is possible to realize multiple functions with one IC card. It also has excellent security,
It has the feature that counterfeiting and unauthorized use are difficult.

(1-2) Outline of non-contact type IC card The basic structure and basic principle of the non-contact type IC card will be described below with reference to the drawings. As shown in FIG. 22, the non-contact type IC card 109 has an IC chip 110, a coil 117 and the like mounted inside the card body as indicated by a dotted line in the figure, and wirelessly transmits and receives data to and from an external device. Therefore, the contact type IC card 1 described above is provided on the surface of the IC card.
No terminal electrode 101 is required as in the case of No. 00. Next, FIG.
An electric circuit configuration of the non-contact type IC card 109 is shown in FIG. As shown in the figure, the non-contact type IC card 109 includes an IC chip 110 and a resonance circuit section 116. Above IC
The chip 110 includes a CPU (central processing unit) 111 and an R.
OM112, RAM113, EEPROM114 and R
The F circuit 115 is mounted. The IC chip 11
A bypass capacitor (not shown) may be provided to stabilize the power supply of 0.

The resonance circuit section 116 is composed of a coil 117 and a capacitor 118, and its resonance frequency is set to be equal to the frequency of the high frequency electromagnetic field emitted by the external device 120. As a result, it is directly electromagnetically coupled to the transmitting / receiving antenna of the external device 120 to enable reception of electric power and transmission / reception of information. The IC chip is developed and designed by each company, and depending on the product design of the IC chip, there is an example in which the step of adjusting the resonance frequency as described above is not necessarily required when the IC chip is mounted on the non-contact type IC card. Of course, in that case, there is no need for such a step of providing electric parts for adjusting the resonance frequency.

Here, a non-contact type IC is connected from the external device 120.
The operation of the coil 117 when transmitting power and information to the card 109 will be described below. External device 1
A high-frequency signal (not shown) generated by the transceiver circuit 20 induces a high-frequency electromagnetic field in the transceiver coil inside the external device 120, and the high-frequency signal is radiated into space as electromagnetic energy. At this time, the non-contact type IC card 1
09 is located in this high frequency electromagnetic field, the external device 12
A high-frequency electromagnetic field generated by the 0 transmission / reception coil causes a high-frequency current to flow in the resonance circuit section 116 in the non-contact type IC card by electromagnetic induction. As a result, the non-contact type IC card 109 obtains an electromotive force. Where coil 1
The resonance frequency of the resonance circuit unit 116 formed by 17 and the capacitor 118 is set so as to sharply resonate with the frequency of the high-frequency electromagnetic field emitted by the external device 120. As a result, the maximum electromagnetic energy can be received from the external device 120. Further, since the resonance circuit unit 116 forms a closed loop, it can hold the received energy as accumulated energy.

As a method of forming the coil 117, a method of forming a copper foil or an aluminum foil by etching, printing a silver paste, or winding an electric wire is known, and a method of forming the capacitor 118. As a method, there is known a method in which an antenna is used as a flexible substrate and electrodes are attached to both surfaces of the substrate to form a capacitor, and a method in which a film capacitor or a ceramic capacitor is mounted. The coil 117 and the capacitor 118 are shown in FIG.
In addition to the case of being formed outside the IC chip 110 as shown in FIG. 3, there is a technique of forming inside the IC chip 110. The technique described above can also be applied to a composite IC card described later.

Further, as a method of manufacturing the non-contact type IC card 109, generally a laminating technique is known. In this laminating technique, a plurality of thermoplastic sheets are stacked and arranged between two plates of a press, and a non-contact type IC chip 110 is arranged in the middle thereof. This I
The C chip 110 is electrically connected to the coil 116 surrounding the IC chip 110 in advance. After the arrangement, heat and pressure are applied to weld the plurality of thermoplastic sheets to integrate the IC chip 110 and the thermoplastic sheets,
The non-contact type IC card 109 is manufactured. In addition to the above laminating technology, for example, a rectangular frame matching the size of the card is provided between the thermoplastic sheets,
The IC chip 11 previously connected to the coil 117 is provided in the cavity formed by the frame and the intermediate sheet.
0 is installed, thermosetting resin is injected into the cavity, and then
There is also a manufacturing method in which this cavity is covered with the thermoplastic sheet. Note that the arrangement of the antenna (generally having a coil shape in general) and the IC chip is not limited to the above example,
You may design appropriately. Further, the antenna and the IC chip do not necessarily need to be connected by a conductor.
Data transmission / reception between the antenna and the IC chip may be performed using an electrical engineering technique such as transformer coupling.

The above-mentioned non-contact type IC card 109 is not easily affected by the outside world such as dirt, dust, starting, etc.
It has features such as excellent operability and terminal maintenance. Further, since information can be exchanged without contacting the external device 120, it is excellent in convenience and maintainability, and can be effectively used as a ticket for railways, for example.

(1-3) Overview of composite type IC card The composite type IC card is a combination of the contact type and non-contact type described above. In addition to being called a composite IC card, it may also be called a hybrid IC card, a combination IC card, or a combination card. In addition, the composite IC card can be
Divided into dual interface type and integrated type.

The dual interface type has a contact type and a non-contact type interface, but a CPU,
This type shares a memory (ROM, RAM, EEPROM, etc.). For example, one IC chip is provided with two types of interface functions, contact type and non-contact type, and an OS (operating system), and one CPU shares a memory. A dual interface IC card,
It is also called a dual IC card or dual card. On the other hand, the integrated type has two IC chips, a contact type IC chip and a non-contact type IC chip, and does not share the CPU and the memory.

Since the composite IC card has the two functions of the contact type and the non-contact type described above, it can be widely used according to the application. That is, credit card, cash card, product sales, high-value payment such as authentication use, authentication service, terminal access control, point service, and contact sales IC card preferred product sales, food and drink use It can be effectively used for small amount payment, entrance / exit management, gate use, attendance management, attendance management, point service card, commuter pass, ticket, etc.

Next, FIG. 24 shows an electric circuit configuration of a typical dual interface type composite IC card 220 (hereinafter, simply referred to as composite IC card). As shown in the figure, the composite IC card 220 is
A CPU 121 for controlling the entire C card, and a ROM 122 in which fixed data such as a boot program is recorded in advance.
The EEPROM 123, which is a non-volatile memory capable of electrically writing and erasing data, the RAM 124, which temporarily stores various data, and the terminal electrode of an external device, are used to transmit and receive power and data. A terminal electrode 125 as a contact type interface (I / F),
A resonance circuit unit 126 as a non-contact type interface (I / F) and an RF circuit 127 interposed between the resonance circuit unit 126 and the CPU 121 are provided.

The terminal electrode 125 functioning as a contact type interface has a power supply terminal Vcc and a ground terminal GND for supplying power from the outside and a reset signal terminal RST for receiving a reset signal from the outside.
And an I / O terminal for transmitting and receiving data to and from the outside, and a clock terminal CLK for receiving a system clock signal from the outside. The above-mentioned metal terminals are arranged on the surface of the IC card, and by electrically contacting these terminals with the contact type card R / W which is an external device, power supply and data transmission / reception are performed. I do.

On the other hand, the resonance circuit section 126 functioning as a non-contact type interface is composed of a coil-shaped antenna and a capacitor formed inside the IC card, like the non-contact type IC card shown in FIG. The electric power can be supplied and data can be transmitted and received by radio waves with the non-contact type card R / W which is an external device. According to the resonance circuit section 126, since the IC card body does not contact the card R / W, the wear portion is small, the life of both the card R / W and the IC card is extended, and the antenna is installed inside the IC card. Therefore, there are advantages that all the front and back surfaces of the card can be used for printing, and reading and writing can be performed on a plurality of IC cards almost at the same time.

In the ROM 122, an operating system compatible with a contact type interface,
An operation system corresponding to the non-contact type interface is stored respectively. Also, EEPRO
The M123 stores an application operating on the contact type operation system or the non-contact type operation system, authentication key information, data and the like.

Next, FIG. 25 shows the composite type IC card 22.
The structure of 0 is shown. FIG. 25 (a) shows the entire structure, and FIG. 25 (b) is a transverse cross-sectional view across the composite type IC module mounting portion. In the figure, the coil 128 constituting the resonance circuit section 126 is formed in a printed pattern on the surface of a sheet-shaped resin, and the capacitor 129 is opposed to the front and back sides via a sheet-shaped resin dielectric. It consists of parallel plates.

The composite type IC module 130 is a composite type I module.
It is composed of a C chip 131, a module substrate 132, and a terminal electrode 125. The composite IC chip 131 includes the CPU 121, the ROM 122, and the EEPROM shown in FIG.
It is an IC chip in which the M123, the RAM 124, and the RF circuit 127 are built. The composite IC chip 131 and the terminal electrode 125 are mounted on different surfaces of the module substrate 132, and after they are circuit-connected to each other through the through holes,
The composite IC chip 131 is resin-sealed. As a result, the composite IC module 130 is completed.

Subsequently, a resonance circuit portion 126 composed of a capacitor 129 having a parallel plate pattern facing the coil 128 by the printed pattern is formed on a resin substrate, and a flexible antenna substrate 134 functioning as a coil is prepared. . Although the coil 128 is formed by a printed pattern here, it may be formed by winding a conductive wire coated with an insulating material. In addition, the antenna substrate 13
As the resin of No. 4, not only vinyl chloride but also polyimide, polycarbonate, PET, etc. can be applied, and the material is not fixed to one kind.

Then, the antenna substrate 13 is formed by injection molding.
4 is enclosed and the card substrate 135 is manufactured. When molding
The antenna substrate 134 is arranged such that the resonance circuit section 126 and the mounting position of the composite IC module 130 are at predetermined positions. In addition, a card substrate 135 formed by injection molding
Simultaneously with the production of the above, the fitting hole 136 of the composite type IC module 130 is formed in the surface of the card substrate 135.
Finally, the composite IC module 220 is completed by adhering the composite IC module 130 to the fitting hole 136 of the composite IC module of the card substrate 135 with a conductive paste or the like. In addition to vinyl chloride as a card substrate,
Any material such as polycarbonate that has sufficient strength and card characteristics such as embossability can be applied to the present invention.

In FIG. 25A, the card substrate 13
Although 5 is drawn separately on the front surface and the back surface, they are originally integrated, and here, the resonance circuit section 126 in the antenna substrate 134 enclosed in the card substrate 135 and the composite IC module 130 are attached. Fitting hole 13
It is modified in order to clearly explain the relationship with 6. In addition to the above-mentioned injection molding, any method can be applied to the production of the card as long as it is a method of maintaining the embossing characteristic. For example, a laminating method, an adhesive filling method, or the like is used. Further, the fitting hole 136 of the composite IC module 130 may be hollowed after the card is formed.

Next, FIG. 26 shows a plan view of the composite type IC card 220 compatible with embossing. In this example, the composite IC in which the coil 128 is mounted in the external terminal region 137
The external terminal area 137 is placed near the module 130.
The (composite type IC module 130) is arranged so as to be located outside the loop of the coil 128, and the embossed area 1
38, the external terminal area 137 is arranged so as not to interfere. This is very effective when the coil 128 has a spiral shape and the width of the coil 128 is wider than the gap between the embossed region 138 and the external terminal region 137 in order to obtain a predetermined inductance in the coil specifications. .

Next, in FIGS. 27A and 27B, inside the composite IC card 220 of the coil 128 in the composite IC card corresponding to the embossed area 138 or the composite IC card without the embossed area 138. Indicates the mounting position. The coil 128 is located substantially all around the card. Since the coil specifications at this time are arranged along almost the entire circumference of the card, it is possible to realize a predetermined inductance with a smaller number of turns than in the case of FIG. Further, the length of the coil 128 in the vicinity of the external terminal area 137 is arbitrary, and as shown in FIG.
It is also possible to arrange the external terminal region 137 so as to surround almost 3/4 of the circumference. In this case, the antenna substrate 134 is obtained by cutting out the resin sheet in the portion corresponding to the embossed region 138. This is aimed at not affecting the embossing properties.

Further, in FIGS. 26 and 27, the coil 12
Although the number of windings of 8 (loop state) was relatively uniform, as shown in FIG. 28, the number of windings of the coil 128 was extremely increased so that the difference between the outer diameter and the inner diameter was increased. Good. In FIG. 28, for example, the coil winding method is suitable when the frequency of the high-frequency electromagnetic field radiated by the external device is one digit to two digits lower than the frequencies in FIGS. 26 and 27.
When the frequency of the high frequency electromagnetic field is lowered, the inductance value of the coil 128 and the capacitance value of the capacitor 129 in the resonance circuit section 126 are naturally increased. Coil 1
The increase in the inductance of 28 leads to an increase in the number of turns, and in the spiral coil shape according to the print pattern, the difference between the outer diameter and the inner diameter becomes large, and the form shown in FIG.

(2) Outline of IC Card System Next, the configuration of the system side (external device side) for communicating with the IC card as described above will be described with reference to FIG. (2-1) Configuration of IC Card System As shown in FIG. 29, the IC card system generally includes a host computer 140, a terminal device 141, and a card R / W 142. Host computer 14
0 centrally controls the entire IC card system. The terminal device 141 is a host computer 140.
Are connected by communication lines, etc., and are distributed in many places. The card R / W 142 is installed in each store, for example, and functions as an interface between the IC card and the host computer 140 side. The card issuing device 143 may be connected to the host computer 140. Examples of the terminal device 141 include a personal computer, a cash dispenser terminal, an ATM terminal, an automatic vending machine, an entrance / exit gate, a POS (Point Of Sales) terminal, and a mobile phone in addition to a dedicated terminal that is specially made. Can be mentioned.

In the IC card system shown in FIG. 29, when a contact type card R / W (contact type or composite type as IC card) is used, a card R / W 142 is used as shown in FIG. When the IC card 144 is inserted, the terminal electrodes of the card R / W 142 and the 145
Comes into contact with the terminal electrode 146 of the IC card 144, and signals are transmitted and received through the terminal electrode. Specifically, a control signal is transmitted from the card R / W 142 to the IC card 144, and a response signal to this is sent to the IC card 144.
From the card to the card R / W 142. When writing information to the IC card, the card R / W 142 and I
Negotiate with C card,
When the W 142 obtains the write permission, the write data can be written by transmitting the write data to the IC card 144.

On the other hand, when reading information from the IC card 144, the card R / W 142 is the IC card 144.
It is possible to read out the desired information from the IC card 144 by transmitting a read request and information about a file desired to be read out to the IC card 144.

Further, in the IC card system shown in FIG. 29, when a non-contact type card R / W (non-contact type or composite type as an IC card) is used, as shown in FIG. By bringing the card 148 close to the card R / W 147, the card R / W 14 is electromagnetically induced.
It is possible to obtain the electromotive force from No. 7 and wirelessly communicate with the card R / W 147 as described above.

(3) From IC Card Manufacture to Issuance Next, the process from IC card manufacture to issuance is shown in FIG.
Will be described in order. First, in the IC card manufacturing process (step SP41 in FIG. 32), the IC card IC
The OS of the chip, the development of application software, the design process of the IC chip, the manufacturing process of the IC chip, the process of mounting the IC chip on a card such as plastic, and the process of printing characters and patterns on the IC card are performed. Then, the IC card manufactured in this way is given to the issuer,
Issuing processing is performed (step SP42).

In the issuing process, the card format (E
Initialization process of EPROM), CDF (Common Data Fil)
The process of generating e) is performed. The CDF also includes card attribute information, card issuer information, card owner information, application software access authority information, and PIN (Personal Identification Numbe).
r) Information (personal identification information) etc. is stored. Also, AD
F (Application Data File) is generated. The ADF stores information on access authority to files in the application, PIN information used in the application, and the like.

Then, the issue processing I as described above is performed.
The C card is given to the user, and the user can receive the service provided by the service provider by using the IC card (step SP43). In addition, at the time of first use,
The user may set a personal identification number or the like using the terminal.

(4) IC Card Memory Management Method Next, an embodiment of an IC card memory management method will be described with reference to FIGS. The memory management method here can be applied to each of the contact-type, non-contact-type, and composite-type IC cards described above.
Contact IC card 10 described in FIGS. 20 to 21.
A case where the memory management method of the present invention is applied to 0 will be described.

First, FIG. 33 shows the original international standard ISO / IE.
The basic file hierarchical structure defined by the C7816 series is shown. In this file structure, MF
(Master File) is the top file,
It is the only mandatory dedicated file that is the basis of the file structure. Under the MF, DF (Dedicated Fil
e) and EF (Elementary File) are configured. DF
Is a file that contains file control information and optional allocatable memory and can be the parent file for EFs and / or dedicated files. An EF is a data unit or a set of records having the same file identifier. A WF (Working EF) that stores application programs, data, etc., and an IEF (Internal EF) that stores an authentication key and encryption are is there. Then, the file having the hierarchical structure as described above is stored in the EEPROM as the non-volatile memory used in the various IC cards described above.

(4-1) File Hierarchical Structure According to This Embodiment Next, FIG. 1 shows a specific file hierarchical structure according to this embodiment. In this embodiment, the file shown in FIG. 1 is stored in the EEPROM 108 of the contact type IC card 100 shown in FIG.

This file hierarchical structure conforms to the original international standard ISO / IEC7816 series shown in FIG. 33, and its structure is such that the reset response EF, DF is subordinate to the MF arranged at the top of the file. Name management EF,
DF1 is connected, and EF2 and D are further subordinate to DF1.
It has a hierarchical structure in which F2 is connected and EF3 and EF4 are connected under DF2. In addition, above the MF,
A system directory sys for managing the state of the memory map of the EEPROM that stores the MF and files existing under the MF is generated.

(4-2) Layout of directories and files according to the present embodiment And each file is managed by the directory. The directory has a layout as shown in FIG. 2, and a directory creation / deletion flag FLG indicating whether the directory is created or deleted, a file ID (file number) FID, Register the start sector (partition) number (start logical address) TOP of the file under it, the last sector (partition) number (final logical address) BTM of the file under it, and the file size (total number of sectors) VLM. It has a memory area. Further, a file name can be given to the above-mentioned DF, and the layout of the memory area in which the file name is written has a directory generation / deletion flag FLG and a top logical address TOP of the DF directory as shown in FIG.
_D and a memory area for storing the ID name (DF name) of the file.

In the present embodiment, file creation and deletion are handled with one sector (one section) consisting of 32 bytes as a minimum unit. In addition, the above directory requires one sector in principle.

(4-3) File Generation Below, the file hierarchical structure shown in FIG. 4 and FIGS.
The file generation process will be described with reference to the transition diagram of the memory map of the EEPROM shown in FIG. Note that FIG.
Is a directory in the file structure shown in FIG.

First, FIG. 5 shows a memory map in the initial state of the EEPROM (nonvolatile memory). As shown in FIG. 5, the memory area of the EEPROM is divided into a file area and a FAT (file allocation table) area (file management area). In this embodiment, physical addresses “h'000000” to “h'049990” are assigned to the file area, and physical addresses after “h'050000” are assigned to the FAT area.

In the file area, a logical address is assigned to each sector consisting of 32 bytes. In the figure, addresses starting with "h '" indicate physical addresses, and addresses starting with "#" indicate logical addresses. Here, the logical address is EEPR
It is not an address actually assigned on the OM but a virtual (logical) address used on a program to manage a file, and is expressed in hexadecimal. On the other hand, the physical address is an address assigned for each byte and is expressed in hexadecimal.
Since hardware uses physical addresses, it is necessary to perform conversion processing between physical addresses and logical addresses on software.

On the other hand, in the FAT area, sector (section) Y
A management sector F corresponding to each of the above is provided, and the usage state of the corresponding partition is registered in each of the management sectors F. The sector Y and the management sector F corresponding to each other are identified by the same logical address, and the numbers shaded in the figure indicate:
It is a logical address assigned to each management sector F in the FAT area.

The logical address in the FAT area (the shaded area in the FAT area) does not actually exist on the memory map. Further, since the management sector F in the FAT area is composed of 2 bytes, a logical address is allocated every 2 bytes.
In the FAT area, one row is represented by 16 bytes, and thus two rows represent 32 bytes corresponding to one sector Y.

Further, in FIG. 5, the initial value "FFFF" is stored in all the memory areas. This state is E
This shows a state where no data is stored in all the memory areas of the EPROM, and corresponds to the state of the EEPROM before formatting, that is, immediately after manufacturing. In addition, "FFF
In some cases, "0000" is stored in place of "F".

Subsequently, the contact type IC card 100 is inserted into an external device (for example, the card R / W 142 in FIG. 43), whereby a format execution command and the number of sectors to be secured are input via the I / O terminal. Is received,
The CPU 105 in the IC card executes the formatting process for the EEPROM 108 in the initial state shown in FIG.

In this format execution process, first, the number of free sectors that have received the command is secured in the file area, and the management sector F corresponding to the secured free sector is FAT.
Generate in the area. Then the system directory (SY
S) and the MF directory (MF) are generated in the reserved free sector. Hereafter, the number of free sectors to be secured is 256
A case where a sector is designated will be described.

<Linking of Management Sectors> First, in the file area, in order to secure the empty sectors for 256 sectors of the logical addresses “# 0000” to “# 00FF”, the management sectors respectively corresponding to the reserved free sectors are secured. It is generated in the FAT area. Specifically, "* 0001" is registered as the link information to the next logical address in the management sector of "# 0000" in the FAT area, and "* 0001" is registered to the subsequent "# 0001" as the link information of the next logical address. * 0002 ”is registered. Similarly, link information to the next logical address is registered in each management sector, and the logical address "# 00FF" corresponding to the last sector is registered.
“FFFF” indicating the final code is registered in the management sector of. In this way, by registering link information to the next logical address in each management sector, 256 consecutive sectors of logical addresses "# 0000" to "# 00FF" are secured as free sectors.

<Generation of System Directory (SYS)>
Subsequently, the CPU 105 causes the system directory (SYS) located at the top of the file structure shown in FIG.
Is executed (SP1 in FIG. 4). First, the start physical address of the file area "h'000000" to "h'00001F"
A system directory is created in the first sector consisting of. This is done by writing "01" to the directory creation / deletion flag storage area of the first sector (hereinafter simply referred to as FLG) to indicate that a directory has been created,
Next, write "# 0000", which is the start logical address of the current empty sector, to the start sector number (start logical address) storage area TOP (hereinafter simply referred to as TOP), and write the last sector number storage area BTM (hereinafter , Simply described as BTM) is "# 00FF" which is the final logical address of the empty sector.
Is written to the file size storage area VLM (hereinafter simply referred to as VLM), which is the current free sector number "010".
Write "0". This sector number is also in hexadecimal notation. As a result, as shown in FIG. 6, the system directory is generated in the first sector, and "256" sectors from "# 0000" to "# 00FF" in the current file area are reserved as free areas. .

<Generation of MF Directory (MF)> Subsequently, the CPU 105 performs an MF directory generation process (SP2 in FIG. 4). First, of the free sectors currently secured, the first one sector is reserved for MF directory generation, and the logical address described in TOP of the system directory is read (see FIG. 6). As a result,
When the logical address “# 0000” is acquired, the final code “FFFF” is registered in the management sector of the FAT area identified by this logical address (see FIG. 7), and the sector identified by the logical address is described above. Disconnect from the free sector link that you made. As a result, the sector with the logical address “# 0000” can be reserved for generating the MF directory.

Subsequently, of the 256 empty sectors, 1
The fact that the sector is reserved for MF directory generation is reflected in the system directory. That is, by securing one sector for generating the MF directory, the leading logical address of the empty sector shifts from "# 0000" to "# 0001", and the number of sectors decreases by 1 to "255". Therefore, to register this fact in the system directory, "# 0001" is set in the TOP of the system directory and the number of sectors is set to "25" in the VLM.
Write "00FF" indicating "5". Since the last sector is not changed, the BTM remains "# 00FF".

Subsequently, the CPU creates the MF directory in the sector of the secured logical address "# 0000". That is, the FLG shows "0" to indicate that the directory has been created.
Register 1 ”. Since no files exist under the MF directory, the TO of the MF directory
The initial values of P, BTM, and VLM remain unchanged. By performing the above-described processing, the memory map of the EEPROM 108 will be in a state as shown in FIG.

<Reset response EF directory (R-EF)
Next, the CPU performs a process of generating a reset response EF directory (R-EF) under the MF directory (MF) (SP3 in FIG. 4). First, of the free sectors,
In order to secure the first sector for generation of the reset response EF directory, the logical address “# 0001” described in TOP of the system directory is read, and the final code is stored in the management sector of this logical address “# 0001”. Register "FFFF". As a result, the logical address "# 000
One sector identified by "1" can be separated from the linkage of empty sectors and reserved for reset response EF directory generation.

Subsequently, by securing the sector of the logical address "# 0001", the leading logical address of the empty sector shifts to "# 0002", and the number of empty sectors is also decreased by 1. Therefore, that effect is stored in the system directory. To reflect
"# 0002" is registered in TOP of the system directory, and "00FE" indicating the number of sectors "254" is registered in VLM. Since the last sector is not changed, the BTM remains "# 00FF".

Subsequently, the CPU performs a process of reflecting the fact that the reset response EF directory is generated under the MF directory in the MF directory. Specifically, first,
In order to determine whether or not a file already exists under the MF directory, "FFF is added to the BTM of the MF directory.
Judge whether "F" is registered. As a result, as can be seen from FIG. 7, “FFF is added to the BTM of the MF directory.
Since “F” is registered, the CPU 105 sets the information of one sector secured for the reset response EF directory to M
It is reflected as it is in the F directory.

Specifically, "#" is added to the TOP of the MF directory.
Write "0001", write "# 0001" to BTM, and write "0001" to VLM. As a result, a file is created under the MF directory, and the file has a logical address "# 0001".
It is possible to indicate that the data is stored in the sector.

Subsequently, the CPU registers "01" in the FLG of the sector of the logical address "# 0001" so as to generate the reset response EF directory in the sector of the secured logical address "# 0001". Since files and the like do not exist under the reset response EF directory, TOP, BTM, and VLM in the reset response EF directory remain at their initial values. By performing the processing described above, the EEP
The memory map of the ROM 108 is as shown in FIG.

<Write of EF1> Subsequently, the CPU performs a process of writing EF1 under the reset response EF directory (R-EF) (SP4 in FIG. 4). First, the address “# 0002” stored in the TOP of the system directory is read, and this logical address is used as the leading logical address to secure the number of sectors according to the size of the EF1 to be written. Here, 2 sectors, that is, “# 0002” to “#
In order to secure "0003" for EF1 storage, "FFFF" indicating the final code is registered in the management sector of the FAT area corresponding to the final logical address "# 0003" of the two secured sectors. As a result, the two sectors identified by the logical addresses “# 0002” to “# 0003” can be separated from the free sector linkage and reserved for EF1 storage.

Then, logical addresses "# 0002" to "# 000" are entered.
By securing 2 sectors of "3", the top logical address of the free sector moved to "# 0004" and the number of free sectors decreased by 2. Therefore, in order to reflect that fact in the system directory, it is added to the top of the system directory. "# 0004"
"00FC" indicating the number of sectors "252" is registered in the VLM. As for the last sector, there is no change, so BT
M remains "# 00FF".

Subsequently, the CPU sets EF1 to reset response E
The reset response EF directory reflects that it is generated under F. Specifically, first, it is determined whether or not "FFFF" is registered in the BTM of the reset response EF directory. As a result, as can be seen from FIG.
Since "FFFF" is registered in BTM, the CPU
Reset response E for the information of 2 sectors secured for F1 storage
It is reflected as it is in the F directory.

Specifically, the reset response EF directory has "# 0002" in the TOP, "# 0003" in the BTM, and "0002" in the VLM.
Write. As a result, it can be shown that a file is generated under the reset response EF and that the file is stored in the sectors of the logical addresses “# 0002” to “# 0003”. Then, the CPU writes EF1 in the secured logical addresses “# 0002” to “# 0003”. By performing the above-described processing, the memory map of the EEPROM 108 becomes the state shown in FIG.

<DF name management EF directory (DF-EF)
Next, the CPU 105 causes the MF directory (M
A DF name management EF directory (DF-EF) is created under F) (SP5 in FIG. 4). First of all, in order to reserve the first sector of the currently reserved free sectors for generating the DF management EF directory, the TO of the system directory is
The logical address written in P is read (see FIG. 9). As a result, when the logical address “# 0004” is acquired, the final code “FFFF” is registered in the management sector of the FAT area identified by this logical address, and the sector identified by the logical address is freed as described above. Disconnect from the sector link. As a result, the logical address "# 000
The 4 "sector can be reserved for generating the DF name EF directory.

Subsequently, by securing the sector of the logical address "# 0004", the leading logical address of the empty sector shifts to "# 0005", and the number of empty sectors is also decreased by 1. Therefore, the fact is stored in the system directory. To reflect
"# 0005" is registered in TOP of the system directory, and "00FB" indicating the number of sectors "251" is registered in the VLM (see FIG. 10). There is no change in the last sector, so
BTM remains “# 00FF”.

Subsequently, the CPU 105 executes the MF command to generate the DF name management EF directory under the MF directory.
Perform the process to reflect in the directory. Specifically, first, it is determined whether or not "FFFF" is registered in the BTM of the MF directory. As a result, as can be seen from FIG. 9, since the information other than “FFFF” is registered in the BTM of the MF directory, the CPU uses the BT of the MF directory.
Update the information of “# 0001” written in M to the final logical address of the sector secured this time, “# 0004”,
Further, the newly secured sector 1 is reflected by updating the VLM information to “0002” (see FIG. 10).

Subsequently, the CPU 105 sets the management sector of the FAT area identified by the logical address "# 0001", which is the previous value (value before updating) of the BTM in the MF directory,
This time, the head logical address “# 0004” of the sector reserved for generating the DF name management EF directory is written.
That is, the information of the management sector of the logical address “# 0001” in the FAT area is rewritten from “FFFF” to “# 0004”.

Thus, as shown in FIG. 10, the CPU
The 105 can follow the logical address “# 0001” → “# 0004” by searching the FAT area based on the information “# 0001” written in the TOP of the MF directory. It can be recognized that the information of “# 0001” and “# 0004” exists under the MF.

Subsequently, the CPU 105 generates the DF name management EF directory in the secured sector of the logical address "# 0004", in order to generate the F of the sector of the logical address "# 0004".
Register "01" in LG. Note that files and the like do not exist under the DF name management EF directory.
The initial values of TOP, BTM, and VLM of the name management EF directory remain unchanged. By performing the processing described above, the EEP
The memory map of the ROM 108 is as shown in FIG.

<Generation of DF1 Directory (DF1)> Subsequently, the CPU 105 sets D under the MF directory (MF).
Generate F1 directory (DF1) (SP in Figure 4
6). First, of the free sectors currently secured, in order to secure the first sector for generating the DF1 directory, the logical address described in TOP of the system directory is read (see FIG. 10). As a result, when the logical address “# 0005” is acquired, the final code “FFFF” is registered in the management sector of the FAT area identified by this logical address, and the sector identified by the logical address is freed as described above. Disconnect from the sector link. As a result, the sector with the logical address “# 0005” can be reserved for generating the DF1 directory.

Subsequently, by securing the sector of the logical address "# 0005", the leading logical address of the empty sector shifts to "# 0006", and the number of empty sectors is also decreased by 1. Therefore, the fact is stored in the system directory. To reflect
“# 0006” is registered in TOP of the system directory, and “00FA” indicating the number of sectors “250” is registered in VLM. Since the last sector is not changed, the BTM remains "# 00FF".

Subsequently, the CPU 105 performs a process of reflecting in the MF directory that the DF1 directory should be created under the MF directory. Specifically, first, MF
Judge whether "FFFF" is registered in the BTM of the directory. As a result, as can be seen from FIG.
Since information other than "FFFF" is registered in the BTM of the directory, the CPU writes the information of "# 0004" written in the BTM of the MF directory as "#" which is the final logical address of the sector secured this time. 0005 ”and also V
The newly secured sector 1 is reflected by updating the LM information to “0003” (see FIG. 11).

Subsequently, the CPU causes the BT in the MF directory to
Logical address "# 00" which is the previous value of M (value before update)
In the FAT area management sector identified by "04", this time, D
"# 0005", which is the head logical address of the sector reserved for F1 directory generation, is written. That is, the information of the logical address "# 0004" of the FAT area is changed from "FFFF" to "# 00".
05 ".

Thus, as shown in FIG. 11, the CPU
Is the information "#" written in the TOP of the MF directory.
By searching the FAT area based on the information “0001”, the logical address “# 0001” → “# 0004” → “# 0005”
You can follow the logical address "# 0001", "# 000"
It is possible to recognize that files and the like stored in the sectors identified by "4" and "# 0005" exist under the MF.

Subsequently, the CPU registers "01" in the FLG of the sector of the logical address "# 0005" in order to generate the DF1 directory in the sector of the secured logical address "# 0005". In addition, since files and the like do not exist under the DF1 directory, TOP, BT of this directory
M and VLM remain at their initial values. The memory map of the EEPROM 108 is shown in FIG.
The state is as shown in 1.

<Registration of DF1 File Name> Next, DF
File name of 1 directory (DF) DF name management EF
Write processing under (DF-EF) (SP in Figure 4
7). A file name can be given to the DF.
Here, under the DF name management EF, which is a file that exclusively manages the file name given to the DF file,
The process of registering the DF name given to one directory is performed.

First, the address "# 0006" stored in the system directory TOP is read, and this logical address "# 0" is reserved in order to secure two sectors for registering the file name of DF1 with this logical address as the leading logical address.
The final code “FFFF” is registered in the management sector of the logical address “# 0007” corresponding to the second sector from “006”.
As a result, the two sectors identified by the logical addresses “# 0006” to “# 0007” can be separated from the free sector linkage and reserved for the file name registration of the DF1.

Then, the logical addresses "# 0006" to "# 000" are entered.
By securing 2 sectors of "7", the start logical address of the empty sector moved to "# 0008" and the number of empty sectors decreased by 2. Therefore, to reflect that fact in the system directory, it is added to the TOP of the system directory. "# 0008"
“00F8” indicating the number of sectors “248” is registered in the VLM. As for the last sector, there is no change, so BT
M remains "# 00FF".

Subsequently, the CPU 105 confirms that the file name of the DF1 is registered under the DF name management EF.
Perform the process to reflect in the directory. Specifically, first, it is determined whether or not "FFFF" is registered in the BTM of the DF name management EF directory. As a result, as can be seen from FIG. 11, since "FFFF" is registered in the BTM of the DF name management EF directory, the CPU uses the DF name management EF for the information of the two sectors reserved for the file name registration of DF1. Reflect it as it is in the directory. In particular,
DF name management "# 0006" at the top of the EF directory, BTM
Write "# 0007" to VLM and "0002" to VLM. As a result, the file name of DF1 is registered under the DF name management EF, and the file has logical addresses "# 0006" to "#".
It can be indicated that the data is stored in the sector “0007”.

Then, the CPU registers "01" in the FLG of the sectors of the secured logical addresses "# 0006" to "# 0007" and stores the head address storage area of the DF directory.
The top logical address “# 0005” of DF1 is written in TOP_D, and the file name of DF1 is written in the file name storage area. The layout of the sector for registering the file name is as shown in FIG. By performing such processing, the head logical address and file name of DF1 are registered in the DF name management EF, and thereafter managed. This enables DF search by file name, and DF1
It is possible to obtain the leading logical address information of and to access the DF1. By performing the above-described processing, the memory map of the EEPROM 108 becomes the state shown in FIG.

<Generation of EF2 Directory (EF2)> Subsequently, the CPU creates an E under the DF1 directory (DF1).
Perform the process to generate the F2 directory (SP in FIG. 4
8). First, of the empty sectors, the first one sector is EF2
In order to reserve for the directory (EF2) generation, the logical address "# 00" written in the TOP of the system directory
"08" is read and the final code "FFFF" is registered in the management sector of this logical address "# 0008". As a result, one sector identified by the logical address “# 0008” can be separated from the free sector linkage and reserved for the EF2 directory generation.

Subsequently, by securing the sector of the logical address "# 0008", the leading logical address of the empty sector shifts to "# 0009", and the number of empty sectors is also decreased by one. To reflect
"# 0009" is registered in the TOP of the system directory, and "00F7" indicating the number of sectors "247" is registered in the VLM. Since the last sector is not changed, the BTM remains "# 00FF".

Subsequently, the CPU 105 performs a process of reflecting the fact that the EF2 directory (EF2) is generated under the DF1 directory (DF1) in the DF1 directory. Specifically, first, it is determined whether or not "FFFF" is registered in the BTM of the DF1 directory. As a result, as can be seen from FIG. 12, “FFF is added to the BTM of the DF1 directory.
Since "F" is registered, the CPU directly reflects the information of one sector reserved for generating the EF2 directory in the DF1 directory. Specifically, "# 0008" is written in the TOP of the DF1 directory, "# 0008" is written in the BTM, and "0001" is written in the VLM (see FIG. 13). As a result, DF
It can be shown that a lower-level directory is generated under the control of 1, and the lower-level directory is stored in the sector of the logical address “# 0008”.

Subsequently, the CPU 105 writes "0" in the FLG of the sector of the logical address "# 0008" in order to generate the EF2 directory in the sector of the secured logical address "# 0008".
Register 1 ”. In addition, under the EF2 directory,
Since files and the like do not exist yet, the TOP, BTM, and VLM of the EF2 directory remain at their initial values. By performing the above-described processing, the memory map of the EEPROM 108 becomes the state shown in FIG.

<Write of EF2> Subsequently, the CPU writes E
A process of writing EF2 under the F2 directory (EF2) is performed (SP9 in FIG. 4). First, read the address "# 0009" stored in the TOP of the system directory,
Using this logical address as the head logical address, the number of sectors according to the size of the EF2 to be written is secured.
Here, 2 sectors, that is, “# 0009” to “# 000A” are EF
2 In order to secure the data for storage, “FFFF” indicating the final code is registered in the management sector of the FAT area corresponding to the secured final logical address “# 000A”. As a result, the two sectors identified by the logical addresses “# 0009” to “# 000A” can be separated from the free sector linkage and reserved for EF2 storage.

Then, the logical addresses "# 0009" to "# 000" are entered.
By securing 2 sectors of "A", the start logical address of the free sector moved to "# 000B" and the number of free sectors decreased by 2. Therefore, to reflect that fact in the system directory, it is added to the top of the system directory. "# 000B"
"00F5" indicating the number of sectors "245" is registered in the VLM. As for the last sector, there is no change, so BT
M remains "# 00FF".

Subsequently, the CPU 105 performs a process of reflecting in the EF2 directory that the EF2 is generated under the EF2 directory. Specifically, first, it is determined whether or not "FFFF" is registered in the BTM of the EF2 directory. As a result, as shown in FIG.
Since "FFF" is registered, the CPU directly reflects the information of the two sectors reserved for EF2 storage in the EF2 directory.

Specifically, "# 0009" is written in the TOP of the EF2 directory, "# 000A" is written in the BTM, and "0002" is written in the VLM (see FIG. 14). As a result, it can be shown that a file is generated under the EF2 directory and that the file is stored in the sectors of logical addresses “# 0009” to “# 000A”. Subsequently, the CPU 105 writes EF2 in the secured logical addresses “# 0009” to “# 000A”. By performing the processing described above, EEPRO
The memory map of M108 is as shown in FIG.

Subsequently, the CPU uses the same method to subordinate the DF1 directory (DF1) to the DF2 directory (DF2).
To generate the DF2 file name under the DF name management EF directory (DF-EF) (SP11 in FIG. 4), the EF3 directory (EF3 directory under the DF2 directory (DF2)). ) Is generated (SP12 in FIG. 4), EF3 directory (EF3)
Writing EF3 underneath (SP13 in FIG. 4), DF
2 directory (DF2) under the EF4 directory (E
F4) generation processing (SP14 in FIG. 4), EF4 writing processing under the EF4 directory (EF4) (S in FIG. 4)
Perform P15). As a result, the memory map of the EEPROM 108 becomes the state shown in FIG.

(5) Regarding ATR information Generally, the transmission protocol of the IC card differs depending on the model. Therefore, the IC card recognizes the reset release by the reset signal in order to inform the card R / W which is an external device of the transmission protocol and the like. , ATR (Answer To Reset) is output to the card R / W. After that, the IC card goes into a command waiting state. In this case, the initial response data is composed of the transmission protocol use information of the IC card and the information unique to the IC card, and is registered in the ROM as a unique parameter when the IC card is manufactured.

By the way, when the application such as the external device is changed after the IC card is issued to the user, it is necessary to change the ATR information registered in the IC card. In this case, since it is impossible to update the ATR information written in the ROM,
The changed ATR information is stored in a specific file in the EEPROM in which information can be rewritten, and thereafter, when a reset signal is received from an external device, the EEPROM is
The ATR information registered in the specific file in M is output.

Here, the EEP according to the embodiment of the present invention.
The memory hierarchical structure of the ROM is shown in FIG. Here, the reset response EF is a file provided in the EEPROM as a file dedicated to writing ATR information. Also,
The authentication EF stores information about an authentication key, which is necessary when rewriting the data in the reset response EF.
The ATR information rewriting process according to this embodiment described below can be applied to any of the contact type IC card, the non-contact type IC card, and the composite type IC card described above. The EEPROM in the following description means an EEPROM mounted in the IC chips of various IC cards.
OM, for example, when the present invention is applied to a contact type IC card, the EEPROM 10 shown in FIG.
8 is the EEPROM 114 when the present invention is applied to a non-contact type IC card. Similarly, in the composite IC card, it is the EEPROM 123.

In the following, with respect to the reset response EF of the EEPROM having the above-mentioned file structure, the AT is newly added.
The process of writing the R information will be described with reference to FIG. As a premise, the EEPROM reset response EF
Is the initial state.

First, the external device outputs a reset signal to activate the IC card (step SP in FIG. 17).
101). As a result, the IC that received the reset signal
The CPU in the card performs a process of reading the ATR information stored in the ROM or the EEPROM and transmits the read ATR information to the external device (step SP10).
2).

Now, the process of reading the ATR information will be described with reference to FIG. First, the CPU
ID added to reset response EF in EPROM
The reset response EF is searched based on the name (step SP201 in FIG. 18). Then, it is determined whether the data part of the reset response EF is in the initial state. (Step SP202). As a result, since the data portion of the reset response EF is in the initial state (for example, the data is all "F"), the CPU reads the ATR information registered in the ROM and outputs the read ATR information. (Step SP203, step SP102 of FIG. 17).

Subsequently, when the external device receives the ATR information, it then outputs an instruction to select the reset response EF to the IC card (step SP10 in FIG. 17).
3). In response to this instruction, the CPU in the IC card selects the reset response EF and notifies the external device to that effect (step SP104). Then, the external device outputs a new ATR information write request to the IC card. Upon receipt of this request, the CPU in the IC card uses the ATR information received with the request in step SP104.
The writing process is executed under the reset response EF directory selected in (see <Write of EF data 1 etc.> above). As a result, it becomes possible to write new ATR information under the reset response EF directory.

Next, a process of rewriting the ATR information written in the reset response EF in the EEPROM to new ATR information by performing the above-described process will be described with reference to FIG. First, the external device outputs a reset signal to activate the IC card (step SP111 in FIG. 19). This allows
Upon receiving the reset signal, the CPU in the IC card performs the processing shown in FIG.
ATR stored in reset response EF of PROM
The information is read and this ATR information is output to the external device (step SP112).

Then, the external device outputs an instruction to select the reset response EF (step SP113). As a result, the CPU in the IC card selects the reset response EF and notifies the external device to that effect (step SP1).
14). Subsequently, the external device outputs a read request for the ATR information stored in the data portion of the reset response EF (step SP115). As a result, the CPU of the IC card reads the ATR information from the data portion of the reset response EF and outputs it (step SP116). Then, the external device outputs a write request for ATR information (step SP117). I received a write request
The CPU of the C card outputs the information indicating that the write request is rejected, that is, the write-rejection error notification to the external device, because the write is not permitted until after the key authentication process is performed (step SP118). .

Subsequently, the external device outputs a request for rewriting the ATR information (step SP119). The CPU of the IC card that has received the write request can only permit the rewrite after the key authentication process is performed, and therefore outputs a notification that the rewrite request is rejected, that is, a rewrite refusal error notification. (Step SP12
0). Subsequently, the external device issues (outputs) the authentication key (KEY1) held by itself (step SP121).
The CPU of the IC card that received the information of this authentication key
If you check the information of the authentication key you have and confirm that both match or are a valid combination,
The rewrite access permission is stored in the RAM, and the fact that the rewrite request is permitted is output to the external device (step SP12).
2).

Subsequently, the external device which has received the notification that the rewriting request is permitted outputs the ATR information rewriting request (step SP123). As a result, the CPU of the IC card rewrites the ATR information stored in the data portion of the reset response EF with the ATR information (step SP124). The communication as described above is performed by the external device.
The reset response E is performed by being performed with the C card.
It becomes possible to rewrite the ATR information in F.

Although the embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and includes a design etc. within the scope not departing from the gist of the present invention. Be done.

[0112]

As described above, according to the IC card of the present invention, the initial response data write-only file for writing new initial response data is provided in the non-volatile memory. If it is necessary to change the initial response data registered in advance in the ROM, the initial response data can be updated by writing new initial response data in the rewritable nonvolatile memory. As a result, it becomes possible to notify the external device of the changed initial information, that is, the latest initial information of the IC card. Further, by providing a file dedicated to writing the initial response data exclusively for storing the initial response data, new initial response data can be easily read, and quick data communication with an external device can be realized.

Further, according to the IC card of the second aspect, when the reset signal is received from the outside, it is judged whether or not new initial response data is written in the file for writing initial response data. , If new initial response data is written in the file for writing initial response data, the initial response data written in the ROM and the new initial response data in the file for writing initial response data are read. Output to the outside. Since the initial response data is read from both the ROM and the non-volatile memory in this way, only the portion in which the original initial response data is changed needs to be registered in the initial response data write-only file. As a result, the amount of data registered in the initial response data file can be reduced, and the initial response data read processing can be performed quickly.

[Brief description of drawings]

FIG. 1 is a diagram showing a file hierarchical structure of an IC card according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout of a sector for generating a directory.

FIG. 3 is a diagram illustrating an example of a layout of a sector that stores a DF file name.

FIG. 4 is a diagram more specifically showing the file hierarchical structure shown in FIG.

FIG. 5 is a diagram showing a memory map of an EEPROM in an initial state.

FIG. 6 EE when a system directory is created
It is a figure which shows the memory map of PROM.

FIG. 7 is a diagram showing a memory map of an EEPROM when an MF is generated.

FIG. 8 is a diagram showing a memory map of an EEPROM when a reset response EF directory is generated.

FIG. 9 is a diagram showing a memory map of an EEPROM when EF1 is stored.

FIG. 10 is a diagram showing a memory map of an EEPROM when a DF name management EF directory is generated.

FIG. 11 EE when a DF1 directory is generated
It is a figure which shows the memory map of PROM.

FIG. 12 EE when the file name of DF1 is stored
It is a figure which shows the memory map of PROM.

FIG. 13 EE when an EF2 directory is created
It is a figure which shows the memory map of PROM.

FIG. 14 is a diagram showing a memory map of an EEPROM when EF2 is stored.

FIG. 15 shows the file hierarchical structure shown in FIG.
It is a figure which shows the memory map when creating it in M.

FIG. 16 is an E of an IC card according to an embodiment of the present invention.
It is a figure which shows the memory hierarchical structure of EPROM.

FIG. 17 is a flowchart showing a process for newly writing ATR information in a reset response EF of the EEPROM.

FIG. 18 is a flowchart showing a process of reading ATR information.

FIG. 19 is a flowchart showing a process of rewriting ATR information with new ATR information.

FIG. 20 is a schematic view of a typical contact type IC card.

FIG. 21 is an electrical configuration diagram of a contact type IC card.

FIG. 22 is a schematic view of a typical non-contact type IC card.

FIG. 23 is a diagram showing an electric circuit configuration of a non-contact type IC card.

FIG. 24 is a diagram showing an electric circuit configuration of a composite IC card.

FIG. 25 is a diagram showing a structure of a composite IC card.

FIG. 26 is a plan view of a composite IC card.

FIG. 27 is a diagram showing a mounting position of a coil in a composite IC card inside the composite IC card.

28 is a diagram showing a coil winding method suitable when the frequency of the high-frequency electromagnetic field radiated by the external device is one digit to two digits lower than the frequencies in FIGS. 39 and 40. FIG.

FIG. 29 is a diagram showing a configuration of a typical IC card system.

FIG. 30 is a diagram for explaining communication between an IC card and a card R / W when a contact type interface is used.

FIG. 31 is a diagram for explaining communication between an IC card and a card R / W when a non-contact type interface is used.

FIG. 32 is a diagram showing a process from manufacturing to issuing of an IC card.

FIG. 33 is a diagram showing a basic file hierarchical structure defined by the original international standard ISO / IEC7816 series.

[Explanation of symbols]

Y sector (section) F management sector (management section) 105, 111, 121 CPU (central processing unit) 106, 112, 122 ROM 107, 113, 124 RAM 108, 114, 123 EEPROM 101,125 Terminal electrode 116, 126 Resonant circuit unit 115,127 RF circuit 102,110 IC chip

Claims (2)

[Claims] 1. A non-volatile memory having rewritable storage contents, a central processing unit for controlling the non-volatile memory, and a ROM in which initial response data for notifying a protocol unique to the card to the outside is stored in advance. IC with and
An IC card, comprising: a file dedicated to writing initial response data for writing new initial response data in the nonvolatile memory. 2. When a reset signal is received from the outside, it is determined whether or not new initial response data is written in the initial response data write-only file,
When new initial response data is written in the file for writing initial response data, the ROM
2. The IC card according to claim 1, wherein the initial response data written in the file and the new initial response data in the file dedicated to writing the initial response data are read and output to the outside.