JP2003271570A5 - - Google Patents
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- JP2003271570A5 JP2003271570A5 JP2003039036A JP2003039036A JP2003271570A5 JP 2003271570 A5 JP2003271570 A5 JP 2003271570A5 JP 2003039036 A JP2003039036 A JP 2003039036A JP 2003039036 A JP2003039036 A JP 2003039036A JP 2003271570 A5 JP2003271570 A5 JP 2003271570A5
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- メモリ制御装置と、複数の第1の処理ユニットと、第2の処理ユニットとを有し、前記各々の第1の処理ユニットが、ローカルメモリを含むコンピュータプロセッサで、プログラムと前記プログラムと関連付けられたデータとを処理する方法において、
前記プログラムと、前記プログラムに関連付けられた前記データとを前記コンピュータプロセッサに接続可能なメイン・メモリに格納するステップと、
前記第2の処理ユニットを用いて、前記第1の処理ユニットの中の任意の処理ユニットに命じて前記プログラムの中の1つを処理するようにするステップと、
前記第2の処理ユニットを用いて、前記メモリ制御装置に命じて、前記メイン・メモリから前記ローカル・メモリへ、前記1つのプログラムと前記1つのプログラムと関連付けられたデータとを転送するようにするステップと、
前記1つの第1の処理ユニットのローカル・メモリから前記1つのプログラムの処理を開始するように、前記第2の処理ユニットを用いて、前記1つの第1の処理ユニットに指示するステップと、
前記指示に応じて、前記1つの第1の処理ユニットを用いて、前記ローカル・メモリから、前記1つのプログラムと前記1つのプログラムと関連付けられた前記データとを処理するステップと、を有することを特徴とする方法。 - 請求項1に記載の方法において、前記メイン・メモリがダイナミック・ランダム・アクセス・メモリであることを特徴とする方法。
- 請求項1に記載の方法において、前記メイン・メモリが、複数のメモリ・ロケーションであって、前記各々のメモリ・ロケーションが前記メモリ・ロケーションと関連付けられたメモリ・セグメントを含むように成す複数のメモリ・ロケーションを含むことを特徴とする方法。
- 請求項3に記載の方法において、前記メモリ・セグメントと関連するメモリ・ロケーションの中に格納されたデータの状態を示す状態情報と、第1の処理ユニットの識別子と、メモリ・アドレスとを前記各々のメモリ・セグメントの中に格納するステップをさらに有することを特徴とする方法。
- 請求項4に記載の方法において、前記状態情報が、前記メモリ・セグメントと関連するメモリ・ロケーションに格納された前記データの妥当性を示し、前記識別子が、前記第1の処理ユニットの中の特定の処理ユニットの識別子を示し、前記メモリ・アドレスが、前記特定の1つの第1の処理ユニットのローカル・メモリ内の格納位置を示すことを特徴とする方法。
- 請求項1に記載の方法において、前記第1の処理ユニットの各々が単一命令、複数データ・プロセッサであることを特徴とする方法。
- 請求項1に記載の方法において、前記第1の処理ユニットの各々が、1組のレジスタと、複数の浮動小数点演算ユニットと、前記1組のレジスタを前記複数の浮動小数点演算ユニットと接続する1以上のバスとを含むことを特徴とする方法。
- 請求項7に記載の方法において、前記第1の処理ユニットの各々が、複数の整数演算ユニットと、前記複数の整数演算ユニットを前記1組のレジスタと接続する1以上のバスとをさらに含むことを特徴とする方法。
- 請求項1に記載の方法において、前記コンピュータ・プロセッサが、光インターフェースと、前記光インターフェースと接続された光導波路とを有することを特徴とし、さらに、前記光導波路を介して前記コンピュータ・プロセッサから伝送するために、前記プロセッサによって生成された電気信号を、光信号に変換し、さらに、前記光導波路を介して前記プロセッサまで伝送された光信号を電気信号に変換するステップをさらに有することを特徴とする方法。
- 請求項1に記載の方法において、前記各々のローカル・メモリがスタティック・ランダム・アクセス・メモリであることを特徴とする方法。
- 請求項1に記載の方法において、前記コンピュータ・プロセッサが、レンダリング・エンジンと、フレーム・バッファと、表示制御装置とをさらに有することを特徴とし、さらに、前記レンダリング・エンジンを用いて画素データを生成するステップと、前記フレーム・バッファに前記画素データを一時的に格納するステップと、前記表示制御装置を用いて、前記画素データをビデオ信号に変換するステップと、をさらに有することを特徴とする方法。
- 請求項1に記載の方法において、前記1つのプログラムと関連付けられた前記データがスタック・フレームを含むことを特徴とする方法。
- 請求項1に記載の方法において、前記1つのプログラムと、前記1つのプログラムと関連付けられた前記データとの前記処理中、前記メモリ制御装置を用いて、前記1つの第1の処理ユニットから前記メモリ制御装置への命令に応じて、前記メイン・メモリから、前記1つの第1の処理ユニットのローカル・メモリへさらなるデータを転送し、次いで、前記1つの第1の処理ユニットの前記ローカル・メモリから、前記1つの第1の処理ユニットを用いて前記さらなるデータを処理するステップと、をさらに有することを特徴とする方法。
- 請求項1に記載の方法において、前記メイン・メモリが、複数のメモリ・バンク・コントローラと、前記第1の処理ユニットの各々と前記メイン・メモリとの間で接続を行うためのクロスバ交換機とを有することを特徴とする方法。
- 請求項1に記載の方法において、前記各々の第1の処理ユニットは、前記第1の処理ユニットが排他的に関連づけられた前記ローカルメモリからデータの読み出しを行うものであり
前記各々の第1の処理ユニットは、前記第1の処理ユニットが排他的に関連づけられてはいない前記ローカルメモリのいずれからのデータの読み出し、あるいは、書き込みも行うことを前記メモリ制御装置を用いて禁止するステップをさらに有することを特徴とする方法。 - 請求項1に記載の方法において、前記1つのプログラムと、前記1つのプログラムと関連付けられた前記データとの前記処理後に、前記1つの第1の処理ユニットから前記メモリ制御装置への命令に応じて、前記メモリ制御装置を用いて、前記メイン・メモリへ、前記1つのプログラムと、前記1つのプログラムと関連付けられた前記データの前記処理から結果として生じた処理データとを転送するステップをさらに有することを特徴とする方法。
- 請求項1に記載の方法において、前記メモリ制御装置がダイレクト・メモリ・アクセス・コントローラであることを特徴とする方法。
- 請求項1に記載の方法において、前記コンピュータ・プロセッサがネットワークと接続され、前記1つのプログラムがソフトウェア・セル内に含まれ、前記ソフトウェア・セルが、前記ネットワークを介して伝送されるすべてのソフトウェア・セルの中で、前記ソフトウェア・セルを一意的に識別するグローバルな識別子を含むことを特徴とする方法。
- メモリ制御装置と、複数の第1の処理ユニットと、第2の処理ユニットとを有し、前記各々の第1の処理ユニットがローカルメモリを含むコンピュータプロセッサであって、このコンピュータプロセッサは、当該コンピュータプロセッサに接続可能なメイン・メモリに格納されたプログラムと前記プログラムと関連付けられたデータとを処理するものであり、
前記第2の処理ユニットは、前記第1の処理ユニットのうち任意の処理ユニットに命じて、前記プログラムの中の1つを処理させるものであり、
前記メモリ制御装置は、前記第2の処理ユニットからの命令により、前記メイン・メモリから前記ローカル・メモリへ、前記1つのプログラムと前記1つのプログラムと関連付けられたデータとを転送するものであり、
前記第1の処理ユニットは、前記第2の処理ユニットからの指示により、当該第1の処理ユニットのローカル・メモリから前記1つのプログラムと前記1つのプログラムと関連付けられた前記データとの処理を行うものであることを特徴とするコンピュータプロセッサ。 - メモリ制御装置と、複数の第1の処理ユニットと、第2の処理ユニットとを有し、前記各々の第1の処理ユニットがローカルメモリを含むコンピュータプロセッサを有し、このコンピュータプロセッサによって、当該コンピュータプロセッサに接続可能なメイン・メモリに格納されたプログラムと前記プログラムと関連付けられたデータとを処理する装置であって、
前記第2の処理ユニットは、前記第1の処理ユニットのうち任意の処理ユニットに命じて、当該コンピュータプロセッサに接続可能なメイン・メモリに格納された前記プログラムの中の1つを処理させるものであり、
前記メモリ制御装置は、前記第2の処理ユニットからの命令により、前記メイン・メモリから前記ローカル・メモリへ、前記1つのプログラムと前記1つのプログラムと関連付けられたデータとを転送するものであり、
前記第1の処理ユニットは、前記第2の処理ユニットからの指示により、当該第1の処理ユニットのローカル・メモリから前記1つのプログラムと前記1つのプログラムと関連付けられた前記データとの処理を行うものであることを特徴とする装置。 - コンピュータネットワークと接続される複数のプロセッサを有するコンピュータ・システムであって、前記コンピュータプロセッサによって、当該コンピュータプロセッサに接続可能なメイン・メモリに格納されたプログラムと前記プログラムと関連付けられたデータとが処理されるものであり、
前記プロセッサのそれぞれが、メモリ制御装置と、複数の第1の処理ユニットと、第2の処理ユニットとを有し、
前記第1の処理ユニットのそれぞれは、ローカルメモリを含み、
前記第2の処理ユニットは、前記第1の処理ユニットのうち任意の処理ユニットに命じて、前記プログラムの中の1つを処理させるものであり、
前記メモリ制御装置は、前記第2の処理ユニットからの命令により、前記メイン・メモリから前記ローカル・メモリへ、前記1つのプログラムと前記1つのプログラムと関連付けられたデータとを転送するものであり、
前記第1の処理ユニットは、前記第2の処理ユニットからの指示により、当該第1の処理ユニットのローカル・メモリから前記1つのプログラムと前記1つのプログラムと関連付けられた前記データとの処理を行うものであることを特徴とするシステム。
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US09/816,004 | 2001-03-22 | ||
US09/816,004 US7233998B2 (en) | 2001-03-22 | 2001-03-22 | Computer architecture and software cells for broadband networks |
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JP2002079356A Division JP2002366533A (ja) | 2001-03-22 | 2002-03-20 | コンピュータ・ネットワーク及びコンピュータ可読媒体 |
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JP2003271570A JP2003271570A (ja) | 2003-09-26 |
JP2003271570A5 true JP2003271570A5 (ja) | 2005-09-08 |
JP4455822B2 JP4455822B2 (ja) | 2010-04-21 |
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JP2003039036A Expired - Lifetime JP4455822B2 (ja) | 2001-03-22 | 2003-02-17 | データ処理方法 |
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US (11) | US7233998B2 (ja) |
EP (2) | EP1370968B1 (ja) |
JP (2) | JP2002366533A (ja) |
KR (2) | KR100891063B1 (ja) |
CN (1) | CN100412848C (ja) |
TW (1) | TWI266200B (ja) |
WO (1) | WO2002077845A1 (ja) |
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