JP2003271569A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003271569A5 JP2003271569A5 JP2003043586A JP2003043586A JP2003271569A5 JP 2003271569 A5 JP2003271569 A5 JP 2003271569A5 JP 2003043586 A JP2003043586 A JP 2003043586A JP 2003043586 A JP2003043586 A JP 2003043586A JP 2003271569 A5 JP2003271569 A5 JP 2003271569A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/080,440 | 2002-02-22 | ||
| US10/080,440 US6874070B2 (en) | 2002-02-22 | 2002-02-22 | System and method for memory interleaving using cell map with entry grouping for higher-way interleaving |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003271569A JP2003271569A (ja) | 2003-09-26 |
| JP2003271569A5 true JP2003271569A5 (US07576130-20090818-C00114.png) | 2006-04-06 |
| JP4348093B2 JP4348093B2 (ja) | 2009-10-21 |
Family
ID=27803675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003043586A Expired - Lifetime JP4348093B2 (ja) | 2002-02-22 | 2003-02-21 | マップテーブルを用いてメモリにインタリーブ方式でアクセスする方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6874070B2 (US07576130-20090818-C00114.png) |
| JP (1) | JP4348093B2 (US07576130-20090818-C00114.png) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7577816B2 (en) * | 2003-08-18 | 2009-08-18 | Cray Inc. | Remote translation mechanism for a multinode system |
| US7421565B1 (en) * | 2003-08-18 | 2008-09-02 | Cray Inc. | Method and apparatus for indirectly addressed vector load-add -store across multi-processors |
| US7437521B1 (en) | 2003-08-18 | 2008-10-14 | Cray Inc. | Multistream processing memory-and barrier-synchronization method and apparatus |
| US7366873B1 (en) | 2003-08-18 | 2008-04-29 | Cray, Inc. | Indirectly addressed vector load-operate-store method and apparatus |
| US8307194B1 (en) | 2003-08-18 | 2012-11-06 | Cray Inc. | Relaxed memory consistency model |
| US7743223B2 (en) | 2003-08-18 | 2010-06-22 | Cray Inc. | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system |
| US7171499B2 (en) * | 2003-10-10 | 2007-01-30 | Advanced Micro Devices, Inc. | Processor surrogate for use in multiprocessor systems and multiprocessor system using same |
| US8806103B2 (en) | 2004-04-28 | 2014-08-12 | Hewlett-Packard Development Company, L.P. | System and method for interleaving memory |
| JP2006018489A (ja) * | 2004-06-30 | 2006-01-19 | Hitachi Ltd | 複数ノード間のメモリインターリーブシステム |
| EP1825433A4 (en) * | 2004-11-23 | 2010-01-06 | Efficient Memory Technology | METHOD AND APPARATUS FOR MULTIPLE INTERLAYING ADDRESSING INTERLACES OF PAGINATED MEMORIES AND INTELLIGENT MEMORY BANKS |
| US8190809B2 (en) * | 2004-11-23 | 2012-05-29 | Efficient Memory Technology | Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines |
| US7478769B1 (en) | 2005-03-09 | 2009-01-20 | Cray Inc. | Method and apparatus for cooling electronic components |
| US7657818B2 (en) * | 2005-06-22 | 2010-02-02 | Adaptive Spectrum And Signal Alignment, Inc. | Dynamic minimum-memory interleaving |
| KR101011171B1 (ko) * | 2005-12-28 | 2011-01-26 | 후지쯔 가부시끼가이샤 | 메모리 제어 방법, 기억 매체 및 장치와 정보 처리 장치 |
| US20070261059A1 (en) * | 2006-04-25 | 2007-11-08 | Orth Joseph F | Array-based memory abstraction |
| US20130232304A1 (en) * | 2012-03-05 | 2013-09-05 | Qualcomm Incorporated | Accelerated interleaved memory data transfers in microprocessor-based systems, and related devices, methods, and computer-readable media |
| US9256531B2 (en) * | 2012-06-19 | 2016-02-09 | Samsung Electronics Co., Ltd. | Memory system and SoC including linear addresss remapping logic |
| US11316713B2 (en) | 2019-11-25 | 2022-04-26 | International Business Machines Corporation | Virtual drawers in a server |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5293607A (en) | 1991-04-03 | 1994-03-08 | Hewlett-Packard Company | Flexible N-way memory interleaving |
| US5530837A (en) | 1994-03-28 | 1996-06-25 | Hewlett-Packard Co. | Methods and apparatus for interleaving memory transactions into an arbitrary number of banks |
| US5655113A (en) | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
| EP0931290A1 (en) * | 1997-03-21 | 1999-07-28 | International Business Machines Corporation | Address mapping for system memory |
| EP1050819A1 (en) * | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Computer memory access |
| US6526459B1 (en) | 1999-11-10 | 2003-02-25 | Ati International Srl | Allocation of input/output bus address space to native input/output devices |
| US6480943B1 (en) * | 2000-04-29 | 2002-11-12 | Hewlett-Packard Company | Memory address interleaving and offset bits for cell interleaving of memory |
| US6598130B2 (en) * | 2000-07-31 | 2003-07-22 | Hewlett-Packard Development Company, L.P. | Technique for referencing distributed shared memory locally rather than remotely |
-
2002
- 2002-02-22 US US10/080,440 patent/US6874070B2/en not_active Expired - Lifetime
-
2003
- 2003-02-21 JP JP2003043586A patent/JP4348093B2/ja not_active Expired - Lifetime
