JP2003258244A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2003258244A
JP2003258244A JP2002053204A JP2002053204A JP2003258244A JP 2003258244 A JP2003258244 A JP 2003258244A JP 2002053204 A JP2002053204 A JP 2002053204A JP 2002053204 A JP2002053204 A JP 2002053204A JP 2003258244 A JP2003258244 A JP 2003258244A
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JP
Japan
Prior art keywords
gate electrode
film
gate
drain
mask
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002053204A
Other languages
Japanese (ja)
Inventor
Keiko Kawamura
圭子 河村
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2002053204A priority Critical patent/JP2003258244A/en
Publication of JP2003258244A publication Critical patent/JP2003258244A/en
Application status is Pending legal-status Critical

Links

Abstract

[PROBLEMS] To provide a semiconductor device capable of reducing element capacitances such as a capacitance between a gate electrode and a drain wiring, a capacitance between a gate electrode and a drain diffusion region, and a capacitance between a gate electrode and a drain electrode, and a method for manufacturing the same. provide. SOLUTION: A gate electrode 5 mounted on a gate insulating film 4 is substantially a rectangular parallelepiped, and at least one pair of opposing sides of an upper part of the rectangular parallelepiped is cut out in a gate width (W) direction. . The formation of such a notch is performed by oxidation using a mask or dry etching such as CDE. With such a gate electrode structure, the distance between the gate electrode and the drain electrode (d1), the distance between the gate electrode and the drain wiring (d2), and the distance between the gate electrode and the drain diffusion region can be made larger than those of the conventional one having the same size. The capacity between them is reduced. Further, the processing is facilitated by heat treatment or chemical dry etching.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a gate electrode used in a semiconductor device such as a photorelay or a high-speed MOS device, and a method of manufacturing the same. 2. Description of the Related Art As the miniaturization and miniaturization of semiconductor devices progress, the influence of element capacitance on semiconductor characteristics cannot be ignored. Particularly in high-speed devices that require a reduction in element capacitance, it is most necessary to reduce the gate-drain capacitance. In that case, the gate electrode
It is difficult to reduce the capacity between the drain electrode, the capacity between the gate electrode and the drain n + diffusion region, and the capacity between the gate electrode and the drain electrode wiring, and there is a limit to the approach between them. FIG. 9 is a schematic schematic sectional view showing a gate electrode structure of a conventional semiconductor device. A semiconductor substrate 101 of silicon or the like is p-type and has an n-type source region 102 and an n-type drain region 103 exposed on the main surface. A gate electrode 105 made of polysilicon or the like is formed above the source / drain regions 102 and 103 via a gate insulating film 104 such as a silicon oxide film. [0003] This semiconductor device is manufactured by the following steps. First, a film of a gate electrode material such as polysilicon is deposited over the entire main surface of the semiconductor substrate via a gate insulating film such as a silicon oxide film. Next, a mask patterned in a gate electrode shape is disposed on the film of the gate electrode material. Then, a film of a gate electrode material is processed according to the patterned pattern to form a gate electrode. After removing the mask, impurities are implanted into the semiconductor substrate using the gate electrode as a mask, and the impurities are diffused by heat treatment or the like to form a source region and a drain region. A source electrode and a drain electrode are formed on each of the source region and the drain region. A gate sidewall insulating film made of a silicon oxide film, a silicon nitride film, or the like is formed on the side surface of the gate electrode as needed. Next, an electrode pad connected to the source electrode or the drain electrode is formed. [0004] Conventionally, the gate electrode has a substantially rectangular parallelepiped shape, and usually has a rectangular or nearly rectangular cross-sectional shape. In a semiconductor device having such a gate electrode, as the capacitance between the gate electrode and the drain wiring, the capacitance between the gate electrode and the drain diffusion region, and the capacitance between the gate electrode and the drain electrode increase, the lower the capacitance, the lower the capacitance. There was a problem that it could not be ignored. The present invention has been made in view of such circumstances, and a gate electrode
Provided are a semiconductor device and a method for manufacturing the same, which can reduce element capacitance such as capacitance between drain wiring, capacitance between gate electrode and drain diffusion region, and capacitance between gate electrode and drain electrode. [0005] The present invention is characterized in that the gate electrode is substantially a rectangular parallelepiped, and at least one pair of opposing sides of the upper portion of the rectangular parallelepiped is cut out. The formation of such a notch shape is performed by oxidation using a mask or chemical dry etching (C
DE is performed by isotropic etching such as chemical dry etching (WET) or wet etching. With such a gate electrode structure, each distance between the gate electrode and the drain electrode, the drain region, and the drain wiring connecting the drain electrode and the drain region can be increased as compared with a conventional gate electrode of the same size. Each capacitance between the gate electrode-drain electrode, the gate electrode-drain wiring, and the gate electrode-drain diffusion region is reduced. Further, by using heat treatment using a mask, isotropic etching, or the like, a process of giving a cutout shape to a gate electrode can be easily performed. That is, a semiconductor device according to the present invention is formed on a semiconductor substrate, a source / drain region formed on the semiconductor substrate, and a gate insulating film on the semiconductor substrate between the source / drain regions. Wherein the gate electrode is substantially a rectangular parallelepiped, and at least a pair of opposing sides of the upper portion of the rectangular parallelepiped are cut out. The cutout shape of the gate electrode may be formed at least along the gate width direction. The side surface of the gate electrode may be covered with a gate side wall insulating film. The method of manufacturing a semiconductor device according to the present invention includes the steps of: depositing a film of a gate electrode material over the entire main surface of a semiconductor substrate via a gate insulating film; and forming a mask patterned in a gate electrode shape on the gate electrode material film. Arranging,
The semiconductor substrate is heat-treated to oxidize the upper portion of the gate electrode material film, and the upper portion of the portion where the mask is disposed,
Oxidizing a predetermined distance from a peripheral portion to a central portion of the mask, processing a film of the gate electrode material in accordance with the pattern of the mask to form a gate electrode, and adding impurities to the semiconductor substrate. Implanting and diffusing to form a source region and a drain region; and forming a source electrode and a drain electrode connected to each of the source region and the drain region on the semiconductor substrate; Is a rectangular parallelepiped,
This rectangular parallelepiped is characterized in that at least one pair of opposing sides of the upper portion is cut out by a step of oxidizing the upper portion of the film of the gate electrode material. Further, a method of manufacturing a semiconductor device according to the present invention
Depositing a film of a gate electrode material on the entire surface of the semiconductor substrate through a gate insulating film, arranging a mask patterned in the shape of a gate electrode on the film of the gate electrode material; A region other than the region where the mask is formed is etched by a CDE method or a wet etching method to remove an upper part of the film of the gate electrode material. Removing the mask to a predetermined distance toward the center, processing the film of the gate electrode material in accordance with the pattern of the mask to form a gate electrode, removing the mask, Implanting and diffusing impurities to form a source region and a drain region; and forming the source region and the drain region on the semiconductor substrate. Forming a source electrode and a drain electrode to be connected to each other, wherein the gate electrode is a rectangular parallelepiped, and the rectangular parallelepiped has at least one pair of opposed upper sides cut out by the etching step. It is characterized by having. The method may further include a step of forming a gate sidewall insulating film on a side surface of the gate electrode, and the step of forming the drain region may be performed after the step of forming the gate sidewall insulating film. Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. 1 is a cross-sectional view of the semiconductor device, FIG. 2 is a perspective view of a gate electrode used in the semiconductor device of FIG. 1, and FIGS. 3 to 5 are cross-sectional views of a manufacturing process of the semiconductor device of FIG. The semiconductor substrate 1 is, for example, p-type silicon and has an n-type source region 2 and an n-type drain region 3 exposed on the main surface. A gate electrode 5 made of polysilicon or the like is formed between the source / drain regions 2 and 3 via a gate insulating film 4 such as a silicon oxide film. The main surface of the semiconductor substrate 1 and the gate electrode 5 are covered with an interlayer insulating film 12 such as a silicon oxide film. On the interlayer insulating film 12, a source electrode 6 and a drain electrode made of aluminum (first Al layer) or the like are provided. 7 are formed. The source electrode 6 and the drain electrode 7 are electrically connected to the n-type source region 2 and the n-type drain region 3 via wirings 8 and 9 embedded in contact holes formed in the interlayer insulating film 12. The wirings 8 and 9 are connected to the source /
The drain regions 2 and 3 are connected to n + contact regions 2 'and 3'. Further, although not shown, the source electrode 6 and the drain electrode 7 are covered with a protective insulating film such as a silicon oxide film. FIG. 2 is a schematic perspective view of the gate electrode shown in FIG. The gate electrode of this embodiment has a gate sidewall insulating film, a silicon nitride film formed on the upper surface of the gate electrode, and a thermal oxide film formed on the upper side surface of the gate electrode. The structure of the gate electrode itself will be described. Therefore, these descriptions are omitted in FIGS. 1 and 2. The semiconductor substrate 1 is disposed between the source region 2 and the drain region 3 with a gate insulating film 4 interposed therebetween. The gate electrode has a gate length in a direction where the source / drain regions face each other, and has a source / drain region.
Since the length in which the drain region faces is the gate width, the gate electrode 5 has a shape in which two upper sides facing each other and along the gate width direction are cut out. FIG. 5 (c)
FIG. 3 is a cross-sectional view illustrating a state of the semiconductor substrate until a drain region is formed. As shown in the figure, the gate electrode 5 has a gate sidewall insulating film 15, a silicon nitride film 14 formed on the upper surface of the gate electrode, and a thermal oxide film 15 ″ formed on the upper side surface of the gate electrode. As described above, since the gate electrode 5 has a shape in which two opposing upper sides are cut, the distance (d1) between the gate electrode 5 and the drain electrode 7 and the distance between the gate electrode 5 and the drain region The distance (d2) between the wiring 3 connecting the 3-drain electrode 7 or the distance between the gate electrode 5 and the drain region 3 is larger than that of the conventional substantially rectangular parallelepiped gate electrode. Next, the manufacturing process of the semiconductor device shown in Fig. 1 will be described with reference to Fig. 3 to Fig. 5. First, the semiconductor substrate 1 will be described.
To form a gate insulating film 4 made of a silicon oxide film on the main surface. A film 5 'of a gate electrode material made of a polysilicon film is formed on the gate insulating film 4 by a method such as CVD (FIG. 3A). Next, a thin silicon nitride film 14 is deposited on the gate electrode material film 5 'by a method such as CVD (FIG. 3B). Next, a photoresist 16 is applied on the silicon nitride film 14, and is patterned into a shape of a gate electrode (FIG. 3).
(C)). This patterned photoresist 16
The silicon nitride film 14 is patterned into a mask shape by wet etching or the like using
(A)). Next, the surface of the gate electrode material film 5 'made of a polysilicon film is oxidized by heat-treating the semiconductor substrate 1 in an oxidizing atmosphere. By this heat treatment, the upper portion of the film 5 'of the gate electrode material is oxidized and changed to a silicon oxide film 5 ".
Since the patterned silicon nitride film 14 has an effect of preventing oxidation, the silicon nitride film 14 under the silicon nitride film 14 remains without being oxidized. However, the masking action of the silicon nitride film 14 is not sufficient, and an oxidizing action proceeds in the peripheral portion. Therefore, the polysilicon film 5 'is in contact with the central portion of the silicon nitride film 14, but the oxidation proceeds toward the peripheral portion, and the thickness of the polysilicon film 5' is reduced. The oxide film under the silicon nitride film has a so-called bird's beak shape (FIG. 4B). Next, using the patterned silicon nitride film 14 as a mask, the polysilicon film 5 'and the silicon oxide
Patterning is performed by anisotropic etching such as E (Reactive Ion Etching) to form the gate electrode 5 covered with the silicon nitride film 14 and the silicon oxide film 5 ″ (FIG. 4).
(C)). Next, a silicon oxide film 15 'is deposited on the main surface of the semiconductor substrate 1 on which the gate electrode 5 is formed by CVD or the like (FIG. 5A). Next, the silicon oxide film 1
5 'is etched by an anisotropic etching method such as RIE to form a gate sidewall insulating film 15 on the gate electrode 5 (FIG. 5B). Next, with the gate sidewall insulating film 15 formed, an n-type impurity is implanted and diffused into the main surface of the semiconductor substrate 1 to form the drain region 3. Since the gate electrode 5 is surrounded by the gate sidewall insulating film 15, a drain region having an offset corresponding to the thickness of the gate sidewall insulating film is formed (FIG. 5C). Thereafter, as shown in FIG. 1, a post-process electrode formation and the like are performed. First, the interlayer insulating film 12 is formed on the semiconductor substrate 1.
Is deposited to cover the drain region 3, the gate electrode 5, and the like. Next, a contact hole is formed in the interlayer insulating film 12. Then, an aluminum film is deposited on the interlayer insulating film 12, and is patterned to form a source electrode 6 and a drain electrode 7 on the interlayer insulating film 12, and connect the source electrode 6 and the contact region 2 'to the contact hole. The wiring 8 to be connected and the wiring 9 connecting the drain electrode 7 and the contact region 3 'are buried. Further, a post-process such as applying a protective insulating film to the surface of the semiconductor substrate 1 is performed to complete the semiconductor device. As described above, the notch shape is formed on the upper side of the gate electrode by the thermal oxidation treatment. Thus, a desired shape of the gate electrode such as a trapezoidal cross section is obtained. Further, in processing the gate electrode by thermal oxidation, it is possible to form a drain region having no overlap with the gate electrode by self-alignment using the gate side wall insulating film. If there is no overlap between the gate electrode and the drain region, an increase in ON resistance is caused. However, a slight shift (for example, about 0.1 μm) does not increase so much and leads to a reduction in gate-drain capacitance. Further, only the upper side of the gate electrode is processed, and the lower side in contact with the gate insulating film is not processed, so that the gate electrode can be processed with good dimensional controllability. Next, a second embodiment will be described with reference to FIGS. FIG. 6 is a cross-sectional view of the semiconductor device, and FIGS. 7 and 8 are cross-sectional views of the manufacturing process of the semiconductor device of FIG. The semiconductor substrate 21 is, for example, p-type silicon, and has an n-type source region 22 and an n-type drain region 23 exposed on the main surface.
have. A gate electrode 25 made of polysilicon or the like is formed between the source / drain regions 22 and 23 via a gate insulating film 24 such as a silicon oxide film. The main surface of the semiconductor substrate 21 and the gate electrode 25 are covered with an interlayer insulating film 32 such as a silicon oxide film, and aluminum (first Al) is formed on the interlayer insulating film 32.
Source electrode 26 and drain electrode 27 comprising
Is formed. Source electrode 26 and drain electrode 2
Reference numeral 7 is electrically connected to the n-type source region 22 and the n-type drain region 23 via wirings 28 and 29 embedded in contact holes formed in the interlayer insulating film 32. Wirings 28 and 29 are connected to n of source / drain regions 22 and 23
+ Contact regions 22 'and 23'. Further, although not shown, the source electrode 26 and the drain electrode 27 are covered with an interlayer insulating film such as a silicon oxide film. The gate electrode of this embodiment is different from the first embodiment in that the gate side wall insulating film is not formed.
A structure having a gate sidewall insulating film may be used. The gate electrode 25 is formed on the semiconductor substrate 21 between the source region 22 and the drain region 23 by a gate insulating film 24.
Are arranged through. Two opposite sides along the gate width direction above the gate electrode 25 are cut out by etching. As described above, the gate electrode 25 has a shape in which two opposing upper sides are cut out, so that the distance between the gate electrode 5 and the drain electrode 7 and the distance between the gate electrode 25 and the drain region 23-drain electrode 27, or the distance between the gate electrode 25 and the drain region 23 is larger than that of the conventional substantially rectangular parallelepiped gate electrode, so that the capacitance between them is small. Has become. Next, the manufacturing process of the semiconductor device shown in FIG. 6 will be described with reference to FIGS. First, the semiconductor substrate 2
1 is heat-treated to form a gate insulating film 24 made of a silicon oxide film on the main surface. A gate electrode material film 25 ′ made of a polysilicon film is formed on the gate insulating film 24 by CV.
D (FIG. 7A). Next, a photoresist 36 is applied on the film 25 'of the gate electrode material, and this is patterned into the shape of the gate electrode (FIG. 7).
(B)). This patterned photoresist 36
Is used as a mask, and the upper portion of the film 25 'of the gate electrode material is
Etching is performed by an isotropic etching method such as E or wet etching. This etching process removes the upper part of the film 25 ′ of the gate electrode material, but maintains the film thickness under the photoresist 36 without being etched. However, the masking action of the photoresist 36 is not sufficient,
The periphery is slightly etched. Therefore, the film 25 'of the gate electrode material is in contact with the central portion of the photoresist 36, but the etching proceeds toward the peripheral portion, and the thickness of the film 25' of the gate electrode material decreases (FIG. 7). (C)). Next, using the patterned photoresist 36 as a mask, the film 25 'of the gate electrode material is removed by RIE.
The gate electrode 25 is formed by patterning by anisotropic etching such as (FIG. 8A). Next, the photoresist 36 is removed from the semiconductor substrate 21 (FIG. 8).
(B)). Next, n-type impurities are implanted and diffused into the main surface of the semiconductor substrate 21 to form source / drain regions 22 and 23 (FIG. 6). Thereafter, as shown in FIG. 6, a subsequent step, such as electrode formation, is performed. First, a contact hole is formed in the interlayer insulating film 32. Then, an aluminum film is deposited on the interlayer insulating film 32, and is patterned to form a source electrode 26 and a drain electrode 27 on the interlayer insulating film 32. The source electrode 26 and the contact region 2 are formed in the contact holes.
The wiring 28 connecting the gate electrode 2 'and the wiring 29 connecting the drain electrode 27 and the contact region 23' are buried. Further, a post-process such as applying a protective insulating film to the surface of the semiconductor substrate 21 is performed to complete the semiconductor device. As described above, the notch shape is formed on the upper side of the gate electrode by the thermal oxidation treatment. in this way,
As the shape of the gate electrode, a desired shape such as a trapezoidal cross section can be obtained. Further, in this embodiment, since the gate electrode is processed by isotropic etching using CDE or the like, a desired shape can be easily obtained. Further, only the upper side of the gate electrode is processed, and the lower side in contact with the gate insulating film is not processed, so that the gate electrode can be processed with good dimensional control. According to the present invention, with the above structure, the capacitance between the gate electrode and the drain region, the capacitance between the gate electrode and the drain, the capacitance between the gate electrode and the drain electrode, etc. can be effectively reduced. Therefore, it is possible to cope with an increase in the speed of the semiconductor device and to make them closer to each other than in the related art.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a perspective view of a gate electrode used in the semiconductor device of FIG. 1; FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device of FIG. 1; FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device of FIG. 1; FIG. 5 is a sectional view of the semiconductor device in FIG. 1 during a manufacturing step; FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 7 is a sectional view of the semiconductor device in FIG. 6 during a manufacturing step; FIG. 8 is a sectional view of the semiconductor device in FIG. 6 during the manufacturing process; FIG. 9 is a schematic cross-sectional view schematically showing a gate electrode structure of a conventional semiconductor device. [Description of Signs] 1, 21, 101: semiconductor substrate, 2, 22, 102: source region, 2 ', 3', 22 ', 23' ... contact region, 3, 23, 103 ..Drain region, 4, 24, 104 ... gate insulating film, 5, 25, 105 ... gate electrode, 5 ', 25' ... film of gate electrode material (polysilicon film), 6, 26 , 106 ... source electrode, 7, 27, 107 ... drain electrode, 8, 9, 10, 28, 29 ... wiring, 12, 32 ... interlayer insulating film, 14 ... silicon nitride film , 15 ... gate sidewall insulating film, 15 '
・ Silicon oxide film, 15 ″... Thermal oxide film, 16,
36 ... Photoresist.

   ────────────────────────────────────────────────── ─── Continuation of front page    F term (reference) 4M104 AA01 BB01 BB02 CC05 DD02                       DD04 DD08 DD09 DD26 DD43                       DD64 DD65 DD66 DD78 DD86                       DD89 EE05 EE14 EE17 FF08                       GG09 GG10 GG14 HH14 HH18                 5F140 AA01 AA11 AA39 BA01 BE07                       BF01 BF04 BF42 BG08 BG12                       BG22 BG28 BG36 BG37 BG38                       BG52 BH17 BH18 BJ01 BJ05                       BK13 BK25 CC03

Claims (1)

  1. Claims: 1. A semiconductor substrate, a source / drain region formed on the semiconductor substrate, and a gate insulating film formed on the semiconductor substrate between the source / drain regions. A gate electrode, wherein the gate electrode is substantially a rectangular parallelepiped, and at least one pair of opposing sides of the rectangular parallelepiped is cut out. 2. The semiconductor device according to claim 1, wherein a cutout shape of said gate electrode is formed at least along a gate width direction. 3. The semiconductor device according to claim 1, wherein a side surface of the gate electrode is covered with a gate side wall insulating film. 4. A step of depositing a film of a gate electrode material over the entire main surface of the semiconductor substrate via a gate insulating film; and a step of arranging a mask patterned in a gate electrode shape on the film of the gate electrode material; The semiconductor substrate is heat-treated to oxidize the upper portion of the gate electrode material film, and the upper portion of the portion where the mask is disposed,
    Oxidizing a predetermined distance from a peripheral portion to a central portion of the mask; processing a film of the gate electrode material in accordance with the mask pattern to form a gate electrode; Implanting and diffusing to form a source region and a drain region; and forming a source electrode and a drain electrode connected to each of the source region and the drain region on the semiconductor substrate, wherein the gate electrode Is a rectangular parallelepiped, and in this rectangular parallelepiped, at least one pair of opposing sides of the upper portion is cut out by a step of oxidizing an upper portion of the film of the gate electrode material. 5. A step of depositing a film of a gate electrode material over the entire main surface of the semiconductor substrate via a gate insulating film; and a step of arranging a mask patterned in a gate electrode shape on the film of the gate electrode material; A region of the semiconductor substrate main surface other than where the mask is formed is etched by a chemical dry etching method or a wet etching method to remove an upper portion of the film of the gate electrode material, and an upper portion of a portion where the mask is disposed is Removing a predetermined distance from a peripheral portion to a central portion of the mask; processing a film of the gate electrode material in accordance with a pattern of the mask to form a gate electrode; removing the mask; Implanting and diffusing impurities into the semiconductor substrate to form a source region and a drain region; and Forming a source electrode and a drain electrode connected to each of the source region and the drain region, wherein the gate electrode is a rectangular parallelepiped, and the rectangular parallelepiped has at least one pair of upper portions opposed by the etching step. Characterized in that the sides of the semiconductor device have notched shapes. 6. The method according to claim 1, further comprising a step of forming a gate sidewall insulating film on a side surface of the gate electrode, wherein the step of forming the drain region is performed after the step of forming the gate sidewall insulating film. A method for manufacturing a semiconductor device according to claim 4.
JP2002053204A 2002-02-28 2002-02-28 Semiconductor device and its manufacturing method Pending JP2003258244A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123774B2 (en) 2013-01-23 2015-09-01 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
WO2017212873A1 (en) * 2016-06-10 2017-12-14 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
CN108172545A (en) * 2016-12-08 2018-06-15 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123774B2 (en) 2013-01-23 2015-09-01 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
WO2017212873A1 (en) * 2016-06-10 2017-12-14 三菱電機株式会社 Semiconductor device and method for manufacturing semiconductor device
CN108172545A (en) * 2016-12-08 2018-06-15 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof

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