JP2003258194A - Housing device for semiconductor circuit - Google Patents
Housing device for semiconductor circuitInfo
- Publication number
- JP2003258194A JP2003258194A JP2002050941A JP2002050941A JP2003258194A JP 2003258194 A JP2003258194 A JP 2003258194A JP 2002050941 A JP2002050941 A JP 2002050941A JP 2002050941 A JP2002050941 A JP 2002050941A JP 2003258194 A JP2003258194 A JP 2003258194A
- Authority
- JP
- Japan
- Prior art keywords
- pin terminal
- circuit
- sbd
- frame
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はパッケージに設けら
れられたピン端子を使用する回路によって、最適に配置
することができるようにした半導体回路収納装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit housing device which can be optimally arranged by a circuit using pin terminals provided in a package.
【０００２】[0002]
【従来の技術】パッケージに設けられたピン端子は金型
を共通にしコストを低下させる等の理由で内蔵される回
路に関係がなく配置が定められている。特に５ピン端子
タイプのパッケージに、ＭＯＳＦＥＴとＳＢＤ（ショッ
トキー バリア ダイオード）とを用いた複合回路を内
蔵する場合において、使用される回路に無関係にピン端
子の配置が同一であると、前記回路間の配線が複雑にな
る。2. Description of the Related Art The arrangement of pin terminals provided in a package is determined irrespective of a built-in circuit for reasons such as using a common mold to reduce the cost. In particular, when a 5-pin terminal type package incorporates a composite circuit using MOSFET and SBD (Schottky barrier diode), if the pin terminals are arranged the same regardless of the circuit used, Wiring becomes complicated.
【０００３】図５は従来の半導体回路収納装置に用いら
れパッケージの平面図である。パッケージ１にはアノー
ドピン端子Ａ、ソースピン端子Ｓ、ゲートピン端子Ｇ、
カソードピン端子Ｃ及びドレインピン端子Ｄが設けられ
ている。これらアノードピン端子Ａ、ソースピン端子
Ｓ、ゲートピン端子Ｇ、カソードピン端子Ｃ及びドレイ
ンピン端子Ｄの配置は固定されている。FIG. 5 is a plan view of a package used in a conventional semiconductor circuit housing device. The package 1 includes an anode pin terminal A, a source pin terminal S, a gate pin terminal G,
A cathode pin terminal C and a drain pin terminal D are provided. The arrangement of the anode pin terminal A, the source pin terminal S, the gate pin terminal G, the cathode pin terminal C, and the drain pin terminal D is fixed.
【０００４】また前記パッケージ１の内部にはＳＢＤを
使用したＳＢＤ回路２ａ（２ｂ）が設けられたＳＢＤフ
レ−ム３とＦＥＴを使用したＦＥＴ回路４ａ（４ｂ）が
設けられたＦＥＴフレーム５が取り付けられている。Inside the package 1, an SBD frame 3 having an SBD circuit 2a (2b) using an SBD and an FET frame 5 having an FET circuit 4a (4b) using an FET are mounted. Has been.
【０００５】図３はＦＥＴとＳＢＤを用いたダウンコン
バータ回路である。電池または商用電源を整流して得ら
れた直流電源７にはＰチャンネルのＭＯＳＦＥＴ８のソ
ース電極Ｓが接続される。前記ＭＯＳＦＥＴ８のドレイ
ン電極Ｄはインダクタンス１１を介してチューナー等の
負荷回路１２が接続されている。FIG. 3 shows a down converter circuit using an FET and an SBD. A source electrode S of a P-channel MOSFET 8 is connected to a DC power source 7 obtained by rectifying a battery or a commercial power source. The drain electrode D of the MOSFET 8 is connected to a load circuit 12 such as a tuner via an inductance 11.
【０００６】前記ＭＯＳＦＥＴ８のドレイン電極Ｄには
ＮチャンネルＭＯＳＦＥＴ９のドレイン電極Ｄが接続さ
れている。そして前記ＮチャンネルＭＯＳＦＥＴ９のド
レイン電極ＤにはＳＢＤ１０のカソード電極Ｃが接続さ
れている。The drain electrode D of the N-channel MOSFET 9 is connected to the drain electrode D of the MOSFET 8. The cathode electrode C of the SBD 10 is connected to the drain electrode D of the N-channel MOSFET 9.
【０００７】ダウンコーバータ回路は上述する構成をな
しており、前記ＭＯＳＦＥＴ８及びＭＯＳＦＥＴ９はゲ
ート電極Ｇに加わる制御信号に制御され、直流電源１の
電圧、例えば１０ＶはＳＢＤ１０、インダクタンス１１
及びコンデンサ１３の動作と相俟って５Ｖに低下されて
負荷回路１１に供給される。前記ＳＢＤ１０を含むＳＢ
Ｄ回路２ａはＳＢＤフレ−ム３に載せられ、ＭＯＳＦＥ
Ｔ８、９を含むＭＯＳＦＥＴ回路４ａはＦＥＴフレーム
５に載せられる。The down-converter circuit has the above-mentioned structure. The MOSFET 8 and the MOSFET 9 are controlled by the control signal applied to the gate electrode G, and the voltage of the DC power supply 1, for example, 10 V is SBD 10 and inductance 11.
In addition to the operation of the capacitor 13, the voltage is lowered to 5V and supplied to the load circuit 11. SB including the SBD 10
The D circuit 2a is mounted on the SBD frame 3 and
The MOSFET circuit 4a including T8 and 9 is mounted on the FET frame 5.
【０００８】図４はＦＥＴとＳＢＤを用いたアップコン
バータ回路である。前述と同様に電池または商用電源を
整流して得られた直流電源１４にはインダクタンス１５
の一端が接続されている。そして前記インダクタンス１
５の他端はＳＢＤ１６のアノード電極Ａに接続され、ま
たＳＢＤ１６のカソード電極は負荷回路１８に接続され
ている。アップコーバータ回路は上述する構成をなして
おり、ＭＯＳＦＥＴ１７はゲート電極Ｇに加わる制御信
号に制御され、直流電源１４の電圧、例えば５Ｖはイン
ダクタンス１５、ＳＢＤ１６及びコンデンサ１９の動作
の相俟って１０Ｖに昇圧されて負荷回路１８に供給され
る。前記ＳＢＤ１６を含むＳＢＤ回路２ｂはＳＢＤフレ
−ム３に載せられ、ＭＯＳＦＥＴ１４を含むＭＯＳＦＥ
Ｔ回路４ｂはＦＥＴフレーム５に載せられる。FIG. 4 shows an up converter circuit using an FET and an SBD. Similarly to the above, the DC power source 14 obtained by rectifying a battery or a commercial power source has an inductance 15
One end of is connected. And the inductance 1
The other end of 5 is connected to the anode electrode A of the SBD 16, and the cathode electrode of the SBD 16 is connected to the load circuit 18. The up-converter circuit has the above-described configuration, the MOSFET 17 is controlled by the control signal applied to the gate electrode G, and the voltage of the DC power source 14, for example, 5V, is 10V in combination with the operation of the inductance 15, the SBD 16, and the capacitor 19. Is boosted to and is supplied to the load circuit 18. The SBD circuit 2b including the SBD 16 is mounted on the SBD frame 3 and includes the MOSFET including the MOSFET 14.
The T circuit 4b is mounted on the FET frame 5.
【０００９】[0009]
【発明が解決しようとする課題】前述したように、パッ
ケージに設けられたピン端子は内蔵される半導体回路に
関係がなく固定されている。As described above, the pin terminals provided on the package are fixed regardless of the semiconductor circuit contained therein.
【００１０】図５に示すようなピン端子配置のパッケー
ジである場合、ダウンコンバータ回路のＳＢＤ回路２ａ
はＳＢＤフレ−ム３に載せられ、ＭＯＳＦＥＴ８、９を
含むＭＯＳＦＥＴ回路４ａはＦＥＴフレーム５に載せら
れる。そしてＳＢＤ１０のカソード端子Ｃはカソードピ
ン端子Ｃに接続され、またアノード端子Ａはアノードピ
ン端子Ａに接続される。同様にＭＯＳＦＥＴ８、９のド
レイン端子Ｄはドレインピン端子Ｄに接続され、そして
ＭＯＳＦＥＴ８、９のゲート電極Ｇはゲートピン端子Ｇ
に夫々接続される。さらに前記ＭＯＳＦＥＴ８、９のド
レイン電極とＳＢＤ１０のカソード電極は内部配線され
るが、前記カソードピン端子Ｃとドレインピン端子Ｄは
同じ側に近接して設けられているので、簡単に接続でき
る。In the case of the package having the pin terminal arrangement as shown in FIG. 5, the SBD circuit 2a of the down converter circuit.
Is mounted on the SBD frame 3, and the MOSFET circuit 4a including the MOSFETs 8 and 9 is mounted on the FET frame 5. The cathode terminal C of the SBD 10 is connected to the cathode pin terminal C, and the anode terminal A is connected to the anode pin terminal A. Similarly, the drain terminals D of the MOSFETs 8 and 9 are connected to the drain pin terminal D, and the gate electrode G of the MOSFETs 8 and 9 is the gate pin terminal G.
Respectively connected to. Further, the drain electrodes of the MOSFETs 8 and 9 and the cathode electrode of the SBD 10 are internally wired, but the cathode pin terminal C and the drain pin terminal D are provided close to each other on the same side, so that they can be easily connected.
【００１１】同様に、アップコンバータ回路のＳＢＤ回
路２ｂはＳＢＤフレ−ム３に載せられ、ＭＯＳＦＥＴ１
７を含むＭＯＳＦＥＴ回路４ｂはＦＥＴフレーム５に載
せられる。そしてＳＢＤ１６のカソード端子Ｃはカソー
ドピン端子Ｃに接続され、またアノード端子Ａはアノー
ドピン端子Ａに接続される。同様にＭＯＳＦＥＴ１７の
ドレイン端子Ｄはドレインピン端子Ｄに接続され、そし
てＭＯＳＦＥＴ１７のゲート電極Ｇはゲートピン端子Ｇ
に夫々接続される。さらに前記ＭＯＳＦＥＴ１７のドレ
イン電極とＳＢＤ１６のアノード電極は内部配線される
が、前記ドレインピン端子Ｄとアノードピン端子Ａは反
対側に設けられている。従って接続するリード線をフレ
ームの下側を通す等する必要があったので、配線が複雑
になった。Similarly, the SBD circuit 2b of the up-converter circuit is mounted on the SBD frame 3, and the MOSFET 1
The MOSFET circuit 4b including 7 is mounted on the FET frame 5. The cathode terminal C of the SBD 16 is connected to the cathode pin terminal C, and the anode terminal A is connected to the anode pin terminal A. Similarly, the drain terminal D of the MOSFET 17 is connected to the drain pin terminal D, and the gate electrode G of the MOSFET 17 is the gate pin terminal G.
Respectively connected to. Further, the drain electrode of the MOSFET 17 and the anode electrode of the SBD 16 are internally wired, but the drain pin terminal D and the anode pin terminal A are provided on opposite sides. Therefore, it is necessary to pass the connecting lead wire through the lower side of the frame, and the wiring becomes complicated.
【００１２】[0012]
【課題を解決するための手段】本発明は内蔵される回路
に応じてピン端子の配置を変更できるようにしたもの
で、パッケージ内に設けられ異なる回路が載置される２
以上のフレームと、前記パッケージに設けられた複数の
ピン端子とよりなり、前記フレームの向きあるいは配置
を変更することにより、前記ピン端子の配置をフレーム
に載置される回路が内部配線するのに好適になるように
変更できる半導体回路収納装置を提供する。According to the present invention, the arrangement of the pin terminals can be changed according to the built-in circuit, and different circuits are provided in the package.
The above-described frame and a plurality of pin terminals provided in the package are provided. By changing the orientation or the arrangement of the frame, the arrangement of the pin terminals can be internally wired by a circuit mounted on the frame. Provided is a semiconductor circuit housing device that can be changed to be suitable.
【００１３】又本発明は前記フレームがＳＢＤ回路を載
置するＳＢＤフレームと、ＭＯＳＦＥＴ回路を載置する
ＦＥＴフレームとであり、前記ピン端子がアノードピン
端子Ａ、カソードピン端子Ｃ、ソースピン端子Ｓ、ゲー
トピン端子Ｇ及びドレインピン端子Ｄとであり、前記Ｆ
ＥＴフレーム又はＳＢＤフレームに夫々載置されるＳＢ
Ｄ回路及びＦＥＴ回路に応じて、これらＳＢＤフレーム
又はＦＥＴフレームの向き又は配置を変更し、前記アノ
ードピン端子Ａ、カソードピン端子Ｃ、ソースピン端子
Ｓ、ゲートピン端子Ｇ及びドレインピン端子Ｄの配置を
前記ＳＢＤ回路とＦＥＴ回路とを内部配線するに好適に
変更する半導体回路収納装置を提供する。In the present invention, the frame is an SBD frame on which an SBD circuit is mounted and an FET frame on which a MOSFET circuit is mounted, and the pin terminals are an anode pin terminal A, a cathode pin terminal C and a source pin terminal S. , A gate pin terminal G and a drain pin terminal D, and said F
SB mounted on ET frame or SBD frame, respectively
Depending on the D circuit and the FET circuit, the orientation or arrangement of these SBD frame or FET frame is changed to arrange the anode pin terminal A, the cathode pin terminal C, the source pin terminal S, the gate pin terminal G and the drain pin terminal D. Provided is a semiconductor circuit housing device that is suitably modified to internally wire the SBD circuit and the FET circuit.
【００１４】さらに本発明は前記ＳＢＤ回路及びＦＥＴ
回路はダウンコンバータ回路とアップコンバータ回路で
あり、ダウンコンバータ回路のとき、パッケージの一方
側に前記アノードピン端子Ａ、ソースピン端子Ｓ及びゲ
ートピン端子Ｇの順に配置し、反対側にカソードピン端
子Ｇ及びドレインピン端子Ｄを配置し、アップコンバー
タ回路のとき前記ＳＢＤフレームの向きを反転し、パッ
ケージの一方側に前記カソードピン端子Ｃ、ソースピン
端子Ｓ及びゲートピン端子Ｇの順に配置し、反対側にア
ノードピン端子Ａ及びドレインピン端子Ｄを配置した半
導体回路収納装置を提供する。Furthermore, the present invention provides the SBD circuit and FET
The circuits are a down converter circuit and an up converter circuit. In the case of the down converter circuit, the anode pin terminal A, the source pin terminal S and the gate pin terminal G are arranged in this order on one side of the package and the cathode pin terminal G and the other on the opposite side. The drain pin terminal D is arranged, the direction of the SBD frame is reversed in the up-converter circuit, the cathode pin terminal C, the source pin terminal S and the gate pin terminal G are arranged in this order on one side of the package, and the anode is arranged on the opposite side. A semiconductor circuit housing device in which a pin terminal A and a drain pin terminal D are arranged is provided.
【００１５】[0015]
【発明の実施の形態】本発明の半導体回路収納装置を図
１から図４に従って説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor circuit housing device of the present invention will be described with reference to FIGS.
【００１６】図１は本発明の半導体回路収納装置の平面
図で、パッケージ２０にはＳＢＤフレーム２１及びＦＥ
Ｔフレーム２２が取り付けられている。前記ＳＢＤフレ
ーム２１にはダウンコンバータ回路のＳＢＤ回路２ａが
載置され、ＦＥＴフレーム２２にはＦＥＴ回路４ａが載
置される。FIG. 1 is a plan view of a semiconductor circuit housing device according to the present invention, in which a package 20 has an SBD frame 21 and an FE.
A T frame 22 is attached. An SBD circuit 2a of a down converter circuit is mounted on the SBD frame 21, and an FET circuit 4a is mounted on the FET frame 22.
【００１７】前記パッケージ１の一方側にはアノードピ
ン端子Ａ、ソースピン端子Ｓ及びゲートピン端子Ｇの順
に配置されている。又前記パッケージ１の他側にはカソ
ードピン端子Ｃ及びドレインピン端子Ｄが配置されてい
る。An anode pin terminal A, a source pin terminal S and a gate pin terminal G are arranged in this order on one side of the package 1. A cathode pin terminal C and a drain pin terminal D are arranged on the other side of the package 1.
【００１８】図３は前述したダウンコンバータ回路であ
る。電池または商用電源を整流して得られた直流電源７
にはＰチャンネルのＭＯＳＦＥＴ８のソース電極Ｓが接
続される。前記ＭＯＳＦＥＴ８のドレイン電極Ｄはイン
ダクタンス１１を介してチューナー等の負荷回路１２が
接続されている。FIG. 3 shows the down converter circuit described above. DC power source 7 obtained by rectifying a battery or commercial power source
Is connected to the source electrode S of the P-channel MOSFET 8. The drain electrode D of the MOSFET 8 is connected to a load circuit 12 such as a tuner via an inductance 11.
【００１９】前記ＭＯＳＦＥＴ８のドレイン電極Ｄには
ＮチャンネルＭＯＳＦＥＴ９のドレイン電極Ｄが接続さ
れている。そして前記ＮチャンネルＭＯＳＦＥＴ９のド
レイン電極ＤにはＳＢＤ１０のカソード電極Ｃが接続さ
れている。The drain electrode D of the N-channel MOSFET 9 is connected to the drain electrode D of the MOSFET 8. The cathode electrode C of the SBD 10 is connected to the drain electrode D of the N-channel MOSFET 9.
【００２０】前記ＳＢＤ回路２ａはＳＢＤフレ−ム３に
載せられ、ＭＯＳＦＥＴ回路はＦＥＴフレーム５に載せ
られる。そして前記ＳＢＤ回路２ａのカソード端子Ｃは
カソードピン端子Ｃに接続され、またアノード端子Ａは
アノードピン端子Ａに接続される。同様にＭＯＳＦＥＴ
８、９のドレイン端子Ｄはドレインピン端子Ｄに接続さ
れ、そしてＭＯＳＦＥＴ８、９のゲート電極Ｇはゲート
ピン端子Ｇに夫々接続される。さらに前記ＭＯＳＦＥＴ
８、９のドレイン電極とＳＢＤ１０のカソード電極は内
部配線されるが、前記カソードピン端子Ｃとドレインピ
ン端子Ｄは同じ側に近接して設けられているので、簡単
に接続できる。The SBD circuit 2a is mounted on the SBD frame 3, and the MOSFET circuit is mounted on the FET frame 5. The cathode terminal C of the SBD circuit 2a is connected to the cathode pin terminal C, and the anode terminal A is connected to the anode pin terminal A. Similarly MOSFET
The drain terminals D of 8 and 9 are connected to the drain pin terminal D, and the gate electrodes G of the MOSFETs 8 and 9 are connected to the gate pin terminal G, respectively. Furthermore, the MOSFET
The drain electrodes 8 and 9 and the cathode electrode of the SBD 10 are internally wired, but since the cathode pin terminal C and the drain pin terminal D are provided close to each other on the same side, they can be easily connected.
【００２１】前記ＭＯＳＦＥＴ８及びＭＯＳＦＥＴ９は
ゲート電極Ｇに加わる制御信号に制御され、直流電源１
の電圧、例えば１０ＶはＳＢＤ１０、インダクタンス１
１及びコンデンサ１３の動作と相俟って５Ｖの低下され
て負荷回路１１に供給される。The MOSFET 8 and MOSFET 9 are controlled by the control signal applied to the gate electrode G, and the DC power supply 1
Voltage of, for example, 10V is SBD10, inductance 1
Together with the operation of 1 and the capacitor 13, the voltage is reduced to 5V and supplied to the load circuit 11.
【００２２】図２は本発明の半導体回路収納装置の他の
使用例を示めす平面図で、パッケージ２０にはＳＢＤフ
レーム２３及びＦＥＴフレーム２４が取り付けられてい
る。前記ＳＢＤフレーム２３にはアップコンバータ回路
のＳＢＤ回路２ｂが載置され、ＦＥＴフレーム２４には
ＦＥＴ回路４ｂが載置される。FIG. 2 is a plan view showing another example of use of the semiconductor circuit housing device of the present invention. An SBD frame 23 and an FET frame 24 are attached to the package 20. The SBD circuit 2b of the up-converter circuit is mounted on the SBD frame 23, and the FET circuit 4b is mounted on the FET frame 24.
【００２３】前記パッケージ２０にはＳＢＤフレーム２
３をＳＢＤフレーム２１とは逆向きにし、一方の側にカ
ノードピン端子Ｃ、ソースピン端子Ｓ及びゲートピン端
子Ｇの順に配置されている。又前記パッケージ２０の他
側にはアノードピン端子Ｃ及びドレインピン端子Ｄが配
置されている。The package 20 includes an SBD frame 2
3 is oriented in the opposite direction to the SBD frame 21, and the node pin terminal C, the source pin terminal S, and the gate pin terminal G are arranged in this order on one side. An anode pin terminal C and a drain pin terminal D are arranged on the other side of the package 20.
【００２４】図４は前記アップコンバータ回路で、電池
または商用電源を整流して得られた直流電源１４にはイ
ンダクタンス１５の一端が接続されている。そして前記
インダクタンス１５の他端はＳＢＤ１６のアノード電極
Ａに接続され、またＳＢＤ１６のカソード電極は負荷回
路１８に接続されている。前記ＳＢＤ１６を含むＳＢＤ
回路２はＳＢＤフレ−ム３に載せられ、ＭＯＳＦＥＴ１
４を含むＭＯＳＦＥＴ回路４はＦＥＴフレーム５に載置
される。FIG. 4 shows the up-converter circuit in which one end of an inductance 15 is connected to a DC power supply 14 obtained by rectifying a battery or a commercial power supply. The other end of the inductance 15 is connected to the anode electrode A of the SBD 16, and the cathode electrode of the SBD 16 is connected to the load circuit 18. SBD including the SBD 16
The circuit 2 is mounted on the SBD frame 3 and the MOSFET 1
The MOSFET circuit 4 including 4 is mounted on the FET frame 5.
【００２５】アップコンバータ回路のＳＢＤ回路２ｂは
ＳＢＤフレ−ム３に載置され、ＭＯＳＦＥＴ１７を含む
ＭＯＳＦＥＴ回路４ｂはＦＥＴフレーム５に載置され
る。そしてＳＢＤ１６のカソード端子Ｃはカソードピン
端子Ｃに接続され、またアノード端子Ａはアノードピン
端子Ａに接続される。同様にＭＯＳＦＥＴ１７のドレイ
ン端子Ｄはドレインピン端子Ｄに接続され、そしてＭＯ
ＳＦＥＴ１７のゲート電極Ｇはゲートピン端子Ｇに夫々
接続される。さらに前記ＭＯＳＦＥＴ１７のドレイン電
極とＳＢＤ１６のアノード電極は内部配線されるが、前
記ドレインピン端子Ｄとアノードピン端子Ａは同じ側に
設けられている。従って前述と同様にアノード電極とド
レイン電極とを簡単に接続できる。The SBD circuit 2b of the up-converter circuit is mounted on the SBD frame 3, and the MOSFET circuit 4b including the MOSFET 17 is mounted on the FET frame 5. The cathode terminal C of the SBD 16 is connected to the cathode pin terminal C, and the anode terminal A is connected to the anode pin terminal A. Similarly, the drain terminal D of MOSFET 17 is connected to the drain pin terminal D, and MO
The gate electrode G of the SFET 17 is connected to the gate pin terminal G, respectively. Further, the drain electrode of the MOSFET 17 and the anode electrode of the SBD 16 are internally wired, but the drain pin terminal D and the anode pin terminal A are provided on the same side. Therefore, similarly to the above, the anode electrode and the drain electrode can be easily connected.
【００２６】アップコーバータ回路は上述する構成をな
しており、ＭＯＳＦＥＴ１７はゲート電極Ｇに加わる制
御信号に制御され、直流電源１４の電圧、例えば５Ｖは
インダクタンス１５、ＳＢＤ１６及びコンデンサ１９の
動作の相俟って１０Ｖに昇圧されて負荷回路１８に供給
される。The up-converter circuit has the above-mentioned structure, the MOSFET 17 is controlled by the control signal applied to the gate electrode G, and the voltage of the DC power supply 14, for example, 5 V, is a function of the operation of the inductance 15, the SBD 16 and the capacitor 19. Therefore, the voltage is boosted to 10 V and supplied to the load circuit 18.
【００２７】[0027]
【発明の効果】本発明の半導体回路収納装置は内蔵され
る回路に応じてピン端子の配置を変更できるようにした
もので、フレームに載置される如何なる回路でも部品端
子間を容易に内部配線にできる。また前記内部配線する
端子間の距離が短くできるため、配線抵抗も低減でき
る。According to the semiconductor circuit housing device of the present invention, the arrangement of the pin terminals can be changed according to the built-in circuit, and internal wiring between the component terminals can be easily carried out in any circuit mounted on the frame. You can Further, since the distance between the terminals for the internal wiring can be shortened, the wiring resistance can be reduced.
【図１】本発明の半導体回路収納装置の平面図である。FIG. 1 is a plan view of a semiconductor circuit housing device of the present invention.
【図２】本発明の半導体回路収納装置の他の使用例を示
めす平面図である。FIG. 2 is a plan view showing another example of use of the semiconductor circuit housing device of the present invention.
【図３】本発明及び従来の半導体回路収納装置に用いら
れたダウンコンバータ回路の回路図である。FIG. 3 is a circuit diagram of a down converter circuit used in the present invention and the conventional semiconductor circuit housing device.
【図４】本発明及び従来の半導体回路収納装置に用いら
れたアップコンバータ回路の回路図である。FIG. 4 is a circuit diagram of an up-converter circuit used in the present invention and the conventional semiconductor circuit housing device.
【図５】従来の半導体回路収納装置の平面図である。FIG. 5 is a plan view of a conventional semiconductor circuit housing device.
２ａ ＳＢＤ回路 ２ｂ ＳＢＤ回路 ４ａ ＦＥＴ回路 ４ｂ ＦＥＴ回路 ２０ パッケージ ２１ ＳＢＤフレーム ２２ ＦＥＴフレーム ２３ ＳＢＤフレーム ２４ ＦＥＴフレーム 2a SBD circuit 2b SBD circuit 4a FET circuit 4b FET circuit 20 packages 21 SBD frame 22 FET frame 23 SBD frame 24 FET frame
───────────────────────────────────────────────────── フロントページの続き (72)発明者 秋庭 隆史 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 及川 慎 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 保坂 健一 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 (72)発明者 齋藤 雅也 大阪府守口市京阪本通２丁目５番５号 三 洋電機株式会社内 Ｆターム(参考） 5F067 AA00 AB02 CD01 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Takashi Akiba 2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture Within Yo Denki Co., Ltd. (72) Inventor Shin Oikawa 2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture Within Yo Denki Co., Ltd. (72) Inventor Kenichi Hosaka 2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture Within Yo Denki Co., Ltd. (72) Inventor Masaya Saito 2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture Within Yo Denki Co., Ltd. F term (reference) 5F067 AA00 AB02 CD01
Claims (3)
が載置される２以上のフレームと、前記パッケージに設
けられた複数のピン端子とよりなり、前記フレームの向
きあるいは配置を変更することにより、前記ピン端子の
配置をフレームに載置される回路が内部配線するのに好
適に変更したことを特徴とする半導体回路収納装置。1. A package comprising two or more frames mounted in a package on which different circuits are mounted, and a plurality of pin terminals provided on the package. By changing the orientation or the layout of the frame, A semiconductor circuit housing device, in which the arrangement of pin terminals is suitably changed for internal wiring of a circuit mounted on a frame.
載置するＳＢＤフレームと、ＭＯＳＦＥＴ回路を載置す
るＦＥＴフレームとであり、前記ピン端子はアノードピ
ン端子Ａ、カソードピン端子Ｃ、ソースピン端子Ｓ、ゲ
ートピン端子Ｇ及びドレインピン端子Ｄとであり、前記
ＳＢＤフレーム及びＦＥＴフレームに夫々載置されるＳ
ＢＤ回路及びＦＥＴ回路に応じてこれらＳＢＤフレーム
又はＦＥＴフレームの向きを変更し、前記アノードピン
端子Ａ、カソードピン端子Ｃ、ソースピン端子Ｓ、ゲー
トピン端子Ｇ及びドレインピン端子Ｄの回路配置を変更
することを特徴とする請求項１記載の半導体回路収納装
置。2. The frame is at least an SBD frame on which an SBD circuit is mounted and an FET frame on which a MOSFET circuit is mounted, and the pin terminals are an anode pin terminal A, a cathode pin terminal C, a source pin terminal S, A gate pin terminal G and a drain pin terminal D, which are mounted on the SBD frame and the FET frame, respectively.
The orientation of the SBD frame or FET frame is changed according to the BD circuit and the FET circuit, and the circuit arrangement of the anode pin terminal A, the cathode pin terminal C, the source pin terminal S, the gate pin terminal G and the drain pin terminal D is changed. The semiconductor circuit housing device according to claim 1, wherein:
コンバータ回路とアップコンバータ回路であり、ダウン
コンバータ回路のとき、パッケージの一方側に前記アノ
ードピン端子Ａ、ソースピン端子Ｓ及びゲートピン端子
Ｇの順に配置し、反対側にカソードピン端子Ｃ及びドレ
インピン端子Ｄを配置し、アップコンバータ回路のとき
前記ＳＢＤフレームの向きを反転し、パッケージの一方
側に前記カソードピン端子Ｃ、ソースピン端子Ｓ及びゲ
ートピン端子Ｇの順に配置し、反対側にアノードピン端
子Ａ及びドレインピン端子Ｄを配置したことを特徴とす
る請求項２記載の半導体回路収納装置。3. The SBD circuit and the FET circuit are a down converter circuit and an up converter circuit, and in the case of the down converter circuit, the anode pin terminal A, the source pin terminal S, and the gate pin terminal G are arranged in this order on one side of the package. Then, the cathode pin terminal C and the drain pin terminal D are arranged on the opposite side, the direction of the SBD frame is reversed in the up-converter circuit, and the cathode pin terminal C, the source pin terminal S and the gate pin terminal are provided on one side of the package. 3. The semiconductor circuit housing device according to claim 2, wherein the anode pin terminal A and the drain pin terminal D are disposed on the opposite side in the order of G.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002050941A JP4646480B2 (en) | 2002-02-27 | 2002-02-27 | Semiconductor circuit storage device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002050941A JP4646480B2 (en) | 2002-02-27 | 2002-02-27 | Semiconductor circuit storage device |
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| Publication Number | Publication Date |
|---|---|
| JP2003258194A true JP2003258194A (en) | 2003-09-12 |
| JP4646480B2 JP4646480B2 (en) | 2011-03-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002050941A Expired - Fee Related JP4646480B2 (en) | 2002-02-27 | 2002-02-27 | Semiconductor circuit storage device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006058477A1 (en) * | 2004-11-30 | 2006-06-08 | Alpha & Omega Semiconductor (Shanghai), Ltd. | Thin small outline package in which mosfet and schottky diode being co-packaged |
| JP2007294669A (en) * | 2006-04-25 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2009110981A (en) * | 2007-10-26 | 2009-05-21 | Mitsubishi Electric Corp | Semiconductor module |
| JP2012064739A (en) * | 2010-09-16 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304190A (en) * | 1992-04-28 | 1993-11-16 | Rohm Co Ltd | Semiconductor device |
| JPH08205528A (en) * | 1995-01-26 | 1996-08-09 | Nec Kansai Ltd | Step-up/step-down switching power supply |
| JPH1023749A (en) * | 1996-07-03 | 1998-01-23 | Fuji Electric Co Ltd | Switching power unit |
| JP2000235997A (en) * | 1999-02-15 | 2000-08-29 | Matsushita Electronics Industry Corp | Semiconductor device |
| WO2001003184A1 (en) * | 1999-07-02 | 2001-01-11 | Rohm Co., Ltd. | Electronic part |
| JP2001127100A (en) * | 1999-10-26 | 2001-05-11 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2001196518A (en) * | 1999-10-28 | 2001-07-19 | Rohm Co Ltd | Semiconductor device |
-
2002
- 2002-02-27 JP JP2002050941A patent/JP4646480B2/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304190A (en) * | 1992-04-28 | 1993-11-16 | Rohm Co Ltd | Semiconductor device |
| JPH08205528A (en) * | 1995-01-26 | 1996-08-09 | Nec Kansai Ltd | Step-up/step-down switching power supply |
| JPH1023749A (en) * | 1996-07-03 | 1998-01-23 | Fuji Electric Co Ltd | Switching power unit |
| JP2000235997A (en) * | 1999-02-15 | 2000-08-29 | Matsushita Electronics Industry Corp | Semiconductor device |
| WO2001003184A1 (en) * | 1999-07-02 | 2001-01-11 | Rohm Co., Ltd. | Electronic part |
| JP2001127100A (en) * | 1999-10-26 | 2001-05-11 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2001196518A (en) * | 1999-10-28 | 2001-07-19 | Rohm Co Ltd | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006058477A1 (en) * | 2004-11-30 | 2006-06-08 | Alpha & Omega Semiconductor (Shanghai), Ltd. | Thin small outline package in which mosfet and schottky diode being co-packaged |
| US8089139B2 (en) | 2004-11-30 | 2012-01-03 | Alpha & Omega Semiconductor, Ltd. | Small outline package in which MOSFET and Schottky diode being co-packaged |
| JP2007294669A (en) * | 2006-04-25 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JP2009110981A (en) * | 2007-10-26 | 2009-05-21 | Mitsubishi Electric Corp | Semiconductor module |
| JP2012064739A (en) * | 2010-09-16 | 2012-03-29 | Mitsubishi Electric Corp | Semiconductor device |
| US9087712B2 (en) | 2010-09-16 | 2015-07-21 | Mitsubishi Electric Corporation | Semiconductor device |
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|---|---|
| JP4646480B2 (en) | 2011-03-09 |
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| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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| LAPS | Cancellation because of no payment of annual fees |