JP2003233635A - Logic model creation method and apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logic model creation method capable of performing logic simulation at the function level of the whole circuit including the standby state and operative state of a CMOS circuit for making MTCMOS or at the gate level without correcting the description of the CMOS circuit describing the function level specifications or gate level specifications during normal operation. <P>SOLUTION: The MTCMOS circuit is grasped as a host hierarchical block of the CMOS circuit in the MTCMOS circuit, a digital circuit for performing logic verification is hierarchically divided into blocks and described, and in the specification description of the CMOS circuit in the MTCMOS circuit, the logic operation when a power supply interrupt transistor is in the on-state is described, and in the specification description of the MTCMOS circuit, included is the description to the effect that during the operation, a signal value of a signal line connected to an input pin is applied to the input pin, and during the standby operation, an undefined value is applied to the input pin. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to MTCMOS (Mu
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic model creating method and apparatus suitable for use when performing a logic simulation at a functional level or a gate level of a digital circuit including an ltithreshold-Voltage CMOS) circuit.

[0002]

2. Description of the Related Art In recent years, as the integration and performance of LSIs have increased, how to reduce the power consumption has become an important issue. MTCMOS technology is being adopted as a method for reducing the leakage current during standby while suppressing a decrease in the operating speed of the transistor during circuit operation. Regarding MTCMOS technology, for example, the paper “1-
VPower Suply High-Speed Digital Circuit Technology
with Multithreshold-Voltage CMOS (IEEE JOURNAL OF
SOLID-STATE CIRCUIT.VOL.30.NO.8, AUGUST 199
5) ”etc.

FIG. 15 is a circuit diagram showing an example of an MTCMOS circuit. In FIG. 15, 1 is an MO having a relatively low threshold voltage.
A CMOS circuit composed of S-transistors, 2 has a relatively high threshold voltage (leakage current when turned off) is a power cutoff transistor, 3 is an actual power line, 4 is a virtual power line, and 5 is an actual ground. The power cutoff transistor 2 is turned on by a signal for controlling standby / operation.
N and OFF are controlled, and are OFF during standby and ON during operation.

That is, this MTCMOS circuit is a power supply terminal 1A of a CMOS circuit 1 which is composed of MOS transistors having a relatively low threshold voltage in order to ensure high-speed operation.
Is connected to the virtual power supply line 4, and a power supply cutoff transistor 2 having a relatively high threshold voltage is provided between the virtual power supply line 4 and the actual power supply line 3 and the power supply cutoff transistor 2 is connected during standby. By turning it off, the leakage current of the CMOS circuit 1 during standby is suppressed.

Further, the power supply terminal 1A of the CMOS circuit 1 is connected to the virtual power supply line 4 and turned on / off by a signal for controlling standby / operation between the virtual power supply line 4 and the actual power supply line 3.
Instead of providing the power-supply cutoff transistor 2 having a relatively high threshold voltage, the ground terminal 1B of the CMOS circuit 1 is connected to a virtual ground line, and control is performed between the virtual ground line and the actual ground line 5. There may be a configuration in which a power cutoff transistor having a relatively high threshold voltage whose ON / OFF is controlled by a signal is provided.

Further, the power supply terminal 1A of the CMOS circuit 1 is connected to the virtual power supply line 4 and turned on / off by a signal for controlling standby / operation between the virtual power supply line 4 and the actual power supply line 3.
Is provided with a power supply cutoff transistor 2 having a relatively high threshold voltage, the ground terminal 1B of the CMOS circuit 1 is connected to a virtual ground line, and a standby / standby is provided between the virtual ground line and the actual ground line 5. In some cases, a power cutoff transistor having a relatively high threshold voltage, which is turned on and off by a signal for controlling the operation, may be provided.

[0007]

Here, for example, as shown in FIG. 16A, each of the functional blocks 6-1 has a plurality of functional blocks 6-1 to 6-N composed of a CMOS circuit.
16B, the large-scale integrated circuit having different standby conditions of 6 to 6-N uses the MTCMOS method as shown in FIG. 16B to reduce the power consumption of each of the functional blocks 6-1 to 6-N. Each functional block 6-
It is important to proceed with the design while verifying the logic with the logic simulator, including the simulation of the indefinite state at the time of standby / return of 1 to 6-N.

In FIG. 16, 7 is an actual power line, 8 is an actual ground line, 9-1, 9-2, 9-N are virtual power lines, 10-1, 10-2, 10-N. Is a power cutoff transistor having a relatively high threshold voltage, S1, S2 and SN are signals for controlling standby / operation of the functional blocks 6-1, 6-2 and 6-N, and 11 is output control signals S1 to SN It is a block that is always operated.

However, in hardware description languages such as VHDL and verilog-HDL which are widely used at present in the design of integrated circuits, for example, a function level description as shown in FIG. 17 and a gate level as shown in FIG. In the description, it is difficult to briefly describe the specification that turning off the power supply causes all signals of a specific functional block to be in an undefined state.

For example, turning on the power-off transistor
When a certain control signal S for controlling ON / OFF is "1",
When the operation according to the specifications shown in FIGS. 17 and 18 is performed and the control signal S is “0”, all internal states and output signals inside the block “sample” shown in FIGS. 17 and 18 are said to be indefinite. It is difficult to describe the specifications concisely.

Even if each behavioral description in a functional block is modified and such behavior is described, if such a special description is included in each logic description, a logic synthesis tool, etc. It becomes difficult to design with CAD software at the design stage like a normal logic circuit.

Here, when the specification description is made at the transistor level, the behavior when the power cutoff transistor is turned off can be simulated, but the amount of description is larger than that of the function level description or the gate level description. In addition, since it requires more time for simulation, it is not realistic to perform logic verification by transistor level specification description in a large scale integrated circuit.

Therefore, the MTCMOS has been conventionally used.
The operation verification of the entire circuit is performed by the description that does not include the power cutoff operation by the method, and the operation verification when the power supply of the functional block to be MTCMOS is cut off is performed by replacing the functional block with a black box. I've been told. However, in such a method, there is a problem that the verification in the case where the power supply of a plurality of functional blocks is shut off, the verification of the excessive operation at the time of shutting down / restoring, and the like are insufficient.

The present invention has been made in view of the above points.
Even if the hardware description language cannot express the phenomenon that the CMOS circuit to be converted into an indefinite state due to power-off, correction is added to the description of the CMOS circuit in which the functional level specifications and gate level specifications during normal operation are described. Without performing a logic simulation at a functional level or a gate level of the entire circuit including a standby state and an operating state of a CMOS circuit to be converted to MTCMOS, shortening the time required for logic verification of a digital circuit including an MTCMOS circuit and logic verification The first object is to provide a logical model creating method capable of improving the accuracy of
A second object of the present invention is to provide a logical model creation device capable of easily creating a logical model composed of a hardware description language compatible with MTCMOS operation from the logical specifications of a digital circuit including a CMOS circuit for MTCMOS conversion.
The purpose of.

[0015]

A logical model creating method of the present invention is a method for creating a logical model of a digital circuit including an MTCMOS circuit by a hardware description language, wherein the MTCMOS circuit is a CMO in the MTCMOS circuit.
It is assumed that the digital circuit is hierarchically divided into blocks and described as an upper hierarchical block of the S circuit, and the specification description of the CMOS circuit describes the logical operation when the power cutoff transistor is on. The specification description of the MTCMOS circuit includes a description that a signal value of a signal line connected to the input pin is applied to the input pin during operation and an undefined value is applied to the input pin during standby.

According to the logical model creating method of the present invention, M
Although the specification description of the CMOS circuit to be TCMOS-ized does not describe the operation at the time of standby, the specification description of the MTCMOS circuit includes the statement that an undefined value is applied to the input pin at the time of standby. It is equivalent to describing the behavior when it is blocked. Therefore, even in a hardware description language that cannot express a phenomenon in which a CMOS circuit that is made into an MTCMOS by powering off is indefinite, a CMOS that is made into an MTCMOS in which functional level specifications and gate level specifications during normal operation are described CMO that is implemented in MTCMOS without any modification to the circuit description
It is possible to perform a logic simulation at the functional level or the gate level of the entire circuit including the standby state and the operating state of the S circuit.

The logical model creating apparatus of the present invention is an MTCM.
A logical model creating device for creating a logical model of a digital circuit including a CMOS circuit to be converted into an OS in a hardware description language, wherein MTCMOS is not described in the hardware description language of MTCMOS operation of the digital circuit.
In order to be able to incorporate the description in the hardware description language of the MTCMOS operation unit of the CMOS circuit to be converted into MTCMOS into the upper layer portion of the CMOS circuit to be converted into MT
Upper layer description conversion means for converting the upper layer description of a CMOS circuit to be CMOSized, and MTCMO of a digital circuit
A description in a hardware description language in which S behavior is not described, and M
MTCMOS operation for automatically generating a description in the hardware description language of the MTCMOS operation unit of the CMOS circuit for MTCMOS based on the MTCMOS related information describing the correspondence relationship between the CMOS circuit for TCMOS conversion and the control signal name of the power-off transistor It has an automatic description generation means.

According to the logical model creating apparatus of the present invention, since the upper layer description converting means and the MTCMOS behavioral description automatic generating means are provided, it is possible to correspond to the MTCMOS behavior from the logical specifications of the digital circuit including the CMOS circuit to be MTCMOS. It is possible to easily create a logical model composed of the HDL description of the digital circuit.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart showing an embodiment of a logical model creating method of the present invention. In one embodiment of the logical model creating method of the present invention, first, an MTCM in which a standby condition is different, that is, a control signal for controlling ON / OFF of a power cutoff transistor is different.
Each OS circuit is grasped as an upper hierarchical block of a CMOS circuit inside the OS circuit, and a digital circuit for logical verification is hierarchically divided into blocks.

FIG. 2 is a block circuit diagram for specifically explaining block division of a digital circuit for performing logic verification. In FIG. 2, 12 is the entire circuit for performing logic verification, 13, 1
Reference numeral 4 denotes a partial circuit, and the partial circuit 13 is a partial circuit including MTCMOS circuits 15 and 16 having different control signals for controlling ON / OFF of the power cutoff transistor, and a CMOS circuit 17 not converted to MTCMOS. In addition, 18,
19 is a CMO in the MTCMOS circuits 15 and 16, respectively.
It is an S circuit. Further, the partial circuit 14 is an MTCMOS circuit, and 20 and 21 are for turning on / off the power cutoff transistor
It is a CMOS circuit in which the control signals for controlling OFF are the same.

For example, when the digital circuit shown in FIG. 2 is divided into blocks, the entire circuit 12 is the uppermost hierarchical block, the partial circuits 13 and 14 are lower hierarchical blocks of the entire circuit 12, the MTCMOS circuits 15 and 16 and the CMOS circuit. Reference numeral 17 denotes a lower hierarchical block of the partial circuit 13, CMOS circuit 18 denotes a lower hierarchical block of the MTCMOS circuit 15, CM
The OS circuit 19 is a lower hierarchical block of the MTCMOS circuit 16, the CMOS circuits 20 and 21 are lower hierarchical blocks of the partial circuit 14, and each of the blocks 12 to 21 is a unit of hardware description.

In one embodiment of the logical model creating method of the present invention, the entire circuit is divided into blocks, and then the hardware description of the MTCMOS circuit and the CMOS circuit is created.
Here, the logic specification of a CMOS circuit which is not converted to MTCMOS describes the logic operation at the function level or the gate level, and the logic specification of the CMOS circuit in the MTCMOS circuit is
The logic operation when the power cutoff transistor is turned on is described by the functional level or the gate level.

The specifications of the MTCMOS circuit are described so as to satisfy the following conditions A, B, and C. (A) A CMOS circuit included in the inside is provided as a lower hierarchical block, and the same input / output signal as the CMOS circuit included in the inside, a control signal for controlling ON / OFF of the power cutoff transistor, and a signal other than the control signal It is assumed that there are as many 2-to-1 selectors as there are input signals. (B) MTCMOS
The output signal of the circuit is assumed to be connected to the corresponding output signal of the output signals of the CMOS circuit in the MTCMOS circuit.

(C) In the 2-to-1 selector, one of the selected input terminals receives a corresponding input signal among the input signals other than the control signal, and the other selected input terminal is set to an undefined value. The output terminal is connected to the corresponding input terminal of the CMOS circuit, and when the control signal turns on the power cutoff transistor, the signal value of the input signal input to one of the selected input terminals is output, and the control signal is the power supply. When the cutoff transistor is turned off, an undefined value set in the other selected input terminal is output.

3 to 5 are views for specifically explaining one embodiment of the logical model creating method of the present invention.
5 is a circuit diagram showing a digital circuit for performing logic verification, FIG. 4 is a diagram showing a main part of a logic model of the digital circuit shown in FIG. 3, which is created by applying an embodiment of a logic model creating method of the present invention, FIG. FIG. 5 is a block circuit diagram showing the contents of the logical model shown in FIG.

In FIG. 3, reference numeral 22 is an actual VDD power supply line, and 23.
Is an actual GND (ground) line, 24-1 is a control signal
MTCMOS whose standby / operation is controlled by signal_1
Circuit, 25-1 is ON / OF by control signal signal_1
Power supply cut-off transistor (P channel M
OS transistor), 26-1 is a virtual VDD power supply line, 2
7-1 is a CMOS circuit in MTCMOS, in1,
..., inN is an input signal, out1, ..., outM is an output signal.

Numeral 24-2 is an MTCMOS circuit whose standby / operation is controlled by a control signal signal_2, 25-2 is a power cut-off transistor (P-channel MOS transistor) whose ON / OFF is controlled by a control signal signal_2,
26-2 is a virtual VDD power supply line, 27-2 is MTCMOS
, InN are input signals, out
1, ..., outM are output signals. 27-3 is a control signal generation circuit that generates control signals signal_1 and signal_2, and is a circuit that is always in an operating state.

In the case of the digital circuit shown in FIG. 3, the entire circuit is the top hierarchical block, the MTCMOS circuits 24-1 and 2-2.
4-2 and the control signal generation circuit 27-3 are lower hierarchical blocks of the uppermost hierarchical block, and the CMOS circuit 27-1 is M
Lower layer block of TCMOS circuit 24-1, CMOS
The circuit 27-2 is a lower hierarchical block of the MTCMOS circuit 24-2.

Here, for example, the entire digital circuit shown in FIG. 3 is TOP, the MTCMOS circuits 24-1 and 24-2 are block1_MT, block2_MT, and CMOS circuit 27-, respectively.
1 and 27-2 are described as block1 and block2 respectively, and the control signal generation circuit 27-3 is described as block3, TOP and b
By describing the specifications of lock1_MT, block2_MT, block1, block2, and block3 as shown in FIG. 4, it is possible to create a logic model for functional level or gate level logic simulation of the digital circuit shown in FIG.

Regarding the digital circuit shown in FIG.
5 is a block diagram of the logical model shown in FIG. 4 created according to the embodiment of the logical model creating method of the present invention.
As shown in. In FIG. 5, 28-1, ..., 28-N,
29-1, ..., 29-N are 2-to-1 selectors.

As described above, according to the embodiment of the logical model creating method of the present invention, the CMO is formed into MTCMOS.
Although the standby operation is not described in the specification description of the S circuit,
Since the MTCMOS circuit specification description includes the description that an undefined value is applied to the input pin in the standby state and the operation description equivalent to that when the power is cut off, MTCMO
Even in a hardware description language that cannot express the phenomenon that a CMOS circuit to be converted into an indefinite state due to power-off, please correct the description of the CMOS circuit in which the functional level specifications and gate level specifications during normal operation are described. Without adding, a logic simulation is performed at the functional level or the gate level of the entire circuit including the standby state and the operating state of the CMOS circuit to be MTCMOS-ized, thereby shortening the time required for logic verification of the digital circuit including the MTCMOS circuit and reducing the logic. The accuracy of verification can be improved.

FIG. 6 is a flow chart showing a verification CAD flow of a digital circuit using an embodiment of the logical model creating method of the present invention. On the other hand, in this logic verification CAD flow, based on the logic specifications of the entire digital circuit, one embodiment of the logic model creating method of the present invention is applied to describe the specifications of the whole digital circuit in a hardware description language (step S1), on the other hand, the verification sequence is described in the hardware description language based on the verification specifications of the digital circuit including the signal application timing, the input vector, the expected output value, etc. (step S2), and the hardware description language The entire verification model described in
It is applied to the L simulator to perform logic verification.

Here, step S1 of FIG. 6 (a step of applying the embodiment of the logical model creating method of the present invention to describe the entire digital circuit in HDL) may be performed as shown in FIG. 7, for example. it can. First, the entire digital circuit is hierarchically divided into blocks based on the logical specifications of the digital circuit including the block (CMOS circuit) to be converted into MTCMOS, and the HDL description of the entire digital circuit during normal operation (when the power cutoff transistor is turned on), That is, the HDL description F1 of the entire digital circuit in which the MTCMOS operation is not described is created (step P1).

Next, the MTCMO created in step P1
HDL description F1 of the entire digital circuit in which S operation is not described, and MTCMOS related information (information on the correspondence relationship between the block name of the block to be MTCMOS-ized and the control signal name of the power-off transistor) included in the logic specifications of the digital circuit F2
MTCMOS logic is automatically inserted based on
HDL description F3 of the entire digital circuit compatible with CMOS operation
Is created (step P2). This HDL description F3 of the entire digital circuit compatible with MTCMOS operation and H of the verification specification
With the DL description, a simulation corresponding to the MTCMOS operation of a digital circuit can be performed.

FIG. 8 is a block diagram of an embodiment of the logical model creating apparatus according to the present invention. Step P2 (MT) shown in FIG.
It realizes an automatic insertion process of CMOS logic).
An embodiment of the logical model creation device of the present invention has a higher layer description conversion means 31 and an MTCMOS behavioral description automatic generation means 32.

The upper layer description conversion means 31 is an MTCMO.
HDL description F1 of the entire digital circuit in which S behavior is not described,
MTCM in the HDL description of the entire digital circuit in which the MTCMOS operation is not described, based on the MTCMOS related information F2
A description of the upper layer of the block to be converted to MTCMOS in the HDL description of the entire digital circuit in which MTCMOS operation has not been described so that the HDL description of the MTCMOS operation unit of the block to be converted to MTCMOS can be incorporated in the upper layer portion of the block to be OS. Is to convert.

Specifically, the upper hierarchy description conversion means 31
Is the HD of the entire digital circuit without MTCMOS operation
In the description part in which the block to be converted to MTCMOS included in the L description F1 is called by the upper hierarchical block, M
By replacing the block name to be converted to TCMOS with the block name of the block describing the MTCMOS operation (generated by the MTCMOS operation description generation means 32) and adding the control signal name of the power cutoff transistor to the input, the MTCMO.
S Adds M to the HDL description F1 of the entire digital circuit that has not been described.
HD of the MTCMOS operation unit of the block to be converted to TCMOS
The HDL description F4 of the entire digital circuit, which has been modified to incorporate the L description, is generated.

MTCMOS behavior description automatic generation means 32
Is the HD of the entire digital circuit without MTCMOS operation
Based on the L description F1 and the MTCMOS related information F2, the input / output signal name of each block to be converted into MTCMOS is extracted, and for each block, “block name”, “input / output signal name”, and “control signal of power cutoff transistor”. Based on the "name", the HDL description F5 of the MTCMOS operation unit of the block to be converted to MTCMOS is automatically generated.

Here, an HDL description F4 of the entire digital circuit, which has been modified to incorporate the HDL description of the MTCMOS operation part of the block to be MTCMOS into the HDL description F1 of the entire digital circuit in which the MTCMOS operation has not been described,
H of the MTCMOS operation part of the block to be converted to MTCMOS
The DL description F5 constitutes the HDL description F3 of the entire digital circuit compatible with MTCMOS operation.

It should be noted that one embodiment of the logical model creating apparatus of the present invention uses a program including contents for causing the computer to function as the upper layer description conversion means 31 and the MTCMOS behavioral description automatic generation means 32. Can be achieved with.

9 to 14 are diagrams for specifically explaining the operation of the embodiment of the logical model creating apparatus of the present invention. FIG. 9 is intended to create a logical model of an HDL description compatible with MTCMOS operation. It is a block diagram of the sample circuit top which does.

In FIG. 9, block1 and block2 are blocks to be converted to MTCMOS, block3 is a block not to be converted to MTCMOS, i1, i2 and i3 are input signals of block1, i4 and i5 are input signals of block2, and i6 and i7 are input of block3. Signal, o1, o2 is block1
, O3 is the output signal of block2, and s1 and s2 are the control signals for the power-off stage transistors.

In the case of this example, the MTC of the sample circuit top
The HDL description F1 in which the MOS operation is not described is described as shown in FIG. 10, and the MTCMOS related information F2 of the sample circuit top is described as shown in FIG.

FIG. 12 is a diagram showing the HDL description F4 output from the upper layer description converting means 31. In the upper layer description converting means 31, the HDL description F1 of the entire digital circuit in which the MTCMOS operation is not described is shown in FIG. Based on the MTCMOS related information F2 shown in FIG.
MT in the HDL description F1 of the entire digital circuit in which no operation is described
MTCMOS of blocks block1 and block2 to be CMOS
An HDL description F4 of the entire digital circuit, which has been modified to incorporate the HDL description of the operation unit, is generated. In this example,
block1_MT obtained by converting block1 into MTCMOS is described as a block in the upper hierarchy of block1, and block2 is MTCMOS.
The converted block2_MT is described as a block in the upper hierarchy of block2.

FIG. 13 is a diagram showing the HDL description F5 output from the MTCMOS behavioral description automatic generation means 32.
In the MTCMOS operation description automatic generation means 32, the HD of the entire digital circuit in which the MTCMOS operation is not described is shown in FIG.
L description F1 and MTCMOS related information F shown in FIG.
Based on 2, the HDL description F5 of the MTCMOS operation unit of the block to be converted to MTCMOS is created as shown in FIG.

Here, the HDL description F4 of the entire digital circuit, which is modified to incorporate the HDL description of the MTCMOS operation unit shown in FIG. 12, and the MTCMOS shown in FIG.
HDL description F5 of the MTCMOS operation part of the integrated block and the HDL of the entire digital circuit compatible with the MTCMOS operation.
The description F3 is configured, and a digital circuit as shown in FIG. 14 is expressed.

As described above, according to the embodiment of the logical model creating apparatus of the present invention, since the upper layer description converting means 31 and the MTCMOS behavioral description automatic generating means 32 are provided, a digital circuit compatible with MTCMOS behavior is provided. A logical model composed of HDL description can be easily created.

[0048]

As described above, according to the logical model creating method of the present invention, even if the hardware description language cannot express the phenomenon that the CMOS circuit to be MTCMOS becomes indefinite due to the power-off, the normal operation can be performed. CM to be converted to MTCMOS without any modification to the description of the CMOS circuit in which the functional level specifications and gate level specifications are described.
A logic simulation is performed at the functional level or the gate level of the entire circuit including the standby state and the operating state of the OS circuit to shorten the time required for the logic verification of the digital circuit including the MTCMOS circuit and improve the accuracy of the logic verification. Can be planned.

Further, according to the logical model creating apparatus of the present invention, it is possible to easily create a logical model composed of a hardware language description compatible with MTCMOS operation from the logical specifications of a digital circuit including a CMOS circuit to be MTCMOS. .

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a logical model creation method of the present invention.

FIG. 2 is a block circuit diagram for specifically explaining block division of a digital circuit for performing logic verification, which is supposed to be performed in one embodiment of the logic model creating method of the present invention.

FIG. 3 is a circuit diagram showing a digital circuit that performs logic verification.

FIG. 4 is a diagram showing a main part of a logical model of the digital circuit shown in FIG. 3 created by applying an embodiment of a logical model creating method of the present invention.

5 is a block circuit diagram showing the contents of the logical model shown in FIG.

FIG. 6 is a flowchart showing a logic verification CAD flow of a digital circuit using an embodiment of the logic model creating method of the present invention.

FIG. 7 is a flowchart showing another implementation example of step S1 of FIG.

FIG. 8 is a configuration diagram of an embodiment of a logical model creation device of the present invention.

FIG. 9 is a configuration diagram of a sample circuit for creating a logical model of HDL description corresponding to MTCMOS operation.

10 is a diagram showing an HDL description in which the MTCMOS operation of the sample circuit shown in FIG. 9 is not described.

11 is a diagram showing MTCMOS related information of the sample circuit shown in FIG. 9;

FIG. 12 is a diagram showing an HDL description output from an upper layer description conversion means included in the logical model creation device of the present invention.

FIG. 13 is an MTC provided in the logical model creation device of the present invention.
It is a figure which shows the HDL description output from the MOS behavioral description automatic generation means.

FIG. 14 is a diagram showing a digital circuit represented by an HDL description of the entire digital circuit compatible with MTCMOS operation.

FIG. 15 is a circuit diagram showing an example of an MTCMOS circuit.

FIG. 16 is a circuit diagram illustrating an example of a digital circuit.

FIG. 17 is a diagram showing an example of a function level description.

FIG. 18 is a diagram showing an example of a gate level description.

[Explanation of symbols]

S1, S2 control signals 28-1, 28-N, 29-1, 29-N 2 to 1 selector

Claims (5)

[Claims] 1. A logical model creating method for creating a logical model of a digital circuit including an MTCMOS circuit in a hardware description language, wherein the MTCMOS circuit is a CM in the MTCMOS circuit.
It is assumed that the digital circuit is hierarchically divided into blocks and described as an upper hierarchical block of an OS circuit, and the specification description of the CMOS circuit describes a logical operation when a power cutoff transistor is turned on. The specification description of the MTCMOS circuit includes a description that a signal value of a signal line connected to an input pin is applied to the input pin during operation, and an undefined value is applied to the input pin during standby. How to create a logical model. 2. The MTCMOS circuit specification description has the CMOS circuit as a lower hierarchical block, and has the same input / output signal as the CMOS circuit, a control signal for the power shutoff transistor, and a signal other than the control signal. The output signals of the MTCMOS circuit have the same number of 2-to-1 selectors as the number of input signals.
The two-to-one selector is connected to a corresponding output signal of the output signals of the CMOS circuit in the circuit, and a corresponding input signal of the input signals other than the control signal is input to one of the selected input terminals. , An undefined value is set in the other selected input terminal, the output terminal is connected to the corresponding input terminal in the input terminals of the CMOS circuit, and the control signal turns on the power cutoff transistor, When the control signal outputs the signal value of the input signal input to the one selected input terminal and turns off the power cutoff transistor, an undefined value set in the other selected input terminal is output. The logical model creating method according to claim 1, further comprising a description indicating that the logical model is to be output. 3. The logic model creating method according to claim 1, wherein the specification description of the CMOS circuit is a gate level description. 4. A logic model creating device for creating a logic model of a digital circuit including a CMOS circuit to be MTCMOS in a hardware description language, wherein the digital circuit is described in a hardware description language in which MTCMOS operation is not described. An upper layer description converting means for converting the description of the upper layer so that the description in the hardware description language of the MTCMOS operation unit of the CMOS circuit can be incorporated in the upper layer portion of the CMOS circuit, and the MTCMOS of the digital circuit. The hardware description language of the MTCMOS operation unit of the CMOS circuit is based on the MTCMOS related information describing the correspondence between the description in the hardware description language in which the operation is not described and the control signal name of the CMOS circuit and the power cutoff transistor. To automatically generate a description in Logical model creating apparatus characterized by having an OS operation description automatic generation means. 5. A CMO for implementing MTCMOS in a computer
A program for creating a logical model of a digital circuit including an S circuit in a hardware description language, wherein the computer is an MTCMOS of the digital circuit.
The MT of the CMOS circuit is added to the upper layer portion of the CMOS circuit being described by the hardware description language in which the operation is not described.
An upper layer description conversion means for converting the description of the upper layer so that the description in the hardware description language of the CMOS operation unit can be incorporated; and a description in the hardware description language of the digital circuit in which the MTCMOS operation is not described. , M that automatically generates a description in the hardware description language of the MTCMOS operation unit of the CMOS circuit based on the MTCMOS related information that describes the correspondence relationship between the CMOS circuit and the control signal name of the power cutoff transistor.
A program including contents for functioning as TCMOS behavior description automatic generation means.