JP2003233350A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JP2003233350A
JP2003233350A JP2002030504A JP2002030504A JP2003233350A JP 2003233350 A JP2003233350 A JP 2003233350A JP 2002030504 A JP2002030504 A JP 2002030504A JP 2002030504 A JP2002030504 A JP 2002030504A JP 2003233350 A JP2003233350 A JP 2003233350A
Authority
JP
Japan
Prior art keywords
signal
power supply
circuit
electrode
signal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002030504A
Other languages
Japanese (ja)
Inventor
Hideki Mine
秀樹 峯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002030504A priority Critical patent/JP2003233350A/en
Publication of JP2003233350A publication Critical patent/JP2003233350A/en
Pending legal-status Critical Current

Links

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by controlling current loss in a step-up circuit of a liquid crystal display device. <P>SOLUTION: The liquid crystal display device always detects an output value of a video signal 16 outputted from a group of signal electrode driving circuits, and compares the difference between the output voltage value of the group of signal electrode driving circuits and the voltage value of the input power source 101, and thereby controls at any time during a single horizontal period whether to drive signal electrodes by the input power source 101 or whether to drive the signal electrodes by the output converted by a D/A converter circuit 14 and amplified by an amplifier circuit 13. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、テレビジョンなど
の映像機器やコンピュータなどの情報機器や携帯電話の
ディスプレイとして有用な液晶表示装置に関する。 【0002】 【従来の技術】(図5)は、近年、よく使用されている
液晶表示装置のブロック図であり、(図4)は、その詳
細図であり、(図3)は、その駆動波形である。 【0003】(図5)において、101は液晶表示装置
に入力される入力電源、102は液晶表示装置に入力さ
れる入力信号、141は制御信号および映像信号を処理
する制御信号回路、144は電源回路制御信号、111
は入力電源101より走査電極および信号電極で使用す
る電源を作成する電源回路、112は信号電極駆動回路
用電源、113は走査電極駆動回路用電源、521は信
号電極駆動回路群、522は信号電極、523は信号電
極駆動回路用信号、531は走査電極駆動回路群、53
2は走査電極、533は走査電極駆動回路用信号、50
9は液晶パネル、18は液晶パネルの画素、である。 【0004】以上のように構成された従来の液晶表示装
置の動作を下記に説明する。 【0005】(図5)に示す従来の液晶表示装置は、液
晶パネル509上に走査電極532と信号電極522が
設けられ、それぞれの交点には画素18が設けられてい
る。この信号電極522と走査電極532をそれぞれ駆
動するのが信号電極駆動回路群521と走査電極駆動回
路群531である。制御信号発生回路141では、入力
信号102に基づき、液晶表示装置に表示する画像を信
号電極駆動回路群521に与える映像信号に加工した
り、信号電極駆動回路群521を制御する制御信号を発
生させたりし、信号電極駆動回路用信号523として、
信号電極駆動回路群521に送り、また、入力信号10
2に基づき、電源回路111を動作させる電源回路制御
信号144を発生させ、電源回路111へ送る。電源回
路111では、電源回路制御信号144により、入力電
圧101を信号電極駆動回路群521と走査電極駆動回
路群533で必要な電源を作成し、それぞれの電極駆動
回路群に送る。 【0006】信号電極駆動回路群521では、電源回路
111よりの信号電極駆動用電源112と制御信号発生
回路141よりの映像信号と制御信号である信号電極駆
動用信号523により、信号電極信号を発生させ、信号
電極522を駆動する。また、走査電極駆動回路群53
1では、電源回路111よりの走査電極駆動用電源11
3と制御信号発生回路141よりの制御信号である走査
電極駆動用信号533により、走査電極信号を発生さ
せ、走査電極532を駆動する。このようにして、発生
した信号電極信号と走査電極信号とで液晶表示装置のそ
れぞれの画素に表示映像を表示させている。 【0007】ここで、(図4)を用いて信号の流れにつ
いてもう少し詳しく下記に説明する。 【0008】(図4)において、101は入力電源、1
02は入力信号、141は制御信号回路、144は電源
回路制御信号、111は電源回路、112は信号電極駆
動回路用電源、142は信号電極駆動回路用制御信号、
421は信号電極駆動回路群出力部、13はアンプ回
路、14はデジタル/アナログ回路(以下、D/A回路
と称す)、15は信号電極駆動回路用電源の昇圧回路
(以下、AVDD昇圧回路と称す)、16は映像信号、
17は信号電極駆動信号、18は画素、である。 【0009】以上のように構成された従来の液晶表示装
置の動作について、上記ではふれなかった映像を表示さ
せる部分についての信号の流れを下記に説明する。 【0010】従来の液晶表示装置の信号電極駆動回路群
521の信号電極駆動回路群出力部421は、D/A回
路14とアンプ回路13とで構成されており、それぞれ
が制御信号発生回路141よりの信号電極駆動回路用制
御信号142に基づき、制御されている。一方、電源回
路111で、入力電源101より、電源回路111内部
のAVDD昇圧回路15で信号電極駆動回路群で使用す
る電源を作成し、信号電極駆動回路群521に供給す
る。これらの電源と信号で、D/A回路14とアンプ回
路13を動作させる。 【0011】ここで、入力信号102よりの信号を制御
信号回路141内の映像信号処理部で信号処理し、液晶
表示装置で使用できるnビットのデジタル信号である映
像信号16を作成し、この映像信号16をD/A回路1
4で、デジタル信号に対応するアナログ量に変換し、そ
のアナログ映像信号をアンプ回路13でアンプし、信号
電極駆動信号17として液晶画素18へ伝送する。ま
た、画素18は、走査電極信号によりオン/オフさせ、
信号電極信号17を導通させたり遮断したりする画素ト
ランジスタと画素電極と対向電極とこの電極間に形成さ
れた液晶層とから構成されている。 【0012】走査電極信号により、画素トランジスタが
オンしている期間、信号電極信号17が画素トランジス
タを導通し画素電極に加えられ、規定された時間で信号
電極信号17側から液晶画素に電荷を蓄積し、信号電極
と対向電極との信号電位差で液晶層のねじれ角を制御
し、次に、走査電極信号により、画素トランジスタをオ
フにさせ、画像情報をホールドする。このような動作を
全ての画素で走査線単位に行うことにより、液晶表示装
置に映像を表示する。 【0013】つぎに、(図3)の信号波形を使用して、
上記で説明した電位差と映像表示についてもう少し、詳
しく説明する。 【0014】(図3)において、22は電源回路部動
作、23は信号電極駆動回路部出力動作、25は昇圧動
作、26は信号電極駆動回路群電源、101は入力電
圧、317は信号電極駆動信号波形、321は信号電極
駆動回路群電源電流、322は入力電源電流、である。 【0015】以上のように構成された波形で従来の液晶
表示装置における信号について説明する。まず、電源回
路111で、入力電圧101をAVDD昇圧回路15
で、電圧レベルを入力電圧101から信号電極駆動回路
群電源26となるように、昇圧動作25が行われ、電圧
値が持ち上げられる。この昇圧された電源を信号電極駆
動回路群のD/A回路14とアンプ回路13に供給し、
それぞれの電源として使用するため、信号電極駆動回路
群の出力信号である信号電極駆動信号波形317は、G
NDレベルであるVSSと電源電圧である信号電極駆動
回路群電源26の間で、D/A回路14に入力されるn
ビットのデジタル映像データで規定された任意の値をと
ることとなる。 【0016】通常、画素トランジスタは、走査電極信号
の”Hi”レベルでオンし、”Lo”レベルでオフす
る。走査電極信号の”Hi”レベルのとき、1水平期間
毎に交流化された対向信号が対向電極に加えられ、対向
信号と同期し、1水平期間毎に交流化された映像信号3
17が、信号レベル負側から信号レベル正側、あるい
は、信号レベル正側から信号レベル負側へと交流化され
るように画素トランジスタを導通し、画素電極に加えら
れる。 【0017】このとき、液晶特性が電圧がかからない状
態で白表示ある場合、液晶表示装置の画素に白を表示し
ようとするならば、対向信号と映像信号の電位差が、0
(V)に近くなるような電圧を加え、液晶層にねじれ角
をほとんど発生しないようにし、逆に、黒を表示しよう
とするならば、対向信号と映像信号の電位差が、大きく
なるように電圧を加え、液晶層にねじれ角を大きくなる
ようにし、中間色を表示しようとするならば、電位差
が、白表示から黒表示の間の任意電位をあたえ、液晶層
にねじれ角を適宜に発生するようにしている。 【0018】 【発明が解決しようとする課題】しかしながら、(図
3)の波形で表示を行っているとき、信号レベル負側か
ら信号レベル正側へ到達するときや、または、信号レベ
ル正側から信号レベル負側へ到達するときは、画素コン
デンサに充電あるいは放電させる電荷つまり電流は、入
力電圧101を昇圧動作25をさせた電圧である信号電
極駆動回路群電源電圧26からすべて供給されるため電
源回路111のAVDD昇圧回路15の昇圧値が大きけ
れば大きいほど入力電圧101に流れる電流は大きくな
る。 【0019】たとえば、信号電極駆動回路群電源26の
値が、入力電圧101の2倍の電圧であった場合、AV
DD昇圧回路15は、入力電圧101を2倍に持ち上げ
るため、逆に、信号電極駆動回路群電源26に流れる電
流は、入力電圧101に換算するとき、2倍になる。入
力電圧をVCC、入力電圧に流れる電流をIVCCと
し、さらに昇圧回路でVCCを昇圧した電圧をAVDD
とし、AVDDに流れる電流をIAVDDとすると、A
VDD=VCC×2倍 となるため、IVCC=IAV
DD×2倍 となる。 【0020】信号電極駆動信号波形の電位が、電位的に
飽和到達するまで、信号電極駆動回路群電源26が電流
を流し続け、信号電極駆動回路群電源電流321のよう
に電位が飽和するまで電流を流し続ける。これにより、
かりに、電源回路111の損失がなかった場合、これを
入力電源101換算すると、入力電源電流322のよう
に信号電極駆動回路群電源電流321の2倍の値をとる
こととなるが、実際は、必ず、電源回路111で損失が
あるため、さらにこの電流が増えることになる。つま
り、信号電極駆動回路群電源26を入力電源101より
昇圧することにより、不必要な電力を消費し続け、液晶
表示装置の消費電力を増やす原因となっている。 【0021】本発明は、かかる点に鑑み、上記の課題と
なる消費電力を抑制する構成とし、低消費電力を実現す
る液晶表示装置を提供することを目的とする。 【0022】 【課題を解決するための手段】上記課題を解決するため
に、本発明は、走査電極と信号電極とがマトリックス状
に形成され、走査電極と信号電極とが交差する1つ1つ
の画素に画素電極が設けられ、画素電極と画素電極に対
向する対向電極との間に液晶層が設けられ、画素電極と
対向電極との電位差で液晶のねじれ角を制御し、映像を
表示する液晶パネルと、走査電極を駆動する走査電極駆
動回路群と、映像信号であるnビットのデジタルの映像
信号をアナログ量に変換するデジタル/アナログ回路
と、変換されたアナログ映像信号を増幅して信号電極に
送り出すアンプ回路とで構成された信号電極駆動回路群
と、走査電極駆動回路群と信号電極駆動回路群とで使用
する電源を、入力電源より昇圧回路で電圧変換し、走査
電極駆動回路群と信号電極駆動回路群とに供給できる電
源回路と、信号電極駆動回路群に電送する映像信号を発
生させ、かつ、走査信号電極回路群と信号電極駆動回路
群と電源回路とに制御信号を送る制御信号回路と、デー
タ信号と制御信号と電源を供給する配線板とを具備する
液晶表示装置であって、信号電極駆動回路群が、電源回
路の昇圧回路で入力電源の電圧値より大きい電圧値を作
りデジタル/アナログ回路とアンプ回路とを駆動し信号
電極に映像信号を送り出している期間に、信号電極駆動
回路群の出力である映像信号の出力値を前記デジタル/
アナログ回路で変換されるデジタルデータ値を常に検出
して、信号電極駆動回路群の出力電圧値と液晶表示装置
の入力電源電圧値との差を比較し、制御信号回路から出
力される制御信号で、入力電源で信号電極を駆動する
か、デジタル/アナログ回路で変換され前記アンプ回路
でアンプされた出力で信号電極を駆動するかを制御し、
信号電極へ送り出す信号を1水平期間内の任意の時間で
切り替えることを特徴とする液晶表示装置である。 【0023】 【発明の実施の形態】以下に本発明をその実施例を示す
図面に基づいて説明する。 【0024】(図1)は、請求項1の実施例の液晶表示
装置の構成図であり、(図2)は、その実施例の信号波
形を示す。 【0025】(図1)において、101は入力電源、1
02は入力信号、141は制御信号回路、142は信号
電極駆動回路用制御信号、144は電源回路制御信号、
111は電源回路、112は信号電極駆動回路用電源、
121は信号電極駆動回路群出力部、11はVCC充電
回路、12はVCC充電制御信号、13はアンプ回路、
14はD/A回路、15はAVDD昇圧回路、16は映
像信号、17は信号電極駆動信号、18は画素、であ
る。 【0026】以上のように構成された液晶表示装置によ
り、本発明の実施例について説明する。 【0027】本発明の液晶表示装置の信号電極駆動回路
群出力部121は、D/A回路14とアンプ回路13と
で構成され、制御信号回路141では、入力信号102
に基づき、表示する画像信号を信号電極に与える信号に
加工した、nビットのデジタル映像信号16と、信号電
極駆動回路群出力部121を制御する信号電極駆動回路
用信号142と、nビットのデジタル映像信号16に応
じてVCC充電回路11を制御するVCC充電制御信号
12と、電源回路111を制御する電源回路制御信号1
44とを作成し、電源回路111では、入力電源101
をAVDD昇圧回路15でD/A回路14とアンプ回路
13に供給する信号電極駆動回路用電源112を作成す
る。 【0028】また、VCC充電回路11では、制御信号
回路141で作成された入力信号102を信号処理し、
信号電極に与える信号に加工した、nビットのデジタル
映像信号16の値と、入力電源101と入力電源101
から作成する信号電極駆動回路用電源112の電圧差つ
まり昇圧差により、入力電源101で信号電極を直接駆
動するか、D/A回路14でnビットのデジタル信号を
アナログ信号に変換し、そのアナログ信号をアンプ回路
13で増幅した信号で駆動するかを、決定するVCC充
電制御信号12で、入力電源101とアンプ回路13の
出力信号である信号とを1水平期間中の任意の規定され
た時間で切り替え、信号電極駆動信号17として、画素
18に電荷を充放電を行える構成となっている。 【0029】つぎに、(図2)の信号波形を使用して、
上記で説明した電源電圧の電位差と、入力電源101で
の駆動とアンプ回路13の出力信号での駆動の任意の規
定された時間内の切り替えについてもう少し、詳しく説
明する。 【0030】(図2)において、22は電源回路部動
作、23は信号電極駆動回路部出力動作、25は昇圧動
作、26は信号電極駆動回路群電源、27はVCC充電
期間、101は入力電圧、211は信号電極駆動信号波
形、221は信号電極駆動回路群電源電流、231は入
力電源電流、である。 【0031】まず、電源回路111で、入力電圧101
をAVDD昇圧回路15で、電圧レベルを入力電源10
1から信号電極駆動回路群電源26となるように、昇圧
動作25が行われ、電圧値が持ち上げられる。ここでは
簡単に、入力電圧101と信号電極駆動回路群電源電圧
26が2倍、つまり、昇圧動作25が2倍であることを
仮定して説明する。 【0032】この2倍に昇圧された電源である信号電極
駆動回路群電源26を信号電極駆動回路群のD/A回路
14とアンプ回路13に供給し、信号電極駆動回路群の
出力信号である信号電極駆動信号波形211は、GND
レベルであるVSSレベルと電源電圧レベルである信号
電極駆動回路群電源26の間で、D/A回路14に入力
されるnビットのデジタルの映像データで規定された任
意の値をとることとなる。 【0033】通常、信号レベル負側から信号レベル正側
へ到達するときや、または、信号レベル正側から信号レ
ベル負側へ到達するときは、画素コンデンサに充電ある
いは放電させる電荷つまり電流は、入力電圧101を昇
圧動作25をさせた電圧である信号電極駆動回路群電源
電圧26からすべて供給され、信号電極駆動回路群電源
電圧26の値が、入力電圧101の値の2倍の電圧であ
るため、AVDD昇圧回路15は、入力電源101の値
の2倍に持ち上げるため、逆に、信号電極駆動電源26
に流れる電流は、入力電源101の値に換算するとき、
2倍になる。つまり、AVDD=VCC×2倍 となる
ため、IVCC=IAVDD×2倍 となる。 【0034】ここで、本発明では、信号レベル負側から
信号レベル正側へ到達するとき、つまり画素コンデンサ
に充電するとき、1水平期間の任意の時間であるVCC
充電期間27の期間は、信号電極駆動信号211の負側
から、入力電源101の電位まで入力電源101で直接
的に画素の充電を行い、1水平期間の残りの期間で、入
力電源101の電位から信号電極駆動信号211の正側
の電位まで、アンプ回路13の出力信号で充電を行うこ
とにより、信号電極駆動信号211が、2段階で充電さ
れたことになる。 【0035】このときの流れる電流値を入力電源101
の値に換算すると、信号電極駆動信号211の負側から
入力電源101の電位までは、入力電源101の1倍の
電流となり、入力電源101の電位から信号電極駆動信
号211の正側の電位までは、信号電極駆動電源26に
流れる電流である信号電極駆動回路群電源電流221
は、入力電源101の値に換算するとき、2倍になる。
これらを合計すると、入力電源電流231のような電流
値になる。つまり、負側からVCC電位までが、IVC
C=IAVDDVCC電位から正側までが、IVCC=
IAVDD×2倍 となる。 【0036】ここで、負側からVCC電位までの電流値
をI1とし、VCC電位から正側までの電流値をI2と
すると、入力電源101に流れる電流は、従来では、
(I1+I2)×2 となり、本発明では、I1+I2
×2 となる。(従来の電流値)−(本発明の電流値)
=I1 となり、I1分の電流を抑制でき、低電力化が
可能となる。 【0037】実際は、必ず電源回路111の昇圧回路で
損失があるため、さらにこの電流が増えることになる
が、入力電源101に対してのみは損失は発生しないこ
とにより、この損失を考慮すると、従来では、(I1+
I2)×2×(1+損失率) となり、本発明では、I
1+I2×2×(1+損失率)となる。(従来の電流
値)−(本発明の電流値)=I1(1+2×損失率分)
となり、I1(1+2×損失率分)の電流を抑制でき、
低電力化が可能となる。 【0038】たいていは損失があるため、損失が大きけ
れば大きいほど、さらなる消費電力を低減できる効果が
大きくなることになる。つまり、信号電極駆動信号21
1を任意の期間であるVCC充電期間27を入力電源1
01とすることにより、常に、入力電源101を昇圧し
た信号電極駆動電源26で駆動するより、不必要な電力
を消費を抑制し、液晶表示装置の消費電力を低減できる
こととなる。 【0039】なお、昇圧を2倍として、本発明実施例を
説明したが、昇圧率は、1以上の数値であればどんな数
値であってもよい。 【0040】さらに、液晶表示装置毎に、信号電極駆動
回路群16の画素への書き込み能力のばらつきや、液晶
の画素17の負荷のばらつきも考慮した、もっとも最適
化なVCC充電期間27を個々に設定できるようにし、
もっとも無駄のない、低電力を実現した液晶表示装置も
実現できる。 【0041】 【発明の効果】以上説明したように、本発明は上記の構
成により、液晶表示装置の昇圧回路での電流ロスを抑制
することができ、その結果、消費電力を抑制することが
可能な液晶表示装置を実現できる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device useful as a display of a video device such as a television, an information device such as a computer, and a mobile phone. 2. Description of the Related Art FIG. 5 is a block diagram of a liquid crystal display device often used in recent years, FIG. 4 is a detailed diagram thereof, and FIG. It is a waveform. In FIG. 5, reference numeral 101 denotes an input power supply input to the liquid crystal display device, 102 denotes an input signal input to the liquid crystal display device, 141 denotes a control signal circuit for processing a control signal and a video signal, and 144 denotes a power supply. Circuit control signal, 111
, A power supply circuit for generating a power supply used for the scanning electrodes and the signal electrodes from the input power supply 101; 112, a power supply for the signal electrode drive circuit; 113, a power supply for the scan electrode drive circuit; 521, a signal electrode drive circuit group; Numeral 523 denotes a signal for a signal electrode driving circuit, 531 denotes a scanning electrode driving circuit group, 53
2 is a scan electrode, 533 is a signal for a scan electrode drive circuit, 50
9 is a liquid crystal panel, and 18 is a pixel of the liquid crystal panel. [0004] The operation of the conventional liquid crystal display device configured as described above will be described below. In the conventional liquid crystal display device shown in FIG. 5, a scanning electrode 532 and a signal electrode 522 are provided on a liquid crystal panel 509, and a pixel 18 is provided at each intersection. The signal electrode driving circuit group 521 and the scanning electrode driving circuit group 531 drive the signal electrode 522 and the scanning electrode 532, respectively. The control signal generation circuit 141 processes an image to be displayed on the liquid crystal display device into a video signal to be provided to the signal electrode drive circuit group 521 or generates a control signal for controlling the signal electrode drive circuit group 521 based on the input signal 102. Or as a signal 523 for a signal electrode drive circuit.
The signal is sent to the signal electrode drive circuit group 521, and the input signal 10
Based on 2, a power supply circuit control signal 144 for operating the power supply circuit 111 is generated and sent to the power supply circuit 111. In the power supply circuit 111, the power supply required for the signal electrode drive circuit group 521 and the scan electrode drive circuit group 533 is generated by the power supply circuit control signal 144, and the input voltage 101 is sent to each of the electrode drive circuit groups. In the signal electrode drive circuit group 521, a signal electrode signal is generated by the signal electrode drive power supply 112 from the power supply circuit 111, the video signal from the control signal generation circuit 141, and the signal electrode drive signal 523 which is a control signal. Then, the signal electrode 522 is driven. Also, the scan electrode drive circuit group 53
1, the scan electrode driving power supply 11 from the power supply circuit 111
3 and a scan electrode driving signal 533 which is a control signal from the control signal generation circuit 141, to generate a scan electrode signal and drive the scan electrode 532. In this way, a display image is displayed on each pixel of the liquid crystal display device by the generated signal electrode signal and scanning electrode signal. Here, the flow of signals will be described in more detail below with reference to FIG. In FIG. 4, reference numeral 101 denotes an input power source,
02 is an input signal, 141 is a control signal circuit, 144 is a power supply circuit control signal, 111 is a power supply circuit, 112 is a power supply for a signal electrode drive circuit, 142 is a control signal for a signal electrode drive circuit,
Reference numeral 421 denotes a signal electrode drive circuit group output unit, 13 denotes an amplifier circuit, 14 denotes a digital / analog circuit (hereinafter, referred to as a D / A circuit), and 15 denotes a booster circuit for a signal electrode drive circuit power supply (hereinafter, referred to as an AVDD booster circuit). , 16 is a video signal,
Reference numeral 17 denotes a signal electrode drive signal, and reference numeral 18 denotes a pixel. [0009] With respect to the operation of the conventional liquid crystal display device configured as described above, a signal flow in a portion for displaying an image not touched in the above will be described below. The signal electrode drive circuit group output section 421 of the signal electrode drive circuit group 521 of the conventional liquid crystal display device comprises a D / A circuit 14 and an amplifier circuit 13, each of which is provided by a control signal generation circuit 141. Is controlled on the basis of the control signal 142 for the signal electrode drive circuit. On the other hand, in the power supply circuit 111, a power supply to be used in the signal electrode drive circuit group by the AVDD booster circuit 15 in the power supply circuit 111 is generated from the input power supply 101 and supplied to the signal electrode drive circuit group 521. The D / A circuit 14 and the amplifier circuit 13 are operated by these power supplies and signals. Here, a signal from the input signal 102 is subjected to signal processing in a video signal processing unit in the control signal circuit 141 to generate a video signal 16 which is an n-bit digital signal usable in a liquid crystal display device. Signal 16 is applied to D / A circuit 1
In step 4, the analog signal is converted into an analog amount corresponding to the digital signal, and the analog video signal is amplified by the amplifier circuit 13 and transmitted to the liquid crystal pixel 18 as a signal electrode drive signal 17. The pixel 18 is turned on / off by a scanning electrode signal,
It comprises a pixel transistor for conducting and blocking the signal electrode signal 17, a pixel electrode, a counter electrode, and a liquid crystal layer formed between the electrodes. In accordance with the scan electrode signal, while the pixel transistor is on, the signal electrode signal 17 conducts the pixel transistor and is applied to the pixel electrode, and charges are accumulated in the liquid crystal pixel from the signal electrode signal 17 side for a specified time. Then, the twist angle of the liquid crystal layer is controlled by the signal potential difference between the signal electrode and the counter electrode, and then the pixel transistor is turned off by the scanning electrode signal to hold the image information. By performing such an operation for each pixel on a scanning line basis, an image is displayed on the liquid crystal display device. Next, using the signal waveform of FIG.
The potential difference and the image display described above will be described in more detail. In FIG. 3, reference numeral 22 denotes a power supply circuit section operation, 23 denotes a signal electrode drive circuit section output operation, 25 denotes a step-up operation, 26 denotes a signal electrode drive circuit group power supply, 101 denotes an input voltage, and 317 denotes a signal electrode drive. A signal waveform, 321 is a signal electrode drive circuit group power supply current, and 322 is an input power supply current. The signals in the conventional liquid crystal display device will be described with the waveforms configured as described above. First, the power supply circuit 111 applies the input voltage 101 to the AVDD booster circuit 15.
Then, the boosting operation 25 is performed so that the voltage level changes from the input voltage 101 to the signal electrode drive circuit group power supply 26, and the voltage value is raised. The boosted power is supplied to the D / A circuit 14 and the amplifier circuit 13 of the signal electrode drive circuit group,
The signal electrode drive signal waveform 317, which is the output signal of the signal electrode drive circuit group,
N input to the D / A circuit 14 between the ND level VSS and the power supply voltage of the signal electrode drive circuit group power supply 26
It takes an arbitrary value defined by the bit digital video data. Normally, the pixel transistor is turned on at the "Hi" level of the scan electrode signal and turned off at the "Lo" level. When the scanning electrode signal is at the “Hi” level, the counter signal converted into AC every one horizontal period is applied to the counter electrode, synchronized with the counter signal, and the video signal 3 converted into AC every one horizontal period is output.
17 conducts the pixel transistor so that the signal level is changed from the negative signal level to the positive signal level or from the positive signal level to the negative signal level, and is applied to the pixel electrode. At this time, if the liquid crystal characteristics are white with no voltage applied, and if it is desired to display white on the pixels of the liquid crystal display device, the potential difference between the opposing signal and the video signal becomes zero.
(V) is applied so that a twist angle is hardly generated in the liquid crystal layer. Conversely, if black is to be displayed, the voltage is set so that the potential difference between the opposing signal and the video signal becomes large. To increase the twist angle in the liquid crystal layer, and if an intermediate color is to be displayed, the potential difference is given an arbitrary potential between white display and black display, and the twist angle is appropriately generated in the liquid crystal layer. I have to. However, when displaying with the waveform of FIG. 3, when the signal level reaches the signal level from the negative side, or when the signal level reaches the positive side, When the signal level reaches the negative side, the electric charge for charging or discharging the pixel capacitor, that is, the current, is supplied from the signal electrode drive circuit group power supply voltage 26 which is the voltage obtained by performing the boosting operation 25 on the input voltage 101. The larger the boost value of the AVDD boost circuit 15 of the circuit 111, the larger the current flowing to the input voltage 101. For example, when the value of the signal electrode drive circuit group power supply 26 is twice the input voltage 101,
Since the DD boosting circuit 15 doubles the input voltage 101, the current flowing through the signal electrode drive circuit group power supply 26 is doubled when converted to the input voltage 101. The input voltage is VCC, the current flowing through the input voltage is IVCC, and the voltage obtained by boosting VCC by the booster circuit is AVDD.
Suppose that the current flowing through AVDD is IAVDD,
Since VDD = VCC × 2 times, IVCC = IAV
DD × 2. Until the potential of the signal electrode drive signal waveform reaches potential saturation, the signal electrode drive circuit group power supply 26 continues to flow current until the potential is saturated like the signal electrode drive circuit group power supply current 321. Keep flowing. This allows
When the power supply circuit 111 has no loss, when converted to the input power supply 101, the value becomes twice the value of the signal electrode drive circuit group power supply current 321 like the input power supply current 322. Since the power supply circuit 111 has a loss, the current further increases. In other words, by boosting the signal electrode drive circuit group power supply 26 from the input power supply 101, unnecessary power continues to be consumed, causing an increase in power consumption of the liquid crystal display device. In view of the foregoing, it is an object of the present invention to provide a liquid crystal display device having a configuration for suppressing power consumption, which is the above problem, and realizing low power consumption. In order to solve the above-mentioned problems, the present invention provides a method in which a scanning electrode and a signal electrode are formed in a matrix, and the scanning electrode and the signal electrode intersect each other. A pixel is provided with a pixel electrode, a liquid crystal layer is provided between the pixel electrode and a counter electrode facing the pixel electrode, and a liquid crystal for displaying an image by controlling a twist angle of the liquid crystal by a potential difference between the pixel electrode and the counter electrode. A panel, a scan electrode drive circuit group for driving the scan electrodes, a digital / analog circuit for converting an n-bit digital video signal, which is a video signal, into an analog amount, and a signal electrode for amplifying the converted analog video signal. The power supply used by the signal electrode drive circuit group composed of an amplifier circuit and the scan electrode drive circuit group and the signal electrode drive circuit group, which is sent to the A power supply circuit capable of supplying the driving circuit group and the signal electrode driving circuit group, and a video signal to be transmitted to the signal electrode driving circuit group, and controlled by the scanning signal electrode circuit group, the signal electrode driving circuit group, and the power supply circuit What is claimed is: 1. A liquid crystal display device comprising: a control signal circuit for transmitting a signal; and a wiring board for supplying a data signal, a control signal, and power. During a period in which a large voltage value is generated and the digital / analog circuit and the amplifier circuit are driven to send a video signal to the signal electrode, the output value of the video signal output from the signal electrode drive circuit group is converted to the digital / analog signal.
The digital data value converted by the analog circuit is always detected, the difference between the output voltage value of the signal electrode drive circuit group and the input power supply voltage value of the liquid crystal display device is compared, and a control signal output from the control signal circuit is used. Controlling whether to drive the signal electrode with an input power supply or to drive the signal electrode with an output converted by a digital / analog circuit and amplified by the amplifier circuit;
A liquid crystal display device characterized in that a signal sent to a signal electrode is switched at an arbitrary time within one horizontal period. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, and FIG. 2 shows signal waveforms of the embodiment. In FIG. 1, reference numeral 101 denotes an input power source;
02 is an input signal, 141 is a control signal circuit, 142 is a control signal for a signal electrode drive circuit, 144 is a power supply circuit control signal,
111 is a power supply circuit, 112 is a power supply for a signal electrode drive circuit,
121 is a signal electrode drive circuit group output unit, 11 is a VCC charging circuit, 12 is a VCC charging control signal, 13 is an amplifier circuit,
14 is a D / A circuit, 15 is an AVDD booster circuit, 16 is a video signal, 17 is a signal electrode drive signal, and 18 is a pixel. An embodiment of the present invention will be described with reference to the liquid crystal display device configured as described above. The signal electrode drive circuit group output section 121 of the liquid crystal display device according to the present invention comprises a D / A circuit 14 and an amplifier circuit 13.
An n-bit digital video signal 16, a signal electrode driving circuit signal 142 for controlling the signal electrode driving circuit group output section 121, and an n-bit digital signal. A VCC charge control signal 12 for controlling the VCC charge circuit 11 according to the video signal 16 and a power supply circuit control signal 1 for controlling the power supply circuit 111
44, and the input power 101
Is supplied to the D / A circuit 14 and the amplifier circuit 13 by the AVDD booster circuit 15 to generate a power supply 112 for a signal electrode drive circuit. The VCC charging circuit 11 processes the input signal 102 generated by the control signal circuit 141,
The value of the n-bit digital video signal 16 processed into a signal to be applied to the signal electrode, the input power supply 101 and the input power supply 101
A signal electrode is directly driven by the input power supply 101 or an n-bit digital signal is converted into an analog signal by the D / A circuit 14 according to a voltage difference, that is, a boost difference of the signal electrode drive circuit power supply 112 created from The VCC charge control signal 12 determines whether the signal is driven by the signal amplified by the amplifier circuit 13, and the input power supply 101 and the signal that is the output signal of the amplifier circuit 13 are arbitrarily defined for one horizontal period. And the pixel 18 can be charged and discharged as the signal electrode drive signal 17. Next, using the signal waveform of FIG.
The potential difference between the power supply voltages described above and the switching between the driving by the input power supply 101 and the driving by the output signal of the amplifier circuit 13 within an arbitrary prescribed time will be described in more detail. In FIG. 2, reference numeral 22 denotes a power supply circuit section operation, 23 denotes a signal electrode drive circuit section output operation, 25 denotes a step-up operation, 26 denotes a signal electrode drive circuit group power supply, 27 denotes a VCC charging period, and 101 denotes an input voltage. , 211 are signal electrode drive signal waveforms, 221 is a signal electrode drive circuit group power supply current, and 231 is an input power supply current. First, an input voltage 101
AVDD booster circuit 15 sets the voltage level to input power supply 10
The boosting operation 25 is performed so that the signal electrode driving circuit group power source 26 changes from 1 to increase the voltage value. Here, the description will be made simply on the assumption that the input voltage 101 and the signal electrode drive circuit group power supply voltage 26 are double, that is, the boosting operation 25 is double. The signal electrode drive circuit group power supply 26, which is a power supply that has been boosted twice, is supplied to the D / A circuit 14 and the amplifier circuit 13 of the signal electrode drive circuit group, and is an output signal of the signal electrode drive circuit group. The signal electrode drive signal waveform 211 is GND
An arbitrary value defined by n-bit digital video data input to the D / A circuit 14 is taken between the VSS level which is the level and the signal electrode driving circuit group power supply 26 which is the power supply voltage level. . Normally, when the signal level reaches the signal level positive side from the signal level negative side, or when the signal level reaches the signal level negative side from the signal level positive side, the electric charge to be charged or discharged to the pixel capacitor, that is, the current, is input. The voltage 101 is all supplied from the signal electrode drive circuit group power supply voltage 26 which is a voltage obtained by performing the boosting operation 25, and the value of the signal electrode drive circuit group power supply voltage 26 is twice the value of the input voltage 101. , AVDD booster circuit 15 has a signal electrode driving power supply 26
Is converted to the value of the input power supply 101,
Double. That is, since AVDD = VCC × 2 times, IVCC = IAVDD × 2 times. Here, in the present invention, when the signal level reaches the signal level negative side from the negative side, that is, when the pixel capacitor is charged, VCC which is an arbitrary time within one horizontal period is used.
In the charging period 27, the pixels are directly charged by the input power supply 101 from the negative side of the signal electrode drive signal 211 to the potential of the input power supply 101, and the potential of the input power supply 101 is maintained in the remaining period of one horizontal period. Is charged from the output signal of the amplifier circuit 13 to the potential on the positive side of the signal electrode drive signal 211, the signal electrode drive signal 211 is charged in two stages. The value of the flowing current at this time is
When the value is converted into the value, the current from the negative side of the signal electrode drive signal 211 to the potential of the input power supply 101 becomes a current that is one time of the input power supply 101, and from the potential of the input power supply 101 to the potential on the positive side of the signal electrode drive signal 211. Is a signal electrode drive circuit group power supply current 221 which is a current flowing through the signal electrode drive power supply 26.
Is doubled when converted to the value of the input power supply 101.
When these are summed, a current value like the input power supply current 231 is obtained. That is, from the negative side to the VCC potential, the IVC
C = IVCC = VCC potential to the positive side, IVCC =
IAVDD × 2 times. Here, assuming that the current value from the negative side to the VCC potential is I1 and the current value from the VCC potential to the positive side is I2, the current flowing through the input power supply 101 is conventionally
(I1 + I2) × 2, and in the present invention, I1 + I2
× 2. (Conventional current value)-(Current value of the present invention)
= I1, the current for I1 can be suppressed, and the power consumption can be reduced. Actually, since the loss always occurs in the booster circuit of the power supply circuit 111, this current further increases. However, no loss occurs only in the input power supply 101. Then, (I1 +
I2) × 2 × (1 + loss rate).
1 + I2 × 2 × (1 + loss rate). (Conventional current value)-(Current value of the present invention) = I1 (1 + 2 × the loss rate)
And the current of I1 (1 + 2 × the loss rate) can be suppressed,
Low power can be achieved. Since there is usually a loss, the greater the loss, the greater the effect of further reducing power consumption. That is, the signal electrode drive signal 21
1 is a VCC charging period 27 which is an arbitrary period
By setting the value to 01, unnecessary power consumption can be suppressed and the power consumption of the liquid crystal display device can be reduced as compared with the case where the input power supply 101 is always driven by the boosted signal electrode driving power supply 26. Although the embodiment of the present invention has been described with the boosting being doubled, the boosting ratio may be any value as long as it is a value of 1 or more. Further, for each liquid crystal display device, the most optimal VCC charging period 27 is individually considered in consideration of the variation in the writing capability of the signal electrode drive circuit group 16 to the pixels and the variation in the load of the pixels 17 of the liquid crystal. So that it can be set,
The least wasteful liquid crystal display device with low power consumption can be realized. As described above, according to the present invention, current loss in the booster circuit of the liquid crystal display device can be suppressed by the above configuration, and as a result, power consumption can be suppressed. Liquid crystal display device can be realized.

【図面の簡単な説明】 【図1】本発明の実施例における液晶表示装置の構成を
示す図 【図2】本発明の実施例における液晶表示装置の信号波
形を示す図 【図3】従来の液晶表示装置の信号波形を示す図 【図4】従来の液晶表示装置の詳細構成図 【図5】従来の液晶表示装置の全体構成図 【符号の説明】 11 VCC充電回路 12 VCC充電制御信号 13 アンプ回路 14 D/A回路 15 AVDD昇圧回路 16 映像信号 17 信号電極駆動信号 18 画素 22 電源回路部動作 23 信号電極駆動回路部出力動作 25 昇圧動作 26 信号電極駆動回路群電源 27 VCC充電期間 101 入力電源 102 入力信号 141 制御信号回路 142 信号電極駆動回路用制御信号 144 電源回路制御信号 111 電源回路 112 信号電極駆動回路用電源 121 信号電極駆動回路群出力部 211 信号電極駆動信号波形 221 信号電極駆動回路群電源電流 231 入力電源電流
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a configuration of a liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a signal waveform of the liquid crystal display device according to an embodiment of the present invention. FIG. 4 is a diagram showing a signal waveform of a liquid crystal display device. FIG. 4 is a detailed configuration diagram of a conventional liquid crystal display device. FIG. 5 is an overall configuration diagram of a conventional liquid crystal display device. Description of reference numerals 11 VCC charging circuit 12 VCC charging control signal 13 Amplifier circuit 14 D / A circuit 15 AVDD booster circuit 16 Video signal 17 Signal electrode drive signal 18 Pixel 22 Power supply circuit section operation 23 Signal electrode drive circuit section output operation 25 Boosting operation 26 Signal electrode drive circuit group power supply 27 VCC charging period 101 Input Power supply 102 Input signal 141 Control signal circuit 142 Signal electrode drive circuit control signal 144 Power supply circuit control signal 111 Power supply circuit 112 Signal electrode drive circuit power supply 121 No. electrode drive circuits output unit 211 the signal electrode driving signal waveform 221 signal electrode driving circuits supply current 231 input supply current

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) G09G 3/20 G09G 3/20 612G 612U 623 623D Fターム(参考) 2H093 NC02 NC11 NC13 NC16 ND39 5C006 AA01 AC21 AF45 AF69 AF71 AF82 BB16 BC12 BF14 BF25 BF42 BF46 FA47 5C080 AA10 BB05 DD26 FF11 GG08 JJ02 JJ04 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 G09G 3/20 612G 612U 623 623D F-term (Reference) 2H093 NC02 NC11 NC13 NC16 ND39 5C006 AA01 AC21 AF45 AF69 AF71 AF82 BB16 BC12 BF14 BF25 BF42 BF46 FA47 5C080 AA10 BB05 DD26 FF11 GG08 JJ02 JJ04

Claims (1)

【特許請求の範囲】 【請求項1】 走査電極と信号電極とがマトリックス状
に形成され、前記走査電極と前記信号電極とが交差する
1つ1つの画素に画素電極が設けられ、前記画素電極と
前記画素電極に対向する対向電極との間に液晶層が設け
られ、前記画素電極と前記対向電極との電位差で液晶の
ねじれ角を制御し、映像を表示する液晶パネルと、前記
走査電極を駆動する走査電極駆動回路群と、映像信号で
あるnビットのデジタルの映像信号をアナログ量に変換
するデジタル/アナログ回路と、変換されたアナログ映
像信号を増幅して信号電極に送り出すアンプ回路とで構
成された信号電極駆動回路群と、前記走査電極駆動回路
群と前記信号電極駆動回路群とで使用する電源を、入力
電源より昇圧回路で電圧変換し、前記走査電極駆動回路
群と前記信号電極駆動回路群とに供給できる電源回路
と、前記信号電極駆動回路群に電送する映像信号を発生
させ、かつ、前記走査信号電極回路群と前記信号電極駆
動回路群と前記電源回路とに制御信号を送る制御信号回
路と、データ信号と制御信号と電源を供給する配線板
と、を具備する液晶表示装置であって、前記信号電極駆
動回路群が、前記電源回路の昇圧回路で前記入力電源の
電圧値より大きい電圧値を作り前記デジタル/アナログ
回路と前記アンプ回路とを駆動し前記信号電極に映像信
号を送り出している期間に、前記信号電極駆動回路群の
出力である映像信号の出力値を前記デジタル/アナログ
回路で変換されるデジタルデータ値を常に検出して、前
記信号電極駆動回路群の出力電圧値と液晶表示装置の入
力電源電圧値との差を比較し、前記制御信号回路から出
力される制御信号で、前記入力電源で信号電極を駆動す
るか、デジタル/アナログ回路で変換され前記アンプ回
路でアンプされた出力で信号電極を駆動するかを制御
し、信号電極へ送り出す信号を1水平期間内の任意の時
間で切り替えることを特徴とする液晶表示装置。
Claims: 1. A scanning electrode and a signal electrode are formed in a matrix, and a pixel electrode is provided for each pixel where the scanning electrode and the signal electrode intersect. A liquid crystal layer is provided between the pixel electrode and a counter electrode facing the pixel electrode, and controls a twist angle of liquid crystal by a potential difference between the pixel electrode and the counter electrode. A scanning electrode driving circuit group to be driven, a digital / analog circuit for converting an n-bit digital video signal which is a video signal into an analog amount, and an amplifier circuit for amplifying the converted analog video signal and sending it to the signal electrode. A power supply used in the configured signal electrode drive circuit group, the scan electrode drive circuit group, and the signal electrode drive circuit group is voltage-converted from an input power supply by a booster circuit, and the scan electrode drive circuit A power supply circuit capable of supplying a power supply to the group and the signal electrode drive circuit group; a video signal to be transmitted to the signal electrode drive circuit group; and the scan signal electrode circuit group, the signal electrode drive circuit group, and the power supply circuit. And a wiring board for supplying a data signal, a control signal, and a power supply, and the signal electrode drive circuit group is a booster circuit of the power supply circuit. A video signal which is an output of the signal electrode drive circuit group during a period in which a voltage value larger than the voltage value of the input power supply is generated and the digital / analog circuit and the amplifier circuit are driven to send a video signal to the signal electrode; Is always detected by the digital / analog circuit, and the difference between the output voltage value of the signal electrode driving circuit group and the input power supply voltage value of the liquid crystal display device is calculated. A control signal output from the control signal circuit controls whether the signal electrode is driven by the input power supply or the signal electrode is driven by an output converted by a digital / analog circuit and amplified by the amplifier circuit. A liquid crystal display device wherein a signal to be sent to a signal electrode is switched at an arbitrary time within one horizontal period.
JP2002030504A 2002-02-07 2002-02-07 Liquid crystal display device Pending JP2003233350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002030504A JP2003233350A (en) 2002-02-07 2002-02-07 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002030504A JP2003233350A (en) 2002-02-07 2002-02-07 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JP2003233350A true JP2003233350A (en) 2003-08-22

Family

ID=27774235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002030504A Pending JP2003233350A (en) 2002-02-07 2002-02-07 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JP2003233350A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100452136C (en) * 2005-06-29 2009-01-14 恩益禧电子股份有限公司 Driver unit for display panel and nonvolatile memory
US7489262B2 (en) 2006-04-18 2009-02-10 Samsung Electronics Co., Ltd. Digital to analog converter having integrated level shifter and method for using same to drive display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100452136C (en) * 2005-06-29 2009-01-14 恩益禧电子股份有限公司 Driver unit for display panel and nonvolatile memory
US7489262B2 (en) 2006-04-18 2009-02-10 Samsung Electronics Co., Ltd. Digital to analog converter having integrated level shifter and method for using same to drive display device

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